74ABT834D

Philips Semiconductors Advanced BiCMOS Products Objective specification Octal inverting transceiver with parity generator/checker (3–State) 74ABT834 FEATURES • Low static and dynamic power dissipation with high speed and high output drive power dissipation with high speed and high output drive. The 74ABT834 is an octal inverting transceiver with a parity generator/checker and is intended for bus–oriented applications. When Output Enable A (OEA) is High, it will place the A outputs in a high impedance state. Output Enable B (OEB) controls the B outputs in the same way. The parity generator creates an odd parity output (PARITY) when OEB is Low. When OEA is Low, the parity of the B port, including the PARITY input, is checked for odd parity. When an error is detected, the error data is • Open–collector ERROR output • Output capability: +64mA/–32mA • Latch–up protection exceeds 500mA per Jedec JC40.2 Std 17 sent to the input of a storage register. If a Low–to–High transition happens at the clock input (CP), the error data is stored in the register and the Open–collector error flag (ERROR) will go Low. The error flag register is cleared with a Low pulse on the CLEAR input. If both OEA and OEB are Low, data will flow from the A bus to the B bus and the part is forced into an error condition which creates an inverted PARITY output. This error condition can be used by the designer for system diagnostics. • ESD protection exceeds 2000 V per MIL STD 883C Method 3015.6 and 200 V per Machine Model • Power up/down 3–State DESCRIPTION The 74ABT834 high–performance BiCMOS device combines low static and dynamic QUICK REFERENCE DATA SYMBOL tPLH tPHL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay An to Bn or Bn to An Propagation delay An to PARITY Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 5V CL = 50pF; VCC = 5V VI = 0V or VCC VI = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 3.4 7.4 4 7 50 UNIT ns ns pF pF µA ORDERING INFORMATION PACKAGES 24–pin plastic DIP (300mil) 24–pin plastic SOL (300mil) CONDITIONS Tamb = 25°C; GND = 0V –40°C to +85°C –40°C to +85°C ORDER CODE 74ABT834N 74ABT834D PIN CONFIGURATION LOGIC SYMBOL OEA 1 24 V CC 23 B0 22 B1 21 B2 20 B3 14 19 B4 18 B5 17 B6 16 B7 15 PARITY 14 OEB 13 CP TOP VIEW 23 22 21 20 19 18 17 16 1 11 13 A0 A1 A2 A3 A4 A5 A6 A7 OEB OEA CLEAR CP B0 B1 B2 B3 B4 B5 B6 B7 PARITY ERROR 15 10 2 3 4 5 6 7 8 9 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 ERROR 10 CLEAR 11 GND 12 June 9, 1992 1 Philips Semiconductors Advanced BiCMOS Products Objective specification Octal inverting transceiver with parity generator/checker (3–State) 74ABT834 PIN DESCRIPTION SYMBOL A0 – A7 B0 – B7 OEA OEB PARITY ERROR CLEAR CP GND VCC PIN NUMBER 2, 3, 4, 5, 6, 7, 8, 9 23, 22, 21, 20, 19, 18, 17, 16 1 14 15 10 11 13 12 24 NAME AND FUNCTION A port 3–State inputs/outputs B port 3–State inputs/outputs Enables the A outputs when Low Enables the B outputs when Low Parity output Error output Clears the error flag register when Low Clock input Ground (0V) Positive supply voltage FUNCTION TABLE INPUTS MODE A data to B bus and generate odd parity output B data to A bus and check for parity error1 A bus and B bus disabled2 A data to B bus and generate inverted parity output OEB L H H L OEA H L H L An Σ of Highs Odd Even NA (output) X Odd Even Bn + Parity Σ of Lows NA (output) Odd Even X NA (output) An NA (input) Bn Z NA (input) OUTPUTS Bn An NA (input) Z An PARITY H L NA (input) Z L H NOTES: 1. Error checking is detailed in the Error Flag Function Table below. 2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd. ERROR FLAG FUNCTION TABLE INPUTS MODE CLEAR H H H H L High voltage level steady state Low voltage level steady state Don’t care Not applicable No change High impedance ”off” state Low–to–High clock transition Not a Low–to–High clock transition CP ↑ ↑ X ↑ X Bn + Parity Σ of Lows Odd Even X X X Internal node Point ”P” H L X X X Output Pre–state ERRORn–1 H X L X X ERROR OUTPUT H L L NC H Sample Hold Clear H L X NA NC Z ↑ ↑ = = = = = = = = June 9, 1992 2 Philips Semiconductors Advanced BiCMOS Products Objective specification Octal inverting transceiver with parity generator/checker (3–State) 74ABT834 LOGIC DIAGRAM 8 A0 – A7 8 B0 – B7 8 OEB PARITY OEA 8 8 MUX 9–bit Odd Parity Tree ”P” A } } B 9 Sel A/B D CP CLEAR R ERROR ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING –0.5 to +7.0 –18 –1.2 to +7.0 –50 –0.5 to +5.5 128 –65 to 150 UNIT V mA V mA V mA °C DC output diode current DC output voltage3 DC output current Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. 2. The performance capability of a high–performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. June 9, 1992 3 Philips Semiconductors Advanced BiCMOS Products Objective specification Octal inverting transceiver with parity generator/checker (3–State) 74ABT834 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Min VCC VI VIH VIL VOH IOH IOL ∆t/∆v Tamb DC supply voltage Input voltage High–level input voltage Input voltage High–level output voltage, ERROR High–level output current Low–level output current Input transition rise or fall rate Operating free–air temperature range 0 –40 4.5 0 2.0 0.8 5.5 –32 64 5 +85 LIMITS Max 5.5 VCC V V V V V mA mA ns/V °C UNIT DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Min VIK IOH Input clamp voltage High–level output current ERROR ONLY VCC = 4.5V; IIK = –18mA VCC = 5.5V; VOH = 5.5V; VI = VIL or VIH VCC = 4.5V; IOH = –3mA; VI = VIL or VIH VOH High–level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or VIH VCC = 4.5V; IOH = –32mA; VI = VIL or VIH VOL II Low–level output voltage Input leakage current IIH + IOZH IIL + IOZL IO ICCH ICCL ICCZ ∆ICC Additional supply current per input pin2 Quiescent supply current Control pins Data pins VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; VI = GND or 5.5V VCC = 5.5V; VI = GND or 5.5V VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3–State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND –50 2.5 3.0 2.0 3.5 4.0 2.6 0.42 ±0.01 ±5 5.0 –5.0 –80 50 20 50 0.3 0.55 ±1.0 ±100 50 –50 –180 250 30 250 1.5 –50 Typ –0.9 Max –1.2 20 2.5 3.0 2.0 0.55 ±1.0 ±100 50 –50 –180 250 30 250 1.5 Tamb = –40°C to +85°C Min Max –1.2 20 V µA V V V V µA µA µA µA mA µA mA µA mA UNIT 3–State output High current 3–State output Low current Output current1 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. June 9, 1992 4 Philips Semiconductors Advanced BiCMOS Products Objective specification Octal inverting transceiver with parity generator/checker (3–State) 74ABT834 AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORMS Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay An to Bn or Bn to An Propagation delay An to PARITY Propagation delay OEA to PARITY Propagation delay CLEAR to ERROR Propagation delay CP to ERROR Output enable time OEA to An or OEB to Bn, PARITY Output disable time OEA to An or OEB to Bn, PARITY 2 1, 2 1, 2 5 1 3, 4 3, 4 Tamb = +25oC VCC = +5.0V Typ Max Tamb = –40 to +85oC VCC = +5.0V ±10% Min Max ns ns ns ns ns ns ns UNIT AC SETUP REQUIREMENTS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORMS Min ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Setup time, High or Low Bn or PARITY to CP Hold time, High or Low Bn or PARITY to CP Pulse width, High or Low CP Pulse width, Low CLEAR Recovery time CLEAR to CP 6 6 6 5 5 Tamb = +25oC VCC = +5.0V Typ Max Tamb = –40 to +85oC VCC = +5.0V ±10% Min Max ns ns ns ns ns UNIT June 9, 1992 5 Philips Semiconductors Advanced BiCMOS Products Objective specification Octal inverting transceiver with parity generator/checker (3–State) 74ABT834 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V INPUT VM tPHL VM tPLH VM VM INPUT VM tPLH VM tPHL VM VM OUTPUT OUTPUT Waveform 1. Propagation Delay For Inverting Output Waveform 2. Propagation Delay For Non–Inverting Output OEA, OEB VM tPZH VM tPHZ VOH –0.3V 0V OEA, OEB VM tPZL VM tPLZ OUTPUT VM OUTPUT VM VOL +0.3V 0V Waveform 3. 3–State Output Enable Time to High Level and Output Disable Time from High Level Waveform 4. 3–State Output Enable Time to Low Level and Output Disable Time from Low Level CLEAR VM tw(L) V M tREC VM tPLH Bn, PARITY VM VM CP ts(H) ERROR VM CP VM Waveform 5. CLEAR Pulse Width, CLEAR to ERROR Delay and CLEAR to Clock Recovery Time Waveform 6. Data Setup and Hold Times and Clock Pulse Width NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. June 9, 1992 6 ÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉÉÉÉ É VM VM th(H) ts(L) th(L) tw(H) tw(L) VM VM ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ Philips Semiconductors Advanced BiCMOS Products Objective specification Octal inverting transceiver with parity generator/checker (3–State) 74ABT834 TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS 18 16 14 12 tPLH 10 8 6 4 tPHL 2 0 0 100 200 300 400 500 600 Propagation delay (ns) Load resistor (Ω) NOTE: When using Open–Collector parts, the value of the pull–up resistor greatly affects the value of the tPLH. For example, changing the specified pull–up resistor value from 500Ω to 100Ω will improve the tPLH over 300% with only a slight change in the tPHL. However, if the value of the pull–up resistor is changed, the user must make certain that the total IOL current through the resistor and the total IIL’s of the receivers does not exceed the IOL maximum specification. TEST CIRCUIT AND WAVEFORM VCC VX VIN D.U.T RT CL RL VOUT RX 90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90% tW VM 10% 90% AMP (V) 0V tTLH (tR) tTHL (tF) 90% VM 10% tW 0V AMP (V) PULSE GENERATOR Test Circuit for 3–State Outputs POSITIVE PULSE 10% VM SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open LOAD VALUES OUTPUT ERROR All other RX VX 100Ω VCC 500Ω 7.0V VM = 1.5V Input Pulse Definition DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns June 9, 1992 7