74ABT845N

Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 FEATURES • High speed parallel latches • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors DESCRIPTION The 74ABT845 consists of eight D-type latches with 3-State outputs. In addition to the LE, OE, MR and PRE pins, the 74ABT845 has two additional OE pins, making a total of three Output Enable (OE0, OE1, OE2) pins. The multiple Output enables allow multiuser control of the interface, e.g., CS, DMA, and RD/WR. • Broadside pinout • Output capability: +64mA/–32mA • Power-up 3-State • Power-up reset • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model QUICK REFERENCE DATA SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay Dn to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC = 5.5V TYPICAL 5.4 4 7 500 UNIT ns pF pF nA ORDERING INFORMATION PACKAGES 24-Pin Plastic DIP 24-Pin plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C OUTSIDE NORTH AMERICA 74ABT845 N 74ABT845 D 74ABT845 DB 74ABT845 PW NORTH AMERICA 74ABT845 N 74ABT845 D 74ABT845 DB 74ABT845PW DH DWG NUMBER SOT222-1 SOT137-1 SOT340-1 SOT355-1 PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL OE0 – OE2 D0-D7 Q0-Q7 MR LE PRE GND VCC FUNCTION Output enable inputs (active-Low) Data inputs Data outputs Master reset input (active-Low) Latch enable input (active-High) Preset input (active-Low) Ground (0V) Positive supply voltage OE0 OE1 D0 D1 D2 D3 D4 D5 D6 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 15 14 13 TOP VIEW VCC OE2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PRE LE 1, 2, 23 3, 4, 5, 6, 7, 8, 9, 10 22, 21, 20, 19,18, 17, 16, 15 11 13 14 12 24 D7 10 MR 11 GND 12 SA00258 1995 Sep 06 1 853-1703 15702 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 LOGIC SYMBOL (IEEE/IEC) LOGIC SYMBOL 1 2 23 14 11 13 & EN 3 4 5 6 7 8 9 10 S2 R C1 13 14 11 D0 D1 D2 D3 D4 D5 D6 D7 LE PRE MR OE0 OE1 OE2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 3 4 5 6 7 8 9 10 1D 2 22 21 20 19 18 17 16 15 1 2 23 22 21 20 19 18 17 16 15 SA00260 SA00259 FUNCTION TABLE INPUTS OE n L L L L L L H L PR E L H H H H H X H MR X L H H H H X H LE X X H H ↓ ↓ X L Dn X X L H l h X X OUTPU TS Qn H L L H L H Z NC Preset Clear Transparent Latched High impedance Hold OPERATING MODE H = High voltage level h = High voltage level one set-up time prior to the High-to-Low LE transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low LE transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low transition LOGIC DIAGRAM D0 3 14 PRE D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 P D D P D P D P D P D P D P D P L 11 MR C Q L C Q L C Q L C Q L C Q L C Q L C Q L C Q 13 LE 1 OE0 2 OE1 OE2 23 22 Q0 21 Q1 20 Q2 19 Q3 18 Q4 17 Q5 16 Q6 15 Q7 SA00261 1995 Sep 06 2 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 ABSOLUTE MAXIMUM RATINGS1,2 SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING –0.5 to +7.0 –18 –1.2 to +7.0 –50 –0.5 to +5.5 128 –65 to 150 UNIT V mA V mA V mA °C DC output diode current DC output voltage3 DC output current Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Min VCC VI VIH VIL IOH IOL ∆t/∆v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 –40 4.5 0 2.0 0.8 –32 64 5 +85 LIMITS Max 5.5 VCC V V V V mA mA ns/V °C UNIT 1995 Sep 06 3 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Min VIK Input clamp voltage VCC = 4.5V; IIK = –18mA VCC = 4.5V; IOH = –3mA; VI = VIL or VIH VOH High–level output voltage VCC = 5.0V; IOH = –3mA; VI = VIL or VIH VCC = 4.5V; IOH = –32mA; VI = VIL or VIH VOL VRST II IOFF IPU/PD IOZH IOZL ICEX IO ICCH ICCL ICCZ ∆ICC Additional supply current per input pin2 Quiescent supply current Low–level output voltage Power-up output low voltage3 Input leakage current Power-off leakage current Power-up/down 3-state output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI ≤ 4.5V VCC = 2.1V; VO = 0.5V; V OE = VCC; VI = GND or VCC VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND –50 2.5 3.0 2.0 Typ –0.9 2.9 3.4 2.4 0.42 0.13 ±0.01 ±5.0 ±5.0 5.0 –5.0 5.0 –80 0.5 24 0.5 0.5 0.55 0.55 ±1.0 ±100 ±50 50 –50 50 –180 250 30 250 1.5 –50 Max –1.2 2.5 3.0 2.0 0.55 0.55 ±1.0 ±100 ±50 50 –50 50 –180 250 30 250 1.5 Tamb = –40°C to +85°C Min Max –1.2 V V V V V V µA µA µA µA µA µA mA µA mA µA mA UNIT NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V " 10%, a transition time of up to 100µsec is permitted. 1995 Sep 06 4 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn Propagation delay LE to Qn Propagation delay PRE to Qn Propagation delay MR to Qn Output enable time OEn to Qn Output disable time OEn to Qn 1 2 1 1 4 5 4 5 1.0 2.2 2.0 2.8 2.2 3.0 2.4 3.1 1.0 2.0 1.9 2.2 Tamb = +25oC VCC = +5.0V Typ 3.9 5.4 5.1 6.4 4.9 5.3 4.9 5.9 3.8 4.7 4.6 4.7 Max 5.4 6.8 6.6 7.9 6.6 6.8 6.4 7.3 5.4 6.1 6.2 6.4 Tamb = -40 to +85oC VCC = +5.0V ±0.5V Min 1.0 2.2 2.0 2.8 2.2 3.0 2.4 3.1 1.0 2.0 1.9 2.2 Max 6.2 7.8 7.5 8.9 7.8 7.4 7.3 8.5 6.3 6.7 7.2 7.0 ns ns ns ns ns ns UNIT AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORM Tamb = VCC = +5.0V Min ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec trec Setup time, High or Low Dn to LE Hold time, High or Low Dn to LE LE pulse width, High PRE pulse width, Low MR pulse width, Low PRE recovery time MR recovery time 3 3 3 6 6 6 6 2.8 3.5 1.0 1.0 3.0 3.5 2.8 3.0 3.4 +25oC Typ 1.0 1.4 –1.2 –0.6 1.5 2.0 1.3 1.4 1.6 Tamb = -40 to +85oC VCC = +5.0V ±0.5V Min 2.8 3.5 1.0 1.0 3.0 3.5 2.8 3.0 3.4 ns ns ns ns ns ns ns UNIT 1995 Sep 06 5 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 AC WAVEFORMS NOTE: For all waveforms, VM = 1.5V. Dn PRE VM MR, Dn LE tPLH Qn tPHL tPLH Qn tPHL VM VM VM VM VM VM VM SA00254 SA00255 Waveform 1. Propagation Delay, Data to Output, Preset to Output, and Master Reset to Output Waveform 2. Propagation Delay, Latch Enable to Output Dn 1995 Sep 06 ÉÉÉ É ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ É ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ VM VM VM VM ts(H) th(H) ts(L) th(L) tw(H) LE VM VM VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. OE VM tPZH VM tPHZ VOH–0.3V 0V Qn VM SA00256 SA00066 Waveform 3. Data Setup and Hold Times and Latch Enable Pulse Width Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level OE VM tPZL VM tPLZ PRE, MR VM tw(L) VM tREC VM Qn LE VM VOL +0.3V VOL SA00109 Qn Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level Qn SA00257 Waveform 6. Master Reset and Preset Pulse Width and Master Reset and Preset to Latch Enable Recovery Time 6 Philips Semiconductors Product specification 8-bit bus interface latch with set and reset (3-State) 74ABT845 TEST CIRCUIT AND WAVEFORM VCC 7.0V RL 90% NEGATIVE PULSE VM 10% tTHL (tF) CL RL POSITIVE PULSE 10% tW tTLH (tR) 90% 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V) PULSE GENERATOR VIN D.U.T. RT VOUT Test Circuit for 3-State Outputs VM SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open VM = 1.5V Input Pulse Definition DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns SA00012 1995 Sep 06 7