74AHCT1G00GW

INTEGRATED CIRCUITS DATA SHEET 74AHC1G00; 74AHCT1G00 2-input NAND gate Product specification Supersedes data of 2002 Feb 27 2002 May 27 Philips Semiconductors Product specification 2-input NAND gate FEATURES • Symmetrical output impedance • High noise immunity • ESD protection: – HBM EIA/JESD22-A114-A exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V – CDM EIA/JESD22-C101 exceeds 1000 V. • Low power dissipation • Balanced propagation delays • Very small 5-pin package • Output capability: standard • Specified from −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. 74AHC1G00; 74AHCT1G00 DESCRIPTION The 74AHC1G/AHCT1G00 is a high-speed Si-gate CMOS device. The 74AHC1G/AHCT1G00 provides the 2-input NAND function. TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PARAMETER propagation delay A and B to Y input capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC1G CL = 15 pF; VCC = 5 V 3.5 1.5 17 AHCT1G 3.6 1.5 18 ns pF pF UNIT 2002 May 27 2 Philips Semiconductors Product specification 2-input NAND gate FUNCTION TABLE See note 1. INPUTS A L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION B L H L H 74AHC1G00; 74AHCT1G00 OUTPUT Y H H H L PACKAGES TYPE NUMBER 74AHC1G00GW 74AHCT1G00GW 74AHC1G00GV 74AHCT1G00GV PINNING PIN 1 2 3 4 5 B A GND Y VCC SYMBOL data input B data input A ground (0 V) data output Y supply voltage DESCRIPTION TEMPERATURE RANGE −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C PINS 5 5 5 5 PACKAGE SC-88A SC-88A SC-74A SC-74A MATERIAL plastic plastic plastic plastic CODE SOT353 SOT353 SOT753 SOT753 MARKING AA CA A00 C00 2002 May 27 3 Philips Semiconductors Product specification 2-input NAND gate 74AHC1G00; 74AHCT1G00 handbook, halfpage B1 A2 GND 3 MNA096 5 VCC handbook, halfpage 1 2 B A 00 4 Y Y 4 MNA097 Fig.1 Pin configuration. Fig.2 Logic symbol. handbook, halfpage 1 2 handbook, halfpage & B Y 4 MNA098 A MNA099 Fig.3 IEC logic symbol. Fig.4 Logic diagram. 2002 May 27 4 Philips Semiconductors Product specification 2-input NAND gate RECOMMENDED OPERATING CONDITIONS 74AHC1G00; 74AHCT1G00 74AHC1G SYMBOL VCC VI VO Tamb tr, tf (∆t/∆f) PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times CONDITIONS MIN. 2.0 0 0 see DC and AC −40 characteristics per device VCC = 3.3 ±0.3 V VCC = 5 ±0.5 V − − TYP. 5.0 − − +25 − − MAX. 5.5 5.5 VCC +125 100 20 MIN. 4.5 0 0 −40 − − 74AHCT1G UNIT TYP. 5.0 − − +25 − − MAX. 5.5 5.5 VCC +125 − 20 V V V °C ns/V ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg PD Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. PARAMETER supply voltage input voltage input diode current output diode current output source or sink current VCC or GND current storage temperature power dissipation per package for temperature range from −40 to +125 °C VI < −0.5 V VO < −0.5 V or VO > VCC + 0.5 V; note 1 −0.5 V < VO < VCC + 0.5 V CONDITIONS MIN. −0.5 −0.5 − − − − −65 − MAX. +7.0 +7.0 −20 ±20 ±25 ±75 +150 250 UNIT V V mA mA mA mA °C mW 2002 May 27 5 Philips Semiconductors Product specification 2-input NAND gate DC CHARACTERISTICS 74AHC1G00; 74AHCT1G00 Family 74AHC1G At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH HIGH-level input voltage VCC (V) 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output VI = VIH or VIL; voltage IO = −50 µA VI = VIH or VIL; IO = −50 µA VI = VIH or VIL; IO = −50 µA VI = VIH or VIL; IO = −4.0 mA VI = VIH or VIL; IO = −8.0 mA VOL LOW-level output voltage VI = VIH or VIL; IO = 50 µA VI = VIH or VIL; IO = 50 µA VI = VIH or VIL; IO = 50 µA VI = VIH or VIL; IO = 4.0 mA VI = VIH or VIL; IO = 8.0 mA ILI ICC CI input leakage current quiescent supply current input capacitance VI = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 25 MIN. 1.5 2.1 3.85 − − − 1.9 2.9 4.4 2.58 3.94 − − − − − − − − TYP. − − − − − − 2.0 3.0 4.5 − − 0 0 0 − − − − 1.5 MAX. − − − 0.5 0.9 1.65 − − − − − 0.1 0.1 0.1 0.36 0.36 0.1 1.0 10 Tamb (°C) -40 to +85 MIN. 1.5 2.1 3.85 − − − 1.9 2.9 4.4 2.48 3.8 − − − − − − − − MAX. − − − 0.5 0.9 1.65 − − − − − 0.1 0.1 0.1 0.44 0.44 1.0 10 10 -40 to +125 MIN. 1.5 2.1 3.85 − − − 1.9 2.9 4.4 2.40 3.70 − − − − − − − − MAX. − − − 0.5 0.9 1.65 − − − − − 0.1 0.1 0.1 0.55 0.55 2.0 40 10 V V V V V V V V V V V V V V V V µA µA pF UNIT VI = VCC or GND; 5.5 IO = 0 2002 May 27 6 Philips Semiconductors Product specification 2-input NAND gate 74AHC1G00; 74AHCT1G00 Family 74AHCT1G At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output VI = VIH or VIL; voltage IO = −50 µA VI = VIH or VIL; IO = −8.0 mA VOL LOW-level output voltage VI = VIH or VIL; IO = 50 µA VI = VIH or VIL; IO = 8.0 mA ILI ICC ∆ICC input leakage current quiescent supply current additional quiescent supply current per input pin input capacitance VI = VIH or VIL VCC (V) MIN. − − 4.5 − 0 − − − − 25 − 0.8 − − 0.1 0.36 0.1 1.0 1.35 Tamb (°C) −40 to +85 − 0.8 − − 0.1 0.44 1.0 10 1.5 −40 to +125 UNIT − 0.8 − − 0.1 0.55 2.0 40 1.5 TYP. MAX. MIN. MAX. MIN. MAX. 2.0 − 4.4 3.8 − − − − − 2.0 − 4.4 3.70 − − − − − V V V V V V µA µA mA 4.5 to 5.5 2.0 4.5 to 5.5 − 4.5 4.5 4.5 4.5 5.5 4.4 3.94 − − − − − VI = VCC or GND; 5.5 IO = 0 VI = 3.4 V; other inputs at VCC or GND; IO = 0 5.5 CI − 1.5 10 − 10 − 10 pF 2002 May 27 7 Philips Semiconductors Product specification 2-input NAND gate AC CHARACTERISTICS Type 74AHC1G00 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay A and B to Y see Figs 5 and 6 15 50 − − − − 4.5 6.5 CL (pF) 25 MIN. TYP. 74AHC1G00; 74AHCT1G00 Tamb (°C) −40 to +85 MAX. MIN. MAX. −40 to +125 MIN. MAX. UNIT 7.9 11.4 1.0 1.0 9.5 13.0 1.0 1.0 10.5 14.5 ns ns VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay A and B to Y see Figs 5 and 6 15 50 3.5 4.9 5.5 7.5 1.0 1.0 6.5 8.5 1.0 1.0 7.0 9.5 ns ns Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5 V. Type 74AHCT1G00 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay A and B to Y see Figs 5 and 6 15 50 − − 3.6 5.0 6.2 7.9 1.0 1.0 7.1 9.0 1.0 1.0 8.0 10.0 ns ns CL (pF) 25 MIN. TYP. MAX. Tamb (°C) −40 to +85 MIN. MAX. −40 to +125 MIN. MAX. UNIT Note 1. Typical values at VCC = 5 V. 2002 May 27 8 Philips Semiconductors Product specification 2-input NAND gate AC WAVEFORMS 74AHC1G00; 74AHCT1G00 handbook, halfpage A, B input VM tPHL tPLH Y output VM MNA106 FAMILY AHC1G AHCT1G VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM INPUT 1.5 V VM OUTPUT 50% VCC 50% VCC 50% VCC Fig.5 The inputs (A and B) to output (Y) propagation delays. handbook, halfpage VCC VI D.U.T. RT CL MNA101 PULSE GENERATOR VO Definitions for test circuit: CL = Load capacitance including jig and probe capacitance (see Chapter “AC characteristics”). RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator. Fig.6 Load circuitry for switching times. 2002 May 27 9 Philips Semiconductors Product specification 2-input NAND gate PACKAGE OUTLINES Plastic surface mounted package; 5 leads 74AHC1G00; 74AHCT1G00 SOT353 D B E A X y HE vMA 5 4 Q A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E (2) 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT353 REFERENCES IEC JEDEC EIAJ SC-88A EUROPEAN PROJECTION ISSUE DATE 97-02-28 2002 May 27 10 Philips Semiconductors Product specification 2-input NAND gate 74AHC1G00; 74AHCT1G00 Plastic surface mounted package; 5 leads SOT753 D B E A X y HE vMA 5 4 Q A A1 c 1 2 3 detail X Lp e bp wM B 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.100 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT753 REFERENCES IEC JEDEC JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 2002 May 27 11 Philips Semiconductors Product specification 2-input NAND gate SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. 74AHC1G00; 74AHCT1G00 If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2002 May 27 12 Philips Semiconductors Product specification 2-input NAND gate 74AHC1G00; 74AHCT1G00 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not suitable(3) SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable suitable not not recommended(4)(5) recommended(6) 2002 May 27 13 Philips Semiconductors Product specification 2-input NAND gate DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development 74AHC1G00; 74AHCT1G00 DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2002 May 27 14 Philips Semiconductors Product specification 2-input NAND gate NOTES 74AHC1G00; 74AHCT1G00 2002 May 27 15 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2002 SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/05/pp16 Date of release: 2002 May 27 Document order number: 9397 750 09699