74AHCT573

INTEGRATED CIRCUITS DATA SHEET 74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state Product specification Supersedes data of 1999 Sep 27 2003 Dec 08 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Balanced propagation delays • All inputs have Schmitt-trigger actions • Common 3-state output enable input • Functionally identical to the 74AHC/AHCT563 and 74AHC/AHCT373 • Inputs accepts voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION The 74AHC/AHCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. 74AHC573; 74AHCT573 The 74AHC/AHCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all latches. The 74AHC/AHCT573 consists of eight D-type transparent latches with 3-state true outputs. When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When pin LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74AHC/AHCT573 is functionally identical to the 74AHC/AHCT533, 74AHC/AHCT563 and 74AHC/AHCT373, but the 74AHC/AHCT533 and 74AHC/AHCT563 have inverted outputs and the 74AHC/AHCT563 and 74AHC/AHCT373 have a different pin arrangement. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL tPHL/tPLH CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. PARAMETER propagation delay Dn to Qn; LE to Qn input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V VI = VCC or GND 3.9 3.0 4.0 12 AHCT 3.5 3.0 4.0 18 ns pF pF pF UNIT 2003 Dec 08 2 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state FUNCTION TABLE See note 1. INPUT OPERATING MODE OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs Note 1. H = HIGH voltage level; L L L L H H LE H H L L L L Dn L H I h l h 74AHC573; 74AHCT573 INTERNAL LATCH L H L H L H OUTPUT Q0 to Q7 L H L H Z Z h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER PINS 74AHC573D 74AHCT573D 74AHC573PW 74AHCT573PW 20 20 20 20 PACKAGE SO20 SO20 TSSOP20 TSSOP20 MATERIAL plastic plastic plastic plastic CODE SOT163-1 SOT163-1 SOT360-1 SOT360-1 2003 Dec 08 3 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYMBOL OE D0 D1 D2 D3 D4 D5 D6 D7 GND LE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC DESCRIPTION 3-state output enable input (active LOW) data input data input data input data input data input data input data input data input ground (0 V) latch enable input (active HIGH) 3-state latch output 3-state latch output 3-state latch output 3-state latch output 3-state latch output 3-state latch output 3-state latch output 3-state latch output supply voltage handbook, halfpage 74AHC573; 74AHCT573 OE 1 D0 2 D1 3 D2 4 D3 5 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 573 D4 6 D5 7 D6 8 D7 9 GND 10 MNA388 15 Q4 14 Q5 13 Q6 12 Q7 11 LE Fig.1 Pin configuration SO20 and TSSSOP20. handbook, halfpage handbook, halfpage 11 1 C1 EN 11 2 3 4 5 6 7 8 9 LE D0 D1 D2 D3 D4 D5 D6 D7 OE 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 2 3 4 5 6 7 8 1D 19 18 17 16 15 14 13 12 MNA390 MNA389 9 Fig.2 Logic symbol. Fig.3 IEC logic symbol. Fi 3 L i di 2003 Dec 08 4 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 handbook, halfpage 2 3 4 5 6 7 8 9 D0 D1 D2 D3 D4 D5 D6 D7 LATCH 1 to 8 3-STATE OUTPUTS Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12 11 LE 1 OE MNA391 Fig.4 Functional diagram. D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q LATCH 1 LE LE OE LATCH 2 LE LATCH 3 LE LATCH 4 LE LATCH 5 LE LATCH 6 LE LATCH 7 LE LATCH 8 LE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MNA392 Fig.5 Logic diagram. 2003 Dec 08 5 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state RECOMMENDED OPERATING CONDITIONS 74AHC573; 74AHCT573 74AHC SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall rates CONDITIONS MIN. 2.0 0 0 see DC and AC −40 characteristics per device −40 VCC = 3.3 V ±0.3 V VCC = 5 V ±0.5 V − − TYP. MAX. MIN. 5.0 − − +25 +25 − − 5.5 5.5 VCC +85 100 20 4.5 0 0 −40 − − 74AHCT UNIT TYP. MAX. 5.0 − − +25 +25 − − 5.5 5.5 VCC +85 − 20 V V V °C ns/V ns/V +125 −40 +125 °C LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO20packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For TSSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. PARAMETER supply voltage input voltage input diode current output diode current output source or sink current VCC or GND current storage temperature power dissipation Tamb = −40 to +125 °C; note 2 VI < −0.5 V; note 1 VO < −0.5 V or VO > VCC + 0.5 V; note 1 −0.5 V < VO < VCC + 0.5 V CONDITIONS MIN. MAX. UNIT −0.5 −0.5 − − − − −65 − +7.0 +7.0 −20 ±20 ±25 ±75 500 V V mA mA mA mA mW +150 °C 2003 Dec 08 6 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state DC CHARACTERISTICS 74AHC573; 74AHCT573 74AHC type At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb = 25 °C VIH HIGH-level input voltage 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage VI = VIH or VIL IO = −50 µA IO = −50 µA IO = −50 µA IO = −4.0 mA IO = −8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 µA IO = 50 µA IO = 50 µA IO = 4.0 mA IO = 8.0 mA ILI IOZ ICC CI input leakage current 3-state output OFF current input capacitance VI = VCC or GND VI = VIH or VIL; VO = VCC or GND 2.0 3.0 4.5 3.0 4.5 5.5 5.5 − − − − − − − − − 0 0 0 − − − − − 3 0.1 0.1 0.1 0.36 0.36 0.1 ±0.25 4.0 10 V V V V V µA µA µA pF 2.0 3.0 4.5 3.0 4.5 1.9 2.9 4.4 2.58 3.94 2.0 3.0 4.5 − − − − − − − V V V V V 1.5 2.1 3.85 − − − − − − − − − − − − 0.5 0.9 1.65 V V V V V V PARAMETER OTHER VCC (V) MIN. TYP. MAX. UNIT quiescent supply current VI = VCC or GND; IO = 0 5.5 − 2003 Dec 08 7 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C VIH HIGH-level input voltage 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage VI = VIH or VIL IO = −50 µA IO = −50 µA IO = −50 µA IO = −4.0 mA IO = −8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 µA IO = 50 µA IO = 50 µA IO = 4.0 mA IO = 8.0 mA ILI IOZ ICC CI input leakage current 3-state output OFF current input capacitance VI = VCC or GND VI = VIH or VIL; VO = VCC or GND 2.0 3.0 4.5 3.0 4.5 5.5 5.5 − − − − − − − − − − − − − − − − − − 0.1 0.1 0.1 0.44 0.44 1.0 ±2.5 40 10 V V V V V µA µA µA pF 2.0 3.0 4.5 3.0 4.5 1.9 2.9 4.4 2.48 3.8 − − − − − − − − − − V V V V V 1.5 2.1 3.85 − − − − − − − − − − − − 0.5 0.9 1.65 V V V V V V VCC (V) MIN. TYP. MAX. UNIT quiescent supply current VI = VCC or GND; IO = 0 5.5 − 2003 Dec 08 8 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +125 °C VIH HIGH-level input voltage 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage VI = VIH or VIL IO = −50 µA IO = −50 µA IO = −50 µA IO = −4.0 mA IO = −8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 µA IO = 50 µA IO = 50 µA IO = 4.0 mA IO = 8.0 mA ILI IOZ ICC CI input leakage current 3-state output OFF current input capacitance VI = VCC or GND VI = VIH or VIL; VO = VCC or GND 2.0 3.0 4.5 3.0 4.5 5.5 5.5 − − − − − − − − − − − − − − − − − − − 0.1 0.1 0.1 0.44 2.0 ±10.0 80 10 V V V V V µA µA µA pF 2.0 3.0 4.5 3.0 4.5 1.9 2.9 4.4 2.48 3.8 1.9 2.9 4.4 2.48 3.8 − − − − − V V V V V 1.5 2.1 3.85 − − − − − − − − − − − − 0.5 0.9 1.65 V V V V V V VCC (V) MIN. TYP. MAX. UNIT quiescent supply current VI = VCC or GND; IO = 0 5.5 − 2003 Dec 08 9 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 74AHCT type At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb = 25 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −50 µA IO = −8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 µA IO = 8.0 mA ILI IOZ input leakage current 3-state output OFF current VI = VIH or VIL 4.5 4.5 5.5 − − − − 0 − − − 0.1 0.36 0.1 ±0.25 V V µA µA 4.5 4.5 4.4 3.94 4.5 − − − V V 4.5 to 5.5 4.5 to 5.5 2.0 − − − − 0.8 V V PARAMETER OTHER VCC (V) MIN. TYP. MAX. UNIT VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 VI = VCC or GND; IO = 0 5.5 VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 4.5 to 5.5 ICC ∆ICC quiescent supply current additional quiescent supply current per input pin input capacitance − − − − 4.0 1.35 µA mA CI − − 3 − − − − − − − − 10 − 0.8 − − 0.1 0.44 1.0 ±2.5 pF Tamb = −40 to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −50 µA IO = −8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 µA IO = 8.0 mA ILI IOZ input leakage current 3-state output OFF current VI = VIH or VIL 4.5 4.5 5.5 − − − − V V µA µA 4.5 4.5 4.4 3.8 V V 4.5 to 5.5 4.5 to 5.5 2.0 − V V VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 VI = VCC or GND; IO = 0 5.5 VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 4.5 to 5.5 ICC ∆ICC quiescent supply current additional quiescent supply current per input pin input capacitance − − − − 40 1.5 µA mA CI − − − 10 pF 2003 Dec 08 10 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −50 µA IO = −8.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 50 µA IO = 8.0 mA ILI IOZ input leakage current 3-state output OFF current VI = VIH or VIL 4.5 4.5 5.5 − − − − − − − − 0.1 0.55 2.0 ±10.0 V V µA µA 4.5 4.5 4.4 3.70 − − − − V V 4.5 to 5.5 4.5 to 5.5 2.0 − − − − 0.8 V V VCC (V) MIN. TYP. MAX. UNIT VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 VI = VCC or GND; IO = 0 5.5 VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 4.5 to 5.5 ICC ∆ICC quiescent supply current additional quiescent supply current per input pin input capacitance − − − − 80 1.5 µA mA CI − − − 10 pF 2003 Dec 08 11 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state AC CHARACTERISTICS 74AHC573 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL VCC = 3.0 to 3.6 V Tamb = 25 °C; note 1 tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn enable pulse width HIGH set-up time Dn to LE hold time Dn to LE see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 10 see Fig.8 see Fig.8 15 15 15 15 50 50 50 50 50 50 50 PARAMETER WAVEFORMS CL (pF) 74AHC573; 74AHCT573 MIN. TYP. MAX. UNIT − − − − − − − − 5.0 3.5 1.5 5.5 5.8 5.8 6.8 7.8 8.3 8.3 9.7 − − − − − − − − − − − − − − 11.0 11.9 11.5 11.0 14.5 15.4 15.0 14.5 − − − ns ns ns ns ns ns ns ns ns ns ns Tamb = −40 to +85 °C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn enable pulse width HIGH set-up time Dn to LE hold time Dn to LE see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 10 see Fig.8 see Fig.8 15 15 15 15 50 50 50 50 50 50 50 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 3.5 1.5 13.0 14.0 13.5 13.0 16.5 17.5 17.0 16.5 − − − ns ns ns ns ns ns ns ns ns ns ns 2003 Dec 08 12 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 to +125 °C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn enable pulse width HIGH set-up time Dn to LE hold time Dn to LE see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 10 see Fig.8 see Fig.8 15 15 15 15 50 50 50 50 50 50 50 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 3.5 1.5 − − − − − − − − − − − 14.0 15.0 14.5 14.0 18.5 19.5 19.0 18.5 − − − ns ns ns ns ns ns ns ns ns ns ns CL (pF) MIN. TYP. MAX. UNIT VCC = 4.5 to 5.5 V Tamb = 25 °C; note 2 tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn enable pulse width HIGH set-up time Dn to LE hold time Dn to LE see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 10 see Fig.8 see Fig.8 15 15 15 15 50 50 50 50 50 50 50 − − − − − − − − 5.0 3.5 1.5 3.9 4.2 4.4 4.6 5.5 5.9 6.3 7.4 − − − − − − − − − − − − − − 6.8 7.7 7.7 7.7 8.8 9.7 9.7 9.7 − − − ns ns ns ns ns ns ns ns ns ns ns Tamb = −40 to +85 °C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn enable pulse width HIGH set-up time Dn to LE hold time Dn to LE see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 10 see Fig.8 see Fig.8 15 15 15 15 50 50 50 50 50 50 50 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 3.5 1.5 8.0 9.0 9.0 9.0 10.0 11.0 11.0 11.0 − − − ns ns ns ns ns ns ns ns ns ns ns 2003 Dec 08 13 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 to +125 °C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn enable pulse width HIGH set-up time Dn to LE hold time Dn to LE see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 10 see Fig.8 see Fig.8 15 15 15 15 50 50 50 50 50 50 50 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 3.5 1.5 − − − − − − − − − − − 8.5 10.0 10.0 10.0 11.0 12.5 12.5 12.5 − − − ns ns ns ns ns ns ns ns ns ns ns CL (pF) MIN. TYP. MAX. UNIT propagation delay Dn to Qn2 see Figs 6 and 10 2003 Dec 08 14 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHCT573 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 1 Tamb = 25 °C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn enable pulse width HIGH set-up time Dn to LE hold time Dn to LE see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 9 see Fig.8 see Fig.8 15 15 15 15 50 50 50 50 50 50 50 74AHC573; 74AHCT573 MIN. CL (pF) TYP. MAX. UNIT − − − − − − − − 5.0 3.5 1.5 3.5 3.9 4.1 4.5 4.9 5.5 5.9 6.4 − − − − − − − − − − − − − − 5.5 6.0 6.5 6.5 7.5 8.5 8.5 9.0 − − − ns ns ns ns ns ns ns ns ns ns ns Tamb = −40 to +85 °C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn enable pulse width HIGH set-up time Dn to LE hold time Dn to LE see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 9 see Fig.8 see Fig.8 15 15 15 15 50 50 50 50 50 50 50 1 1 1 1 1 1 1 1 5.0 3.5 1.5 6.5 7.0 7.5 7.5 8.5 9.5 10.0 10.0 − − − ns ns ns ns ns ns ns ns ns ns ns 2003 Dec 08 15 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 to +125 °C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th Note 1. Typical values at VCC = 5.0 V. propagation delay Dn to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn propagation delay LE to Qn propagation delay OE to Qn propagation delay OE to Qn enable pulse width HIGH set-up time Dn to LE hold time Dn to LE see Figs 6 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 10 see Figs 9 and 10 see Figs 9 and 10 see Figs 7 and 9 see Fig.8 see Fig.8 15 15 15 15 50 50 50 50 50 50 50 1 1 1 1 1 1 1 1 5.0 3.5 1.5 − − − − − − − − − − − 7.0 7.5 8.5 8.5 9.5 11.0 11.0 11.5 − − − ns ns ns ns ns ns ns ns ns ns ns CL (pF) MIN. TYP. MAX. UNIT propagation delay Don to Qn see Figs 6 and 10 2003 Dec 08 16 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state AC WAVEFORMS 74AHC573; 74AHCT573 handbook, halfpage VI VM Dn input GND tPHL VOH Qn output VOL VM tPLH MNA811 FAMILY AHC AHCT VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM INPUT 50% VCC 1.5 V VM OUTPUT 50% VCC 50% VCC Fig.6 The data input (Dn) to output (Qn) propagation delays. handbook, full pagewidth 1/fmax VI LE input GND tW t PHL VOH Qn output VOL VM MNA812 VM t PLH FAMILY AHC AHCT VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM INPUT 50% VCC 1.5 V VM OUTPUT 50% VCC 50% VCC Fig.7 The latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays. 2003 Dec 08 17 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 handbook, full pagewidth VI Dn input GND th t su VI LE input GND VM MNA814 VM th t su FAMILY AHC AHCT VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM INPUT 50% VCC 1.5 V The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.8 Data set-up and hold times for the Dn input to the LE input. handbook, full pagewidth VI OE input GND tPLZ output LOW-to-OFF OFF-to-LOW VCC VM(2) VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled MNA450 VM(1) tPZL VOL + 0.3 V tPZH VOH − 0.3 V VM(2) FAMILY AHC AHCT VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM(1) INPUT 50% VCC 1.5 V VM(2) OUTPUT 50% VCC 50% VCC Fig.9 The 3-state enable and disable times. 2003 Dec 08 18 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 handbook, full pagewidth S1 VCC PULSE GENERATOR VI D.U.T. RT CL MNA183 RL = VO 1 kΩ VCC open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH open VCC GND S1 Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.10 Load circuitry for switching times. 2003 Dec 08 19 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm 74AHC573; 74AHCT573 SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) θ 0.9 0.4 0.035 0.016 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2003 Dec 08 20 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74AHC573; 74AHCT573 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2003 Dec 08 21 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development 74AHC573; 74AHCT573 DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Dec 08 22 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R44/02/pp23 Date of release: 2003 Dec 08 Document order number: 9397 750 12156