74ALVC00

INTEGRATED CIRCUITS DATA SHEET 74ALVC00 Quad 2-input NAND gate Product specification Supersedes data of 2003 Feb 06 2003 May 14 Philips Semiconductors Product specification Quad 2-input NAND gate FEATURES • Wide supply voltage range from 1.65 to 3.6 V • 3.6 V tolerant inputs/outputs • CMOS low power consumption • Direct interface with TTL levels (2.7 to 3.6 V) • Power-down mode • Latch-up performance exceeds 250 mA • Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay inputs nA, nB to output nY CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. input capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 DESCRIPTION 74ALVC00 The 74ALVC00 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. The 74ALVC00 provides the 2-input NAND function. TYPICAL 2.8 2.1 2.6 2.1 3.5 28 ns ns ns ns UNIT pF pF 2003 May 14 2 Philips Semiconductors Product specification Quad 2-input NAND gate ORDERING INFORMATION PACKAGE TYPE NUMBER 74ALVC00D 74ALVC00PW 74ALVC00BQ FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. nB L H L H TEMPERATURE RANGE −40 to +85 °C −40 to +85 °C −40 to +85 °C PINS 14 14 14 PACKAGE SO14 TSSOP14 DHVQFN14 MATERIAL plastic plastic plastic 74ALVC00 CODE SOT108-1 SOT402-1 SOT762-1 OUTPUT nY H H H L PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC DESCRIPTION data input data input data output data input data input data output ground (0 V) data output data input data input data output data input data input supply voltage Fig.1 Pin configuration SO14 and TSSOP14. 1B 1Y 2A 2B 2Y GND 2 3 4 5 6 7 MNA210 handbook, halfpage 1A 1 14 VCC 13 4B 12 4A 00 11 4Y 10 3B 9 8 3A 3Y 2003 May 14 3 Philips Semiconductors Product specification Quad 2-input NAND gate 74ALVC00 handbook, halfpage 1A 1 VCC 14 13 12 4B 4A 4Y B 3B 3A handbook, halfpage 1B 1Y 2A 2B 2Y 2 3 4 5 6 7 Top view GND 8 3Y A Y MNA211 GND(1) 11 10 9 MNA950 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.2 Pin configuration DHVQFN14. Fig.3 Logic diagram (one gate). handbook, halfpage handbook, halfpage 1 2 & 3 1 2 4 5 9 10 12 13 1A 1B 2A 2B 3A 3B 4A 4B 1Y 3 4 & 6 2Y 6 5 3Y 8 9 10 & 8 4Y 11 12 & 11 MNA212 13 MNA246 Fig.4 Function diagram. Fig.5 IEC logic symbol. 2003 May 14 4 Philips Semiconductors Product specification Quad 2-input NAND gate RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times VCC = 1.65 to 2.7 V VCC = 2.7 to 3.6 V VCC = 1.65 to 3.6 V VCC = 0 V; Power-down mode CONDITIONS 0 0 0 −40 0 0 MIN. 1.65 74ALVC00 MAX. 3.6 3.6 VCC 3.6 +85 20 10 V V V V UNIT °C ns/V ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. 3. For SO14 packages: above 70 °C derate linearly with 8 mW/K. For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation per package Tamb = −40 to +125 °C; note 3 VO > VCC or VO < 0 notes 1 and 2 Power-down mode; note 2 VO = 0 to VCC VI < 0 CONDITIONS − −0.5 − −0.5 −0.5 − − −65 − MIN. −0.5 MAX. +4.6 −50 +4.6 ±50 +4.6 ±50 ±100 +150 500 V mA V mA V mA mA °C mW UNIT VCC + 0.5 V 2003 May 14 5 Philips Semiconductors Product specification Quad 2-input NAND gate DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C VIH HIGH-level input voltage 1.65 to 1.95 0.65 × VCC − 2.3 to 2.7 2.7 to 3.6 VIL LOW-level input voltage 2.3 to 2.7 2.7 to 3.6 VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 6 mA IO = 12 mA IO = 18 mA IO = 12 mA IO = 18 mA IO = 24 mA VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −6 mA IO = −12 mA IO = −18 mA IO = −12 mA IO = −18 mA IO = −24 mA ILI Ioff ICC ∆ICC input leakage current power OFF leakage current quiescent supply current additional quiescent supply current per input pin VI = 3.6 V or GND VI or VO = 3.6 V VI = VCC or GND; IO = 0 VI = VCC − 0.6 V; IO = 0 1.65 to 3.6 1.65 2.3 2.3 2.7 3.0 3.0 3.6 0.0 3.6 3.0 to 3.6 VCC − 0.2 1.25 1.8 1.7 2.2 2.4 2.2 − − − − − 1.51 2.10 2.01 2.53 2.76 2.68 ±0.1 ±0.1 0.2 5 1.65 to 3.6 1.65 2.3 2.3 2.7 3.0 3.0 − − − − − − − − 0.11 0.17 0.25 0.16 0.23 0.30 1.7 2 − − − − − − − VCC (V) MIN. TYP.(1) 74ALVC00 MAX. UNIT − − − 0.7 0.8 0.2 0.3 0.4 0.6 0.4 0.4 0.55 − − − − − − − ±5 ±10 20 750 V V V V V V V V V V V V V V V V V V V µA µA µA µA 1.65 to 1.95 − 0.35 × VCC V Note 1. All typical values are measured at Tamb = 25 °C. 2003 May 14 6 Philips Semiconductors Product specification Quad 2-input NAND gate AC CHARACTERISTICS TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 to +85 °C tPHL/tPLH propagation delay nA, nB to nY see Figs 6 and 7 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Note 1. All typical values are measured at Tamb = 25 °C. AC WAVEFORMS 1.0 1.0 1.0 1.0 2.8 2.1 2.6 2.1 VCC (V) MIN. TYP.(1) 74ALVC00 MAX. UNIT 4.4 2.8 3.2 3.0 ns ns ns ns handbook, halfpage VI VM GND tPHL VOH tPLH nA, nB input nY output VOL VM MNA218 INPUT VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V VCC VCC 2.7 V 2.7 V VI tr = tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 Inputs nA, nB to output nY propagation delay times. 2003 May 14 7 Philips Semiconductors Product specification Quad 2-input NAND gate 74ALVC00 handbook, full pagewidth VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL MNA616 VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V VI VCC VCC 2.7 V 2.7 V CL 30 pF 30 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω VEXT tPLH/tPHL open open open open tPZH/tPHZ GND GND GND GND tPZL/tPLZ 2 × VCC 2 × VCC 6V 6V Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.7 Load circuitry for switching times. 2003 May 14 8 Philips Semiconductors Product specification Quad 2-input NAND gate PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm 74ALVC00 SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 A1 pin 1 index θ Lp 1 e bp 7 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 θ inches 0.069 Note 0.010 0.057 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 8 0o o 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2003 May 14 9 Philips Semiconductors Product specification Quad 2-input NAND gate 74ALVC00 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 2003 May 14 10 Philips Semiconductors Product specification Quad 2-input NAND gate 74ALVC00 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 2003 May 14 11 Philips Semiconductors Product specification Quad 2-input NAND gate SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept: • below 220 °C for all the BGA packages and packages with a thickness ≥ 2.5mm and packages with a thickness