74ALVCH32501EC

INTEGRATED CIRCUITS DATA SHEET 74ALVCH32501 36-bit universal bus transceiver with direction pin; 3-state Product specification Supersedes data of 2000 Mar 16 2004 Oct 13 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state FEATURES • 3-state non-inverting outputs for bus oriented applications • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A • Current drive ±24 mA at 3.0 V • Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode • CMOS low power consumption • Direct interface with TTL levels • All inputs have bus-hold circuitry • Output drive capability 50 Ω transmission lines at 85 °C • Plastic fine-pitch ball grid array package. DESCRIPTION The 74ALVCH32501 is a high-performance CMOS product designed for VCC operation at 2.5 V and 3.3 V. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPHL/tPLH CI CI/O CPD PARAMETER propagation delay An to Bn; Bn to An input capacitance input/output capacitance power dissipation capacitance per latch VI = GND to VCC; note 1 outputs enabled outputs disabled Note 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. CONDITIONS CL = 30 pF; VCC = 2.5 V CL = 50 pF; VCC = 3.3 V 74ALVCH32501 The 74ALVCH32501 can be used as two 18-bit transceivers or one 36-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CPAB and CPBA). For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When input LEAB is LOW, the A data is latched if input CPAB is held at a HIGH or LOW level. If input LEAB is LOW, the A data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When input OEAB is HIGH, the outputs are active. When input OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B, but uses inputs OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW). To ensure the high-impedance state during power-up or power-down, pin OEBA should be tied to VCC through a pull-up resistor and pin OEAB should be tied to GND through a pull-down resistor. The minimum value of the resistor is determined by the current-sinking or current-sourcing capability of the driver. TYP. 2.8 3.0 4.0 8.0 21 3 ns ns UNIT pF pF pF pF 2004 Oct 13 2 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state FUNCTION TABLE See notes 1 and 2. INPUT nOEAB L L L L L L H H H H H H H H Notes 1. A-to-B data flow is shown; B-to-A flow is similar but uses nOEBA, nLEBA and nCPBA. 2. H = HIGH voltage level; h = HIGH voltage level on set-up time prior to the enable or clock transition; L = LOW voltage level; l = LOW voltage level on set-up time prior to the enable or clock transition; NC = no change; X = don’t care; ↑ = LOW-to-HIGH enable or clock transition; ↓ = HIGH-to-LOW enable or clock transition; Z = high impedance OFF-state. nLEAB H ↓ ↓ L L L H H ↓ ↓ L L L L nCPAB X X X H or L ↑ ↑ X X X X ↑ ↑ H or L H or L nAn X h l X h l H L h l h l X X INTERNAL REGISTERS X H L NC H L H L H L H L H L OUTPUT 74ALVCH32501 OPERATING MODE nBn Z Z Z Z Z Z H L H L H L H L disabled disabled; latch data disabled; hold data disabled; clock data transparent latch data and display clock data and display hold data and display 2004 Oct 13 3 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state ORDERING INFORMATION PACKAGE TYPE NUMBER 74ALVCH32501EC PINNING SYMBOL nAn nBn GND VCC nOEAB nOEBA nLEAB nLEBA nCPAB nCPBA data inputs data outputs ground (0 V) DC supply voltage output enable inputs A to B (active HIGH) output enable inputs B to A (active LOW) latch enable inputs A to B latch enable inputs B to A clock input A to B clock input B to A DESCRIPTION TEMPERATURE RANGE −40 °C to +85 °C PINS 114 PACKAGE LFBGA114 74ALVCH32501 MATERIAL plastic CODE SOT537-1 handbook, full pagewidth 1B1 1B3 6 1B5 1B4 GND 1B7 1B6 VCC VCC 1A6 1A7 1B9 1B8 GND GND 1A8 1A9 1B11 1B10 GND GND 1A10 1A11 1B13 1B12 VCC VCC 1A12 1A13 1B14 1B15 1B16 n.c. 2B1 2B0 GND 2B3 2B2 GND 2B5 2B4 VCC VCC 2A4 2A5 2B7 2B6 GND GND 2A6 2A7 2B9 2B8 GND GND 2A8 2A9 2B11 2B10 VCC VCC 2A10 2A11 2B13 2B12 2B14 2B16 2B17 5 4 3 2 1 1B0 1CPAB 1B2 GND 1B17 2CPAB GND 2B15 GND 1CPBA GND 2CPBA GND GND 2OE BA 2LE BA 2A12 2A13 2A15 2A14 2A17 2A16 1LEAB 1OEAB GND 1A0 1A1 1A2 1A3 1A4 1A5 GND 1OE BA 1LE BA 2OEAB GND 1A15 1A14 1A17 2LEAB 1A16 n.c. 2A0 2A1 2A2 2A3 A B C D E F G H J K L M N P R T U V W MNA562 Fig.1 Pin configuration. 2004 Oct 13 4 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state 74ALVCH32501 1OEAB 1CPBA 1LEBA 1CPAB 1LEAB 1OEBA handbook, halfpage VCC data input to internal circuit C1 1A0 C1 1B0 MNA473 1D 1D C1 C1 1D 18 IDENTICAL CHANNELS 1D Fig.3 Bus-hold circuit. 2OEAB 2CPBA 2LEBA 2CPAB 2LEAB 2OEBA C1 2A0 C1 2B0 1D 1D C1 C1 1D 18 IDENTICAL CHANNELS 1D MNA563 Fig.2 Logic symbol. 2004 Oct 13 5 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage CONDITIONS 74ALVCH32501 MIN. MAX. 2.7 3.6 VCC VCC +85 20 10 V V V V UNIT 2.5 V range (for maximum speed 2.3 performance at 30 pF output load) 3.3 V range (for maximum speed 3.0 performance at 50 pF output load) VI VO Tamb tr, tf input voltage output voltage ambient temperature input rise and fall time ratios (∆t/∆V) VCC = 1.2 V to 2.7 V VCC = 2.7 V to 3.6 V output HIGH or LOW state 0 0 −40 0 0 °C ns/V ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK VO IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 55 °C the value of Ptot derates linearly with 1.8 mW/K. PARAMETER supply voltage input voltage input diode current output clamping diode current output voltage output sink current VCC or GND current storage temperature power dissipation Tamb = −40 °C to +85 °C; note 2 for control pins; note 1 for data input pins; note 1 VI < 0 V VO < 0 V; note 1 see note 1 VO = 0 V to VCC CONDITIONS MIN. −0.5 −0.5 −0.5 − − −0.5 − − −65 − MAX. +4.6 +4.6 −50 50 −50 ±100 +150 1000 V V mA mA mA mA °C mW UNIT VCC + 0.5 V VCC + 0.5 V 2004 Oct 13 6 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 °C to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −6 mA IO = −12 mA IO = −12 mA IO = −12 mA IO = −24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 6 mA IO = 12 mA IO = 12 mA IO = 24 mA II IOZ ICC ∆ICC input leakage current 3-state output OFF-state current quiescent supply current additional quiescent supply current given per data I/O pin with bus-hold bus-hold LOW sustaining current bus-hold HIGH sustaining current bus-hold LOW overdrive current bus-hold HIGH overdrive current VI = VCC or GND 2.3 to 3.6 2.3 2.3 2.7 3.0 2.3 to 3.6 − − − − − − − − − 2.3 to 3.6 2.3 2.3 2.7 3.0 3.0 VCC − 0.2 VCC − 0.3 VCC − 0.6 VCC − 0.5 VCC − 0.6 VCC − 1.0 2.3 to 2.7 2.7 to 3.6 2.3 to 2.7 2.7 to 3.6 1.7 2.0 − − 1.2 1.5 1.2 1.5 VCC (V) MIN. 74ALVCH32501 TYP.(1) MAX. UNIT − − 0.7 0.8 − V V V V V V V V V V V V V V V µA µA µA µA VCC VCC − 0.08 − VCC − 0.26 − VCC − 0.14 − VCC − 0.09 − VCC − 0.28 − GND 0.07 0.15 0.14 0.27 ±0.1 0.1 0.4 150 0.20 0.40 0.70 0.40 0.55 ±5 ±10 80 750 VI = VIH or VIL; 2.3 to 3.6 VO = VCC or GND; note 2 VI = VCC or GND; IO = 0 A VI = VCC − 0.6 V; IO = 0 A 2.3 to 3.6 2.7 to 3.6 IBHL IBHH IBHLO IBHHO Notes VI = 0.7 V; note 3 VI = 0.8 V; note 3 VI = 1.7 V; note 3 VI = 2.0 V; note 3 note 3 note 3 2.3 3.0 2.3 3.0 3.6 3.6 45 75 −45 −75 500 −500 − 150 − −175 − − − − − − − − µA µA µA µA µA µA 1. All typical values are at VCC = 3.3 V and Tamb = 25 °C. 2. For I/O ports, the parameter IOZ includes the input leakage current. 3. Valid for data inputs of bus-hold parts. 2004 Oct 13 7 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state AC CHARACTERISTICS Tamb = −40 °C to +85 °C; GND = 0 V TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 2.3 V to 2.7 V; tr = tf ≤ 2.0 ns; note 1 tPHL/tPLH propagation delay nAn to nBn; nBn to nAn nLEBA to nAn; nLEAB to nBn nCPBA to nAn; nCPAB to nBn tPZH/tPZL tPHZ/tPLZ tW 3-state output enable time nOEAB to nBn 3-state output enable time nOEBA to nAn 3-state output disable time nOEAB to nBn 3-state output disable time nOEBA to nAn nLEAB or nLEBA pulse width HIGH nCPAB or nCPBA pulse width HIGH or LOW tsu see Figs 4 and 8 30 pF see Figs 5 and 8 30 pF see Figs 5 and 8 30 pF see Figs 6 and 8 30 pF see Figs 6 and 8 30 pF see Figs 6 and 8 30 pF see Figs 6 and 8 30 pF see Figs 5 and 8 30 pF see Figs 5 and 8 30 pF 1.0 1.1 1.0 1.0 1.3 1.5 1.3 3.3 3.3 1.7 1.1 1.7 1.6 150 CL MIN. 74ALVCH32501 TYP. MAX. UNIT 2.8 3.5 3.3 2.5 2.8 2.5 2.5 0.8 2.0 0.1 0.1 0.3 0.3 330 5.1 6.1 6.1 5.8 6.3 6.2 5.3 − − − − − − − ns ns ns ns ns ns ns ns ns ns ns ns ns MHz see Figs 7 and 8 30 pF set-up time nAn before nCPAB↑ or nBn before nCPBA↑ set-up time CP HIGH or LOW nAn before nLEAB↓ or nBn before nLEBA↓ see Figs 7 and 8 30 pF see Figs 7 and 8 30 pF see Figs 7 and 8 30 pF see Figs 5 and 8 30 pF th hold time nAn after nCPAB↑ or nBn after nCPBA↑ hold time CP HIGH or LOW nAn after nLEAB↓ or nBn after nLEBA↓ fmax maximum clock frequency VCC = 2.7 V; tr = tf ≤ 2.5 ns; note 2 tPHL/tPLH propagation delay nAn to nBn; nBn to nAn nLEBA to nAn; nLEAB to nBn nCPBA to nAn; nCPAB to nBn tPZH/tPZL tPHZ/tPLZ tW 3-state output enable time nOEAB to nBn 3-state output enable time nOEBA to nAn 3-state output disable time nOEAB to nBn 3-state output disable time nOEBA to nAn pulse width nLEAB or nLEBA HIGH pulse width nCPAB or nCPBA HIGH or LOW tsu see Figs 4 and 8 50 pF see Figs 5 and 8 50 pF see Figs 5 and 8 50 pF see Figs 6 and 8 50 pF see Figs 6 and 8 50 pF see Figs 6 and 8 50 pF see Figs 6 and 8 50 pF see Figs 5 and 8 50 pF see Figs 5 and 8 50 pF − − − − − − − 3.3 3.3 +1.4 +1.0 3.0 3.6 3.4 2.7 3.3 3.6 3.3 0.7 1.4 −0.1 −0.2 4.6 5.3 5.6 5.3 6.0 5.7 4.6 − − − − ns ns ns ns ns ns ns ns ns ns ns set-up time see Figs 7 and 8 50 pF nAn before nCPAB↑ or nBn before nCPBA↑ set-up time CP HIGH or LOW nAn before nLEAB↓ or nBn before nLEBA↓ see Figs 7 and 8 50 pF 2004 Oct 13 8 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state TEST CONDITIONS SYMBOL th PARAMETER WAVEFORMS hold time nAn after nCPAB↑ or nBn after nCPBA↑ hold time CP HIGH or LOW nAn after nLEAB↓ or nBn after nLEBA↓ fmax maximum clock frequency VCC = 3.0 V to 3.6 V; tr = tf ≤ 2.5 ns; note 3 tPHL/tPLH propagation delay nAn to nBn; nBn to nAn nLEBA to nAn; nLEAB to nBn nCPBA to nAn; nCPAB to nBn tPZH/tPZL tPHZ/tPLZ tW 3-state output enable time nOEAB to nBn 3-state output enable time nOEBA to nAn 3-state output disable time nOEAB to nBn 3-state output disable time nOEBA to nAn pulse width nLEAB or nLEBA HIGH pulse width nCPAB or nCPBA HIGH or LOW tsu see Figs 4 and 8 50 pF see Figs 5 and 8 50 pF see Figs 5 and 8 50 pF see Figs 6 and 8 50 pF see Figs 6 and 8 50 pF see Figs 6 and 8 50 pF see Figs 6 and 8 50 pF see Figs 5 and 8 50 pF see Figs 5 and 8 50 pF 1.0 1.3 1.4 1.0 1.1 1.4 1.3 3.3 3.3 +1.3 1.0 +1.3 1.2 150 CL 1.6 1.5 150 see Figs 7 and 8 50 pF see Figs 7 and 8 50 pF see Figs 5 and 8 50 pF MIN. 74ALVCH32501 TYP. 0.3 0.1 333 MAX. − − − UNIT ns ns MHz 3.0 3.4 3.3 2.4 2.5 2.9 3.1 0.9 1.1 −0.3 0.3 −0.4 0.1 340 4.2 4.8 4.9 4.6 5.0 5.0 4.2 − − − − − − − ns ns ns ns ns ns ns ns ns ns ns ns ns MHz set-up time see Figs 7 and 8 50 pF nAn before nCPAB↑ or nBn before nCPBA↑ set-up time CP HIGH or LOW nAn before nLEAB↓ or nBn before nLEBA↓ see Figs 7 and 8 50 pF see Figs 7 and 8 50 pF see Figs 7 and 8 50 pF see Figs 5 and 8 50 pF th hold time nAn after nCPAB↑ or nBn after nCPBA↑ hold time CP HIGH or LOW nAn after nLEAB↓ or nBn after nLEBA↓ fmax Notes maximum clock frequency 1. All typical values are measured at VCC = 2.5 V and Tamb = 25 °C. 2. All typical values are measured at Tamb = 25 °C. 3. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2004 Oct 13 9 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state AC WAVEFORMS 74ALVCH32501 handbook, halfpage VI nAn, nBn input GND t PHL VOH nBn, nAn output VOL VM t PLH VM MNA564 VCC 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 1.5 V 1.5 V VM 0.5 × VCC VCC 2.7 V 2.7 V VI VOL and VOH are typical output voltage drop that occur with the output load. Fig.4 Input nAn, nBn to output nBn, nAn propagation delay times. handbook, full pagewidth 1/fmax nLEAB, nLEBA, nCPAB, nCPBA input VI VM GND tW t PHL VOH nAn, nBn output VOL VM MNA565 t PLH VCC 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 1.5 V 1.5 V VM 0.5 × VCC VCC 2.7 V 2.7 V VI VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 Latch enable input (nLEAB, nLEBA) and clock input (nCPAB, nCPBA) to output propagation delays and their pulse width. 2004 Oct 13 10 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state OEAB input VM OEBA input t PLZ output LOW-to-OFF OFF-to-LOW VCC VM VOL t PHZ output HIGH-to-OFF OFF-to-HIGH VOH VY VM VX t PZH t PZL VM 74ALVCH32501 handbook, full pagewidth GND outputs enabled outputs disabled outputs enabled MNA566 VCC 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 1.5 V 1.5 V VM 0.5 × VCC VX VOL + 150 mV VOL + 300 mV VOL + 300 mV VY VOH − 150 mV VOH − 300 mV VOH − 300 mV VCC 2.7 V 2.7 V VI VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 3-state enable and disable times. handbook, full pagewidth VI nAn, nBn input GND th tsu nLEAB, nLEBA, VI VM MNA567 VM th tsu nCPAB, nCPBA input GND The shaded areas indicate when the input is permitted to change for predictable output performance. VCC 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 1.5 V 1.5 V VM 0.5 × VCC VCC 2.7 V 2.7 V VI VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 Data set-up and hold times for the nAn and nBn inputs to the nLEAB, nLEBA, nCPAB and nCPBA inputs. 2004 Oct 13 11 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state 74ALVCH32501 handbook, full pagewidth S1 VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 500 Ω VO RL 500 Ω 2 × VCC open GND MNA479 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 open 2 × VCC GND Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator. Fig.8 Load circuitry for switching times. 2004 Oct 13 12 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state PACKAGE OUTLINE 74ALVCH32501 LFBGA114: plastic low profile fine-pitch ball grid array package; 114 balls; body 16 x 5.5 x 1.05 mm SOT537-1 D B A ball A1 index area A E A2 A1 detail X e1 1/2 e ∅v M C A B C y1 C y e W V U T R P N M L K J H G F E D C B A ball A1 index area b ∅w M C e e2 123456 0 5 scale 10 mm X DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.41 0.31 A2 1.2 0.9 b 0.51 0.41 D 5.6 5.4 E 16.1 15.9 e 0.8 e1 4 e2 14.4 v 0.15 w 0.1 y 0.1 y1 0.2 OUTLINE VERSION SOT537-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-04 03-02-05 2004 Oct 13 13 Philips Semiconductors Product specification 36-bit universal bus transceiver with direction pin; 3-state DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION 74ALVCH32501 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2004 Oct 13 14 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2004 SCA76 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/02/pp15 Date of release: 2004 Oct 13 Document order number: 9397 750 14053