74AUP1G00GW

74AUP1G00 Low-power 2-input NAND gate Rev. 02 — 29 June 2006 Product data sheet 1. General description The 74AUP1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G00 provides the single 2-input NAND function. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-C Class 3A. Exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1G00GW 74AUP1G00GM 74AUP1G00GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C TSSOP5 XSON6 XSON6 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm Version SOT353-1 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Marking code pA pA pA Type number 74AUP1G00GW 74AUP1G00GM 74AUP1G00GF 5. Functional diagram B 1 2 B A 1 Y 4 2 mna097 & 4 A mna098 Y mna099 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning 74AUP1G00 74AUP1G00 B A 1 2 GND GND 3 001aaf016 B 5 VCC A 1 6 VCC B A 74AUP1G00 1 2 3 6 5 4 VCC n.c. Y 2 5 n.c. 3 4 Y GND 4 Y 001aaf017 001aaf018 Transparent top view Transparent top view Fig 4. Pin configuration SOT353-1 (TSSOP5) 74AUP1G00_2 Fig 5. Pin configuration SOT886 (XSON6) Rev. 02 — 29 June 2006 Fig 6. Pin configuration SOT891 (XSON6) © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet 2 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate 6.2 Pin description Table 3. Symbol B A GND Y n.c. VCC Pin description Pin TSSOP5 1 2 3 4 5 XSON6 1 2 3 4 5 6 data input B data input A ground (0 V) data output Y not connected supply voltage Description 7. Functional description Table 4. Input A L L H H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output B L H L H Y H H H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −0.5 [1] [1] Max +4.6 −50 +4.6 ±50 VCC + 0.5 +4.6 ±20 +50 −50 +150 250 Unit V mA V mA V V mA mA mA °C mW VO > VCC or VO < 0 V Active mode Power-down mode VO = 0 V to VCC −0.5 −0.5 −65 Tamb = −40 °C to +125 °C [2] - The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 3 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate 9. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input transition rise and fall rate VCC = 0.8 V to 3.6 V Active mode Power-down mode; VCC = 0 V Conditions Min 0.8 0 0 0 −40 0 Max 3.6 3.6 VCC 3.6 +125 200 Unit V V V V °C ns/V 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 °C VIH HIGH-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-state output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V 74AUP1G00_2 Conditions Min Typ Max - Unit V V V V 0.70 × VCC 0.65 × VCC 1.6 2.0 VCC − 0.1 1.11 1.32 2.05 1.9 2.72 2.6 - 0.30 × VCC V 0.35 × VCC V 0.7 0.9 0.1 0.3 × VCC 0.31 0.31 0.31 0.44 0.31 0.44 V V V V V V V V V V V V V V V V V V 0.75 × VCC - © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 4 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II IOFF ∆IOFF ICC ∆ICC CI CO VIH input leakage current power-off leakage current additional power-off leakage current supply current additional supply current input capacitance output capacitance HIGH-state input voltage Conditions VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-state output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF input leakage current power-off leakage current additional power-off leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V 0.1 0.3 × VCC 0.37 0.35 0.33 0.45 0.33 0.45 ±0.5 ±0.5 ±0.6 V V V V V V V V µA µA µA VCC − 0.1 0.7 × VCC 1.03 1.30 1.97 1.85 2.67 2.55 V V V V V V V V [1] Min - Typ 0.8 1.7 Max ±0.1 ±0.2 ±0.2 0.5 40 - Unit µA µA µA µA µA pF pF V V V V Tamb = −40 °C to +85 °C 0.70 × VCC 0.65 × VCC 1.6 2.0 - 0.30 × VCC V 0.35 × VCC V 0.7 0.9 V V 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 5 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC ∆ICC supply current additional supply current Conditions VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-state output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF ICC ∆ICC input leakage current power-off leakage current additional power-off leakage current supply current additional supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V [1] [1] Min - Typ - Max 0.9 50 Unit µA µA Tamb = −40 °C to +125 °C VIH HIGH-state input voltage 0.75 × VCC 0.70 × VCC 1.6 2.0 V V V V 0.25 × VCC V 0.30 × VCC V 0.7 0.9 0.11 0.41 0.39 0.36 0.50 0.36 0.50 ±0.75 ±0.75 ±0.75 1.4 75 V V V V V V V V V V V V V V V V V µA µA µA µA µA VCC − 0.11 0.6 × VCC 0.93 1.17 1.77 1.67 2.40 2.30 - 0.33 × VCC V [1] One input at VCC − 0.6 V, other input at VCC or GND. 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 6 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol tPHL, tPLH Parameter Conditions Min Typ [1] Max Unit Tamb = 25 °C; CL = 5 pF see Figure 7 HIGH-to-LOW and LOW-to-HIGH VCC = 0.8 V propagation delay A or B to Y VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 °C; CL = 10 pF tPHL, tPLH HIGH-to-LOW and see Figure 7 LOW-to-HIGH VCC = 0.8 V propagation delay A or B to Y VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 °C; CL = 15 pF tPHL, tPLH HIGH-to-LOW and see Figure 7 LOW-to-HIGH VCC = 0.8 V propagation delay A or B to Y VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 °C; CL = 30 pF tPHL, tPLH HIGH-to-LOW and see Figure 7 LOW-to-HIGH VCC = 0.8 V propagation delay A or B to Y VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 4.6 3.0 2.6 2.4 2.3 34.8 9.2 6.5 5.4 4.6 4.3 20.1 11.8 9.3 7.1 6.5 ns ns ns ns ns ns 3.4 2.8 2.0 1.7 1.6 24.5 6.9 5.0 4.1 3.5 3.2 14.8 8.9 7.0 5.3 4.9 ns ns ns ns ns ns 2.4 2.4 2.0 1.4 1.3 21.0 6.1 4.4 3.7 3.0 2.8 13.0 7.9 6.2 4.7 4.3 ns ns ns ns ns ns 2.5 2.0 1.6 1.3 1.0 17.5 5.3 3.8 3.1 2.5 2.2 11.0 6.8 5.3 4.0 3.6 ns ns ns ns ns ns 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 7 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol CPD Parameter Conditions [2] Min Typ [1] Max Unit Tamb = 25 °C power dissipation capacitance f = 1 MHz; VI = GND to VCC VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] All typical values are measured at nominal VCC. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. - 2.6 2.8 2.9 3.1 3.6 4.2 - pF pF pF pF pF pF Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol CL = 5 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 10 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 2.2 2.2 1.9 1.3 1.2 14.4 9.2 7.3 5.6 4.9 2.2 2.2 1.9 1.3 1.2 15.9 10.2 8.1 6.2 5.4 ns ns ns ns ns 2.1 1.8 1.4 1.1 1.0 12.2 7.8 6.2 4.7 4.2 2.1 1.8 1.4 1.1 1.0 13.5 8.6 6.9 5.2 4.7 ns ns ns ns ns Parameter Conditions −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 8 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol CL = 15 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 4.1 2.9 2.3 2.1 2.1 22.6 14.0 11.1 8.5 7.6 4.1 2.9 2.3 2.1 2.1 24.9 15.4 12.3 9.4 8.4 ns ns ns ns ns 3.1 2.5 2.0 1.5 1.4 16.5 10.5 8.3 6.4 5.7 3.1 2.5 2.0 1.5 1.4 18.2 11.6 9.2 7.1 6.3 ns ns ns ns ns Parameter Conditions −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit 12. Waveforms VI A, B input GND t PHL VOH Y output VOL VM mna612 VM t PLH Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The data input (A or B) to output (Y) propagation delays Table 10. VCC 0.8 V to 3.6 V Measurement points Output VM 0.5 × VCC Input VM 0.5 × VCC VI VCC tr = tf ≤ 3.0 ns Supply voltage 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 9 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate VCC VEXT 5 kΩ PULSE GENERATOR VI VO DUT RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times Table 11. VCC 0.8 V to 3.6 V [1] Test data Load CL 5 pF, 10 pF, 15 pF and 30 pF RL [1] Supply voltage VEXT tPLH, tPHL open tPZH, tPHZ GND tPZL, tPLZ 2 × VCC 5 kΩ or 1 MΩ For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 10 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 D E A X c y HE vMA Z 5 4 A2 A1 (A3) θ A 1 e e1 bp 3 wM detail X Lp L 0 1.5 scale 3 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.1 0 A2 1.0 0.8 A3 0.15 bp 0.30 0.15 c 0.25 0.08 D(1) 2.25 1.85 E(1) 1.35 1.15 e 0.65 e1 1.3 HE 2.25 2.0 L 0.425 Lp 0.46 0.21 v 0.3 w 0.1 y 0.1 Z(1) 0.60 0.15 θ 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC MO-203 JEITA SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 9. Package outline SOT353-1 (TSSOP5) 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 11 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 10. Package outline SOT886 (XSON6) 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 12 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 L1 e L 6 e1 5 e1 4 A A1 D E terminal 1 index area 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-03-11 05-04-06 Fig 11. Package outline SOT891 (XSON6) 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 13 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate 14. Abbreviations Table 12: Acronym CDM CMOS DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor Transistor Logic 15. Revision history Table 13. Revision history Release date 20060629 Data sheet status Product data sheet Change notice Supersedes 74AUP1G00_1 Document ID 74AUP1G00_2 Modifications: 74AUP1G00_1 • • ESD HBM and CPD values modified in Section 2, Table 8 Added type number 74AUP1G00GF (XSON6/SOT891) package Product data sheet - 20050711 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 14 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 16.2 Definitions Draft — The document is a draft version only. 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Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 15 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Date of release: 29 June 2006 Document identifier: 74AUP1G00_2