74AUP1G32GM

74AUP1G32 Low-power 2-input OR gate Rev. 01 — 2 August 2005 Product data sheet 1. General description The 74AUP1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G32 provides the single 2-input OR function. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-C exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3 ns. Symbol Parameter Conditions CL = 5 pF; RL = 1 MΩ; VCC = 0.8 V CL = 5 pF; RL = 1 MΩ; VCC = 1.1 V to 1.3 V CL = 5 pF; RL = 1 MΩ; VCC = 1.4 V to 1.6 V CL = 5 pF; RL = 1 MΩ; VCC = 1.65 V to 1.95 V CL = 5 pF; RL = 1 MΩ; VCC = 2.3 V to 2.7 V CL = 5 pF; RL = 1 MΩ; VCC = 3.0 V to 3.6 V Ci CPD input capacitance power dissipation capacitance VCC = 1.8 V; f = 10 MHz VCC = 3.3 V; f = 10 MHz [1] [2] [1] [2] Min 2.4 1.6 1.4 1.1 1.0 - Typ 16.8 5.1 3.6 3.0 2.4 2.1 0.8 3.5 4.3 Max 10.9 6.6 5.2 3.9 3.5 - Unit ns ns ns ns ns ns pF pF pF tPHL, tPLH propagation delay A or B to Y [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. The condition is VI = GND to VCC [2] 4. Ordering information Table 2: Ordering information Package Temperature range Name 74AUP1G32GW 74AUP1G32GM −40 °C to +125 °C −40 °C to +125 °C TSSOP5 XSON6 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm Version SOT353-1 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 5. Marking Table 3: Marking Marking code pG pG Type number 74AUP1G32GW 74AUP1G32GM 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 2 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 6. Functional diagram 1 2 B A Y 4 1 2 ≥1 4 mna164 mna165 Fig 1. Logic symbol Fig 2. IEC logic symbol B Y A mna166 Fig 3. Logic diagram 7. Pinning information 7.1 Pinning 32 B B A 1 2 5 VCC 1 6 VCC A 2 5 n.c. 32 GND 3 4 Y 4 001aab640 GND 3 Y 001aab641 Transparent top view Fig 4. Pin configuration SOT353-1 (TSSOP5) Fig 5. Pin configuration SOT886 (XSON6) 7.2 Pin description Table 4: Symbol B A GND Y n.c. VCC Pin description Pin TSSOP5 1 2 3 4 5 XSON6 1 2 3 4 5 6 data input B data input A ground (0 V) data output Y not connected supply voltage Description 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 3 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 8. Functional description 8.1 Function table Table 5: Input A L L H H [1] H = HIGH voltage level; L = LOW voltage level. Function table [1] Output B L H L H Y L H H H 9. Limiting values Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current quiescent supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −0.5 [1] [1] Max +4.6 −50 +4.6 ±50 Unit V mA V mA VO > VCC or VO < 0 V active mode Power-down mode VO = 0 V to VCC −0.5 −0.5 −65 VCC + 0.5 V +4.6 ±20 +50 −50 +150 250 V mA mA mA °C mW Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 4 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 10. Recommended operating conditions Table 7: Symbol VCC VI VO Tamb tr, tf Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature input rise and fall times VCC = 0.8 V to 3.6 V active mode Power-down mode; VCC = 0 V Conditions Min 0.8 0 0 0 −40 0 Max 3.6 3.6 VCC 3.6 +125 200 Unit V V V V °C ns/V 11. Static characteristics Table 8: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 °C VIH HIGH-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V VOH HIGH-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-state output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V 9397 750 14678 Conditions Min Typ Max - Unit V V V V 0.70 × VCC 0.65 × VCC 1.6 2.0 VCC − 0.1 1.11 1.32 2.05 1.9 2.72 2.6 - 0.30 × VCC V 0.35 × VCC V 0.7 0.9 0.1 0.3 × VCC 0.31 0.31 0.31 0.44 0.31 0.44 V V V V V V V V V V V V V V V V V V 0.75 × VCC - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 5 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate Table 8: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ILI IOFF ∆IOFF ICC ∆ICC Ci Co VIH input leakage current power-off leakage current additional power-off leakage current quiescent supply current Conditions VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V [1] Min - Typ 1.5 3 Max ±0.1 ±0.2 ±0.2 0.5 40 - Unit µA µA µA µA µA pF pF V V V V additional quiescent supply VI = VCC − 0.6 V; IO = 0 A; current VCC = 3.3 V input capacitance output capacitance HIGH-state input voltage VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = −40 °C to +85 °C 0.70 × VCC 0.65 × VCC 1.6 2.0 VCC − 0.1 0.7 × VCC 1.03 1.30 1.97 1.85 2.67 2.55 - VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 0.30 × VCC V 0.35 × VCC V 0.7 0.9 0.1 0.3 × VCC 0.37 0.35 0.33 0.45 0.33 0.45 ±0.5 ±0.5 ±0.6 V V V V V V V V V V V V V V V V V V µA µA µA VOH HIGH-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-state output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V ILI IOFF ∆IOFF input leakage current power-off leakage current additional power-off leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 6 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate Table 8: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ICC ∆ICC quiescent supply current Conditions VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V [1] Min - Typ - Max 0.9 50 Unit µA µA additional quiescent supply VI = VCC − 0.6 V; IO = 0 A; current VCC = 3.3 V HIGH-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = −40 °C to +125 °C VIH 0.75 × VCC 0.70 × VCC 1.6 2.0 V V V V VIL LOW-state input voltage VCC = 0.8 V VCC = 0.9 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 0.25 × VCC V 0.30 × VCC V 0.7 0.9 0.11 0.41 0.39 0.36 0.50 0.36 0.50 ±0.75 ±0.75 ±0.75 1.4 75 V V V V V V V V V V V V V V V V V µA µA µA µA µA VOH HIGH-state output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VCC − 0.11 0.6 × VCC 0.93 1.17 1.77 1.67 2.40 2.30 [1] - VOL LOW-state output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V 0.33 × VCC V ILI IOFF ∆IOFF ICC ∆ICC input leakage current power-off leakage current additional power-off leakage current quiescent supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V quiescent additional supply VI = VCC − 0.6 V; IO = 0 A; current VCC = 3.3 V - [1] One input at VCC − 0.6 V, other input at VCC or GND. 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 7 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 12. Dynamic characteristics Table 9: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7 Symbol tPHL, tPLH Parameter Conditions Min Typ [1] Max Unit Tamb = 25 °C; CL = 5 pF propagation delay A or B to Y see Figure 6 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 °C; CL = 10 pF tPHL, tPLH propagation delay A or B to Y see Figure 6 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 °C; CL = 15 pF tPHL, tPLH propagation delay A or B to Y see Figure 6 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V Tamb = 25 °C; CL = 30 pF tPHL, tPLH propagation delay A or B to Y see Figure 6 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 4.5 3.4 2.6 2.3 2.2 34.1 9.0 6.3 5.3 4.4 4.2 19.1 11.3 8.9 7.0 6.4 ns ns ns ns ns ns 3.3 2.3 2.0 1.7 1.5 23.8 6.7 4.8 4.0 3.3 3.1 14.3 8.6 6.7 5.3 4.9 ns ns ns ns ns ns 2.3 1.9 1.7 1.4 1.3 20.3 5.9 4.2 3.5 2.9 2.7 12.7 7.7 6.0 4.6 4.3 ns ns ns ns ns ns 2.4 1.6 1.4 1.1 1.0 16.8 5.1 3.6 3.0 2.4 2.1 10.9 6.6 5.2 3.9 3.5 ns ns ns ns ns ns 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 8 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate Table 9: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7 Symbol CPD Parameter Conditions [2] [3] Min Typ [1] Max Unit Tamb = 25 °C power dissipation capacitance f = 10 MHz VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] All typical values are measured at nominal VCC. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. The condition is VI = GND to VCC. - 3.2 3.4 3.4 3.5 3.9 4.3 - pF pF pF pF pF pF [3] Table 10: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7 Symbol CL = 5 pF tPHL, tPLH propagation delay A or B to Y see Figure 6 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 10 pF tPHL, tPLH propagation delay A or B to Y see Figure 6 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 2.1 1.7 1.5 1.3 1.2 13.8 8.7 6.9 5.5 5.0 2.1 1.7 1.5 1.3 1.2 15.2 9.6 7.7 6.1 5.5 ns ns ns ns ns 2.1 1.4 1.2 1.0 0.9 11.9 7.5 6.0 4.6 4.1 2.1 1.4 1.2 1.0 0.9 13.2 8.3 6.6 5.1 4.6 ns ns ns ns ns Parameter Conditions −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 9 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate Table 10: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7 Symbol CL = 15 pF tPHL, tPLH propagation delay A or B to Y see Figure 6 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 30 pF tPHL, tPLH propagation delay A or B to Y see Figure 6 VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V 4.0 2.9 2.4 2.2 2.1 21.5 13.3 10.7 8.4 7.7 4.0 2.9 2.4 2.2 2.1 23.7 14.7 11.8 9.3 8.5 ns ns ns ns ns 3.0 2.0 1.8 1.6 1.5 15.6 9.8 7.9 6.3 5.8 3.0 2.0 1.8 1.6 1.5 17.2 10.8 8.7 6.9 6.4 ns ns ns ns ns Parameter Conditions −40 °C to +85 °C Min Max −40 °C to +125 °C Min Max Unit 13. Waveforms VI A, B input GND t PHL VOH Y output VOL VM mna615 VM t PLH Measurement points are given in Table 11. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 6. The data input (A or B) to output (Y) propagation delays Table 11: VCC 0.8 V to 3.6 V Measurement points Output VM 0.5 × VCC Input VM 0.5 × VCC VI VCC tr = tf ≤ 3.0 ns Supply voltage 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 10 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate VCC VEXT 5 kΩ PULSE GENERATOR VI VO DUT RT CL RL 001aac521 Test data is given in Table 12. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance RT = Termination resistance should be equal to the output impedance Zo of the pulse generator Fig 7. Load circuitry for switching times Table 12: VCC 0.8 V to 3.6 V [1] Test data Load CL RL [1] Supply voltage VEXT tPLH, tPHL tPZH, tPHZ GND tPZL, tPLZ 2 × VCC 5 pF, 10 pF, 5 kΩ or 1 MΩ open 15 pF and 30 pF For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 11 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 14. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 D E A X c y HE vMA Z 5 4 A2 A1 (A3) θ A 1 e e1 bp 3 wM detail X Lp L 0 1.5 scale 3 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.1 0 A2 1.0 0.8 A3 0.15 bp 0.30 0.15 c 0.25 0.08 D(1) 2.25 1.85 E(1) 1.35 1.15 e 0.65 e1 1.3 HE 2.25 2.0 L 0.425 Lp 0.46 0.21 v 0.3 w 0.1 y 0.1 Z(1) 0.60 0.15 θ 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC MO-203 JEITA SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Fig 8. Package outline SOT353-1 (TSSOP5) 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 12 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 9. Package outline SOT886 (XSON6) 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 13 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 15. Abbreviations Table 13: Acronym CMOS TTL HBM ESD MM CDM Abbreviations Description Complementary Metal Oxide Semiconductor Transistor Transistor Logic Human Body Model ElectroStatic Discharge Machine Model Charged Device Model 16. Revision history Table 14: Revision history Release date 20050802 Data sheet status Product data sheet Change notice Doc. number 9397 750 14678 Supersedes Document ID 74AUP1G32_1 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 14 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 17. Data sheet status Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 20. Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 9397 750 14678 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 2 August 2005 15 of 16 Philips Semiconductors 74AUP1G32 Low-power 2-input OR gate 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 9 10 11 12 13 14 15 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information . . . . . . . . . . . . . . . . . . . . 15 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 2 August 2005 Document number: 9397 750 14678 Published in The Netherlands