74AUP1G97GW

74AUP1G97 Low-power configurable multiple function gate Rev. 01 — 7 November 2006 Product data sheet 1. General description The 74AUP1G97 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G97 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to VCC or GND. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the input hysteresis voltage VH. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s ESD protection: x HBM JESD22-A114-D Class 3A exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1G97GW 74AUP1G97GM 74AUP1G97GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SC-88 XSON6 XSON6 Description plastic surface-mounted package; 6 leads Version SOT363 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Marking code aV aV aV Type number 74AUP1G97GW 74AUP1G97GM 74AUP1G97GF 5. Functional diagram 3 4 B 1 A Y C 6 001aad998 Fig 1. Logic symbol 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 2 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 6. Pinning information 6.1 Pinning 74AUP1G97 74AUP1G97 B GND 1 2 6 5 C GND VCC A A 3 001aad999 B 1 6 C B GND 74AUP1G97 1 2 3 6 5 4 C VCC Y 2 5 VCC 3 4 Y A 4 Y 001aae000 001aae001 Transparent top view Transparent top view Fig 2. Pin configuration SOT363 (SC-88) Fig 3. Pin configuration SOT886 (XSON6) Fig 4. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Symbol B GND A Y VCC C Pin description Pin 1 2 3 4 5 6 Description data input B ground (0 V) data input A data output Y supply voltage data input C 7. Functional description Table 4. Input C L L L L H H H H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output B L L H H L L H H A L H L H L H L H Y L L H H L H L H 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 3 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 7.1 Logic configurations Table 5. Function selection table Figure see Figure 5 see Figure 6 see Figure 7 see Figure 7 see Figure 8 see Figure 8 see Figure 9 see Figure 10 see Figure 11 Logic function 2-input MUX 2-input AND 2-input OR with one input inverted 2-input NAND with one input inverted 2-input AND with one input inverted 2-input NOR with one input inverted 2-input OR Inverter Buffer VCC B B Y A A C 001aae002 VCC 1 A C Y A 2 3 6 5 4 Y 001aae003 1 2 3 6 5 4 C C Y Fig 5. 2-input MUX Fig 6. 2-input AND gate VCC VCC A C Y 1 2 6 5 4 C B C Y B 1 2 6 5 4 C A C Y A 3 Y 001aae004 B C Y 3 Y 001aae005 Fig 7. 2-input NAND gate with input A inverted or 2-input OR gate with input C inverted Fig 8. 2-input NOR gate with input B inverted or 2-input AND gate with input C inverted VCC B B C Y 1 2 3 6 5 C 4 Y 3 001aae006 VCC C 1 Y 2 6 5 4 Y 001aae007 C Fig 9. 2-input OR gate Fig 10. Inverter 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 4 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate VCC B B Y 1 2 3 6 5 4 Y 001aae008 Fig 11. Buffer 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage Conditions VI < 0 V [1] Min −0.5 −0.5 [1] Max +4.6 −50 +4.6 ±50 +4.6 ±20 50 −50 +150 250 Unit V mA V mA V mA mA mA °C mW output clamping current VO > VCC or VO < 0 V output voltage output current supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C [2] Active mode and Power-down mode VO = 0 V to VCC −0.5 −65 - The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 7. Symbol VCC VI VO Tamb Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature Active mode Power-down mode; VCC = 0 V Conditions Min 0.8 0 0 0 −40 Max 3.6 3.6 VCC 3.6 +125 Unit V V V V °C 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 5 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 °C VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF ICC ∆ICC CI CO VOH input leakage current power-off leakage current additional power-off leakage current supply current additional supply current input capacitance output capacitance HIGH-level output voltage VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V VCC = 0 V to 3.6 V; VI = GND or VCC VO = GND; VCC = 0 V VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V 74AUP1G97_1 Conditions Min Typ Max Unit VCC − 0.1 1.11 1.32 2.05 1.9 2.72 2.6 [1] 1.1 1.8 0.1 0.3 × VCC 0.31 0.31 0.31 0.44 0.31 0.44 ±0.1 ±0.2 ±0.2 0.5 40 - V V V V V V V V V V V V V V V V µA µA µA µA µA pF pF 0.75 × VCC - - Tamb = −40 °C to +85 °C VCC − 0.1 0.7 × VCC 1.03 1.30 1.97 1.85 2.67 2.55 V V V V V V V V © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 6 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage Conditions VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF ∆IOFF ICC ∆ICC input leakage current power-off leakage current additional power-off leakage current supply current additional supply current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V IO = −1.1 mA; VCC = 1.1 V IO = −1.7 mA; VCC = 1.4 V IO = −1.9 mA; VCC = 1.65 V IO = −2.3 mA; VCC = 2.3 V IO = −3.1 mA; VCC = 2.3 V IO = −2.7 mA; VCC = 3.0 V IO = −4.0 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V IO = 1.1 mA; VCC = 1.1 V IO = 1.7 mA; VCC = 1.4 V IO = 1.9 mA; VCC = 1.65 V IO = 2.3 mA; VCC = 2.3 V IO = 3.1 mA; VCC = 2.3 V IO = 2.7 mA; VCC = 3.0 V IO = 4.0 mA; VCC = 3.0 V II IOFF input leakage current power-off leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V VI or VO = 0 V to 3.6 V; VCC = 0 V 0.11 0.41 0.39 0.36 0.50 0.36 0.50 ±0.75 ±0.75 V V V V V V V µA µA 0.33 × VCC V VCC − 0.11 0.6 × VCC 0.93 1.17 1.77 1.67 2.40 2.30 V V V V V V V V [1] Min - Typ - Max 0.1 0.3 × VCC 0.37 0.35 0.33 0.45 0.33 0.45 ±0.5 ±0.5 ±0.6 0.9 50 Unit V V V V V V V V µA µA µA µA µA Tamb = −40 °C to +125 °C VOH HIGH-level output voltage 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 7 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ∆IOFF ICC ∆ICC additional power-off leakage current supply current additional supply current Conditions VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V [1] Min - Typ - Max ±0.75 1.4 75 Unit µA µA µA [1] One input at VCC − 0.6 V, other input at VCC or GND. 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter Conditions Min CL = 5 pF tpd propagation delay A, B, C to Y; see Figure 12 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 10 pF tpd propagation delay A, B, C to Y; see Figure 12 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 15 pF tpd propagation delay A, B, C to Y; see Figure 12 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [2] [2] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max Max (85 °C) (125 °C) Unit 2.8 2.3 2.2 2.0 1.9 23.0 6.6 4.7 3.9 3.2 2.9 12.6 7.6 6.2 4.5 3.9 2.5 2.5 2.0 1.7 1.5 13.0 8.2 6.8 5.1 4.1 13.2 8.6 7.2 5.3 4.3 ns ns ns ns ns ns 3.2 2.6 2.5 2.4 2.3 26.6 7.4 5.3 4.5 3.7 3.4 14.3 8.7 7.0 5.2 4.6 2.9 2.8 2.3 2.1 1.9 14.9 9.4 7.8 5.9 4.9 15.2 9.8 8.2 6.1 5.1 ns ns ns ns ns ns 3.6 2.9 2.8 2.7 2.5 30.1 8.2 5.9 5.0 4.2 3.8 16.0 9.6 7.8 5.8 5.1 3.2 3.1 2.5 2.4 2.2 16.7 10.4 8.7 6.5 5.5 17.0 10.9 9.1 6.9 5.7 ns ns ns ns ns ns 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 8 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter Conditions Min CL = 30 pF tpd propagation delay A, B, C to Y; see Figure 12 VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V CL = 5 pF, 10 pF, 15 pF and 30 pF CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC VCC = 0.8 V VCC = 1.1 V to 1.3 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V [1] [2] [3] All typical values are measured at nominal VCC. tpd is the same as tPLH and tPHL CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [3] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max Max (85 °C) (125 °C) Unit 4.6 3.7 3.5 3.4 3.2 38.3 10.5 7.4 6.3 5.3 4.9 20.9 12.2 9.9 7.4 6.6 4.0 3.8 3.2 3.1 2.8 21.8 13.3 11.1 8.3 7.0 22.2 14.0 11.8 8.8 7.4 ns ns ns ns ns ns - 2.9 3.1 3.2 3.4 4.0 4.6 - - - - pF pF pF pF pF pF 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 9 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 12. Waveforms VI A, B, C input GND t PHL VOH Y output VOL t PLH VOH Y output VOL VM VM t PHL VM VM t PLH VM VM 001aab593 Measurement points are given in Table 10. VOL and VOH are typical output voltage drop that occur with the output load. Fig 12. Input A, B and C to output Y propagation delay times Table 10. VCC 0.8 V to 3.6 V Measurement points Output VM 0.5 × VCC Input VM 0.5 × VCC VI VCC tr = tf ≤ 3.0 ns Supply voltage 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 10 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate VCC VEXT 5 kΩ PULSE GENERATOR VI VO DUT RT CL RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 13. Load circuitry for switching times Table 11. VCC 0.8 V to 3.6 V [1] Test data Load CL 5 pF, 10 pF, 15 pF and 30 pF RL[1] 5 kΩ or 1 MΩ VEXT tPLH, tPHL open tPZH, tPHZ GND tPZL, tPLZ 2 × VCC Supply voltage For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 13. Transfer characteristics Table 12. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 13. Symbol Parameter Conditions Min VT+ positive-going see Figure 14 and Figure 15 threshold voltage VCC = 0.8 V VCC = 1.1 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VT− negative-going see Figure 14 and Figure 15 threshold voltage VCC = 0.8 V VCC = 1.1 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V 25 °C Typ Max −40 °C to +125 °C Min Max (85 °C) 0.60 0.90 1.11 1.29 1.77 2.29 0.60 0.65 0.75 0.84 1.04 1.24 Max (125 °C) 0.62 0.92 1.13 1.31 1.80 2.32 0.60 0.65 0.75 0.84 1.04 1.24 V V V V V V V V V V V V Unit 0.30 0.53 0.74 0.91 1.37 1.88 0.10 0.26 0.39 0.47 0.69 0.88 - 0.60 0.90 1.11 1.29 1.77 2.29 0.60 0.65 0.75 0.84 1.04 1.24 0.30 0.53 0.74 0.91 1.37 1.88 0.10 0.26 0.39 0.47 0.69 0.88 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 11 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate Table 12. Transfer characteristics …continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 13. Symbol Parameter Conditions Min VH hysteresis voltage (VT+ − VT−); see Figure 14, Figure 15, Figure 16 and Figure 17 VCC = 0.8 V VCC = 1.1 V VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V 0.07 0.08 0.18 0.27 0.53 0.79 0.50 0.46 0.56 0.66 0.92 1.31 0.07 0.08 0.18 0.27 0.53 0.79 0.50 0.46 0.56 0.66 0.92 1.31 0.50 0.46 0.56 0.66 0.92 1.31 V V V V V V 25 °C Typ Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit 14. Waveforms transfer characteristics VO VT+ VI VT− VH VO VH VT− VT+ VI mna207 mna208 VT+ and VT− limits at 70 % and 20 %. Fig 14. Transfer characteristic Fig 15. Definition of VT+, VT− and VH 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 12 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 240 ICC (µA) 160 001aad691 80 0 0 0.4 0.8 1.2 1.6 VI (V) 2.0 Fig 16. Typical transfer characteristics; VCC = 1.8 V 1200 ICC (µA) 800 001aad692 400 0 0 1.0 2.0 VI (V) 3.0 Fig 17. Typical transfer characteristics; VCC = 3.0 V 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 13 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 15. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 18. Package outline SOT363 (SC-88) 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 14 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 19. Package outline SOT886 (XSON6) 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 15 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 L1 e L 6 e1 5 e1 4 A A1 D E terminal 1 index area 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-03-11 05-04-06 Fig 20. Package outline SOT891 (XSON6) 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 16 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 16. Abbreviations Table 13. Acronym CDM CMOS DUT ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 17. Revision history Table 14. Revision history Release date 20061107 Data sheet status Product data sheet Change notice Supersedes Document ID 74AUP1G97_1 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 17 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74AUP1G97_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 7 November 2006 18 of 19 NXP Semiconductors 74AUP1G97 Low-power configurable multiple function gate 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Logic configurations . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Transfer characteristics. . . . . . . . . . . . . . . . . . 11 Waveforms transfer characteristics . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 November 2006 Document identifier: 74AUP1G97_1