74AVCM162835DGG

INTEGRATED CIRCUITS 74AVCM162835 18-bit registered driver with 15 Ω termination resistors (3-State) Product specification File under Integrated Circuits ICL03 2001 Apr 20 Philips Semiconductors Philips Semiconductors Product specification 18-bit registered driver with 15 Ω termination resistors (3-State) 74AVCM162835 FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A/5/7. • CMOS low power consumption • Input/output tolerant up to 3.6 V • Low inductance multiple VCC and GND pins for minimum noise and ground bounce PIN CONFIGURATION NC NC Y0 GND Y1 Y2 VCC Y3 Y4 Y5 GND Y6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND NC A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 CP GND • Integrated 15 Ω termination resistors to minimize output overshoot and undershoot • Full PC133 solution provided when used with PCK2510S and CBT16292 DESCRIPTION The 74AVCM162835 is a 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion). Y7 Y8 Y9 Y10 Y11 GND Y12 Y13 Y14 VCC Y15 Y16 GND Y17 OE LE SH00130 QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns; CL = 30 pF. PARAMETER SYMBOL tPHL/tPLH Propagation delay An to Yn Propagation delay LE to Yn; CP to Yn Input capacitance Power dissipation capacitance per buffer dissi ca er buffer VI = GND to VCC1 GND to Outputs enabled Output disabled VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V CONDITIONS TYPICAL 2.6 2.0 1.7 2.8 2.2 1.8 5.0 25 6 UNIT ns tPHL/tPLH CI CPD ns pF pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES 56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II TEMPERATURE RANGE –40 to +85 °C ORDER CODE 74AVCM162835DGG DRAWING NUMBER SOT364-1 2001 Apr 20 2 853-2170 26096 Philips Semiconductors Product specification 18-bit registered driver with 15 Ω termination resistors (3-State) 74AVCM162835 PIN DESCRIPTION PIN NUMBER 1, 2, 55 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 4, 11, 18, 25, 32, 39, 46, 53, 56 7, 22, 35, 50 27 28 30 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 SYMBOL NC Y0 to Y17 NAME AND FUNCTION No connection Data outputs LOGIC SYMBOL (IEEE/IEC) OE CP LE 27 30 28 C3 G2 EN1 2C3 GND VCC OE LE CP A0 to A17 Ground (0V) Positive supply voltage Output enable input (active LOW) Latch enable input (active HIGH) Clock input Data inputs Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1∇ 1 3D 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 LOGIC SYMBOL Y12 Y13 Y14 OE Y15 Y16 CP Y17 SH00154 LE A0 FUNCTION TABLE D LE CP Y0 INPUTS OE H L L L L SH00138 LE X H H L L L L CP X X X ↑ ↑ H L A X L H L H X X OUTPUTS Z L H L H Y01 Y02 TO THE 17 OTHER CHANNELS L L H L X Z ↑ = = = = = HIGH voltage level LOW voltage level Don’t care High impedance “off” state LOW-to-HIGH level transition NOTES: 1. Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low. 2. Output level before the indicated steady-state input conditions were established. 2001 Apr 20 3 Philips Semiconductors Product specification 18-bit registered driver with 15 Ω termination resistors (3-State) 74AVCM162835 168-pin SDR SDRAM DIMM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM BACK SIDE SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM FRONT SIDE 74AVCM16835 74AVCM16835 74AVCM16835 PCK2509S or PCK2510S The PLL clock distribution device and AVCM registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER DC supply voltage (according to JEDEC Low Voltage Standards) VCC DC supply voltage (for low voltage applications) VI VO Tamb tr, tf DC Input voltage range DC output voltage range; output 3-State DC output voltage range; output HIGH or LOW state Operating free-air temperature range Input rise and fall times VCC = 1.65 to 2.3 V VCC = 2.3 to 3.0 V VCC = 3.0 to 3.6 V CONDITIONS MIN 1.65 2.3 3.0 1.2 0 0 0 –40 0 0 0 MAX 1.95 2.7 3.6 3.6 3.6 3.6 V VCC +85 30 20 10 °C ns/V V UNIT SDRAM SW00408 V 2001 Apr 20 4 Philips Semiconductors Product specification 18-bit registered driver with 15 Ω termination resistors (3-State) 74AVCM162835 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER VCC IIK VI IOK VO VO IO IGND, ICC Tstg PTOT DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output 3-State DC output voltage; output HIGH or LOW state DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package –plastic thin-medium-shrink (TSSOP) For temperature range: –40 to +125 °C above +55 °C derate linearly with 8 mW/K VI t0 For all inputs1 VO uVCC or VO t 0 Note 1 Note 1 VO = 0 to VCC CONDITIONS RATING –0.5 to +4.6 –50 –0.5 to 4.6 "50 –0.5 to 4.6 –0.5 to VCC +0.5 "50 "100 –65 to +150 600 UNIT V mA V mA V V mA mA °C mW NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VCC = 1.2 V VIH HIGH level Input voltage level In voltage VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 1.2 V VIL LOW level Input voltage level In voltage VCC = 1.65 to 1.95 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 1.65 to 3.6 V; VI = VIH or VIL; IO = –100 µA VOH HIGH level output voltage VCC = 1.65 V; VI = VIH or VIL; IO = –4 mA VCC = 2.3 V; VI = VIH or VIL; IO = –8 mA VCC = 3.0 V; VI = VIH or VIL; IO = –12 mA VCC = 1.65 to 3.6 V; VI = VIH or VIL; IO = 100 µA VOL LOW level output voltage VCC = 1.65 V; VI = VIH or VIL; IO = 4 mA VCC = 2.3 V; VI = VIH or VIL; IO = 8 mA VCC = 3.0 V; VI = VIH or VIL; IO = 12 mA II IOFF IIHZ/IILZ IOZ Input leakage current 3-State output OFF-state current 3-State output OFF-state current VCC = 1.65 to 3.6 V; to VI = VCC or GND or GND VCC = 0 V; VI or VO = 3.6 V VCC = 1.65 to 3.6 V; VI = VCC or GND VCC = 1.65 to 2.7 V; VI = VIH or VIL; VO = VCC or GND VCC = 3.0 to 3.6 V; VI = VIH or VIL; VO = VCC or GND VCC = 1.65 to 2.7 V; VI = VCC or GND; IO = 0 VCC = 3.0 to 3.6 V; VI = VCC or GND; IO = 0 TEST CONDITIONS Temp = –40 to +85 °C MIN VCC 0.65VCC 1.7 2.0 – – – – VCC*0.20 VCC*0.45 VCC*0.55 VCC*0.70 – – – – – – – – – – – TYP1 – 0.9 1.2 1.5 – 0.9 1.2 1.5 VCC VCC*0.10 VCC*0.28 VCC*0.32 GND 0.10 0.26 0.36 0.1 0.1 0.1 0.1 0.1 0.1 0.2 MAX – – – – GND 0.35VCC 0.7 0.8 – – – – 0.20 0.45 0.55 0.70 2.5 "10 12.5 5 µA 10 20 40 µA µA µA µA V V V V UNIT 3-State out 3-State output OFF-state current OFF-state current ICC Quiescent supply current su current NOTES: 1. All typical values are at Tamb = 25 °C. 2001 Apr 20 5 Philips Semiconductors Product specification 18-bit registered driver with 15 Ω termination resistors (3-State) 74AVCM162835 AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF SYMBOL PARAMETER Propagation delay An to Yn tPHL/tPLH Propagation delay LE to Yn Propagation delay CP to Yn tPZH/tPZL tPHZ/tPLZ tW 3-State output enable time OE to Yn 3-State output disable time OE to Yn CP pulse width HIGH or LOW LE pulse width HIGH Set-up time An to CP tSU Set-up time An to LE HIGH Set-up time An to LE LOW Hold time An to CP th Hold time An to LE HIGH Hold time An to LE LOW Fmax Maximum clock pulse frequency WAVEFORM 1, 7 2, 7 3, 7 6, 7 6, 7 3, 7 2, 7 5, 7 4, 7 4, 7 5, 7 4, 7 4, 7 3, 7 VCC = 3.3 ± 0.3 V MIN TYP1 MAX 0.7 0.7 0.7 1.0 1.0 1.0 1.0 0.7 0.5 0.5 0.9 1.6 1.4 500 1.7 1.8 1.7 2.3 2.3 – – – – – – – – – 2.5 2.7 2.5 4.5 3.5 – – – – – – – – – LIMITS VCC = 2.5 ± 0.2 V VCC = 1.8 ± 0.15 V MIN TYP1 MAX MIN TYP1 MAX 0.8 0.8 0.8 1.0 1.0 1.2 1.2 0.7 0.5 0.5 0.9 1.7 1.5 400 2.0 2.2 2.0 2.5 2.2 – – – – – – – – – 3.1 3.3 3.0 4.5 4.0 – – – – – – – – – 1.0 1.0 1.0 1.5 1.5 2.0 2.0 0.7 0.5 0.6 1.0 2.0 1.7 250 2.6 2.8 2.6 3.0 3.5 – – – – – – – – – 4.5 5.0 4.5 6.5 6.5 – – – – – – – – – VCC = 1.2 V MIN TYP – – – – – – – 1.0 0.2 2.0 1.5 3.2 2.8 – 5.2 5.6 5.2 5.5 6.9 – ns – – ns – – – ns – – – ns MHz ns ns ns ns UNIT NOTES: 1. All typical values are measured at Tamb = 25 °C and at VCC = 1.8 V, 2.5 V, 3.3 V. 2001 Apr 20 6 Philips Semiconductors Product specification 18-bit registered driver with 15 Ω termination resistors (3-State) 74AVCM162835 VM = 0.5 VCC VX = VOL + 0.300 V VY = VOH – 0.300 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC An INPUT GND LE INPUT AC WAVEFORMS FOR VCC = 2.3 V TO 2.7 V AND VCC < 2.3 V RANGE VM = 0.5 VCC VX = VOL + 0.15 V VY = VOH – 0.15 V VOL and VOH are the typical output voltage drop that occur with the output load. VI = VCC VI An INPUT GND tPHL VOH Yn OUTPUT VOL NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V VM tPLH VM GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5VCC at VCC = 2.3 to 2.7V Waveform 4. Data set-up and hold times for the An input to the LE input CP INPUT GND An INPUT GND VOH SH00132 Yn OUTPUT VOL Waveform 1. Input (An) to output (Yn) propagation delay VI LE INPUT GND VM tW VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5VCC at VCC = 2.3 to 2.7 V SH00136 Waveform 5. Data set-up and hold times for the An input to the clock CP input tPHL VOH Yn OUTPUT VOL VM tPLH VI nOE INPUT GND VM NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7V SH00134 Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Yn) propagation delays. VCC OUTPUT LOW-to-OFF OFF-to-LOW VX VM 1/fMAX VI CP INPUT GND VM tW VM VOL tPHZ VOH tPZH tPHL VOH Yn OUTPUT VOL VM tPLH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V SH00135 NOTE: VM = 0.5VCC at VCC = 2.3 to 2.7 V Waveform 3. The clock (CP) to Yn propagation delays, the clock pulse width and the maximum clock frequency. 2001 Apr 20 7 ÉÉÉ É ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ É ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ VI VM th th tSU tSU VI VM AC WAVEFORMS FOR VCC = 3.0 V TO 3.6 V RANGE SH00133 VI VM tsu th tsu th VI Waveform 6. 3-State enable and disable times ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ VM tPLZ tPZL VY VM outputs disabled outputs enabled SH00137 Philips Semiconductors Product specification 18-bit registered driver with 15 Ω termination resistors (3-State) 74AVCM162835 TEST CIRCUIT VCC S1 2 * VCC Open GND VI PULSE GENERATOR RT D.U.T. VO RL CL RL Test Circuit for switching times DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. SWITCH POSITION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 < VCC GND VCC < 2.3 V 2.3–2.7 V 3.0 –3.6 V VI VCC VCC VCC RL 1000 Ω 500 Ω 500 Ω SV01883 Waveform 7. Load circuitry for switching times 2001 Apr 20 8 Philips Semiconductors Product specification 18-bit registered driver with 15 Ω termination resistors (3-State) 74AVCM162835 TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 2001 Apr 20 9 Philips Semiconductors Product specification 18-bit registered driver with 15 Ω termination resistors (3-State) 74AVCM162835 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 04-01 9397-750-08283 Philips Semiconductors 2001 Apr 20 10