74F169

INTEGRATED CIRCUITS 74F168*, 74F169 4-bit up/down binary synchronous counter * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 FEATURES • Synchronous counting and loading • Up/Down counting • Modulo 16 binary counter • Two Count Enable inputs for n-bit cascading • Positive edge-triggered clock • Built-in carry look-ahead capability • Presettable for programmable operation DESCRIPTION The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down counter featuring an internal carry look-ahead for applications in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the Count Enable inputs and internal gating. This mode of operation eliminates the output spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the flip-flops on the Low-to-High transition of the clock. The counter is fully programmable; that is, the outputs may be preset to either level. Presetting is synchronous with the clock and takes place regardless of the levels of the Count Enable inputs. A Low level on the Parallel Enable (PE) input disables the counter and causes the data at the Dn input to be loaded into the counter on the next Low-to-High transition of the clock. The direction of counting is controlled by the Up/Down (U/D) input; a High will cause the count to increase, a Low will cause the count to decrease. The carry look-ahead circuitry provides for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two Count Enable inputs (CET, CEP) and a Terminal Count (TC) output. Both Count Enable inputs must be Low to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a Low output pulse with a duration approximately equal to the High level portion of the Q0 output. The Low level TC pulse is used to enable successive cascaded stages. PIN CONFIGURATION U/D CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE SF00766 TYPE 74F169 TYPICAL fMAX 115MHz TYPICAL SUPPLY CURRENT (TOTAL) 35mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F169N N74F169D PKG DWG # SOT38-4 SOT109-1 16-pin plastic DIP 16-pin plastic SO INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0 - D3 CEP CET CP PE U/D Q 0 - Q3 Parallel data inputs Count Enable parallel input (active Low) Count Enable Trickle input (active Low) Clock input (active rising edge) Parallel Enable input (active Low) Up/Down count control input Flip-flop outputs DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/1.2mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 1.0mA/20mA 1.0mA/20mA TC Terminal count output (active Low) 50/33 NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state. 1996 Jan 05 2 853–0350 16190 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 LOGIC SYMBOL 3 4 5 6 LOGIC SYMBOL (IEEE/IEC) CTR DIV 16 9 M1 [LOAD] M2 [COUNT] 9 1 2 7 10 PE U/D D0 D1 D2 D3 1 M3 [UP] M4 [DOWN] 15 10 CP CEP CET Q0 Q1 Q2 Q3 3 14 13 12 11 4 5 VCC = Pin 16 GND = Pin 8 6 TC 15 7 2 G5 G6 2, 3, 5, 6+/C7 2, 4, 5, 6– 3, 5 CT=15 4, 5 CT=0 1, 7D [1] [2] [4] [8] 14 13 12 11 SF00786 SF00787 FUNCTIONAL DESCRIPTION The 74F169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is Low, the data on the D0 - D3 inputs enter the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be Low and PE must be High; the U/D input determines the direction of counting. The Terminal Count (TC) output is normally High and goes Low, provided that CET is Low, when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). 1) Count Enable = CEP⋅CET⋅PE 2) Up: TC = Q0⋅Q3⋅(U/D)⋅CET 3) Down: TC = Q0⋅Q1⋅Q2⋅Q3⋅(U/D)⋅CET MODE SELECT — FUNCTION TABLE INPUTS CP ↑ ↑ ↑ ↑ ↑ ↑ H= h= L= l= q= X= ↑= (1) = U/D X X h l X X CEP X X l l h X CET X X l l X X PE l X h h h h Dn l X X X X X OUTPUTS Qn L H Count Up Count Down qn qn TC (1) (1) (1) (1) (1) H OPERATING MODE MODE Parallel load (Dn→Qn) Count Up (increment) Count Down (decrement) Hold (do nothing) High voltage level steady state High voltage level one setup time prior to the Low-to-High clock transition Low voltage level steady state Low voltage level one setup time prior to the Low-to-High clock transition Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition Don’t care Low-to-High clock transition The TC is Low when CET is Low and the counter is at Terminal Count. Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL). 1996 Jan 05 3 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 MODE SELECT TABLE INPUTS PE CEP CET U/D X H L X X OPERATING MODE MODE Load (Dn→Qn) Count Up (Increment) Count Down (Decrement) No Change (Hold) No Change (Hold) STATE DIAGRAM 0 1 2 3 4 L X X H L L H L L H H X H X H H = High Voltage L = Low Voltage Level X = Don’t care 15 5 14 6 13 7 12 11 10 9 8 COUNT DOWN COUNT UP SF00788 LOGIC DIAGRAM 3 D0 D Q 14 Q0 CP Q D1 4 D Q 13 Q1 CP Q D2 5 D Q 12 Q2 CP Q D3 PE 6 D Q 11 Q3 9 CP Q 7 CEP 10 CET 2 1 15 TC CP U/D VCC = Pin 16 GND = Pin 8 SF00789 1996 Jan 05 4 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 APPLICATION CP U/D PE D0 PE U/D CP CEP CET Q0 Q1 Q2 Q3 TC D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 PE U/D CP CEP CET PE U/D CP TC CEP CET PE U/D CP TC CEP CET TC Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 LEAST SIGNIFICANT 4-BIT COUNTER MOST SIGNIFICANT 4-BIT COUNTER SF00790 Figure 1. Synchronous Multistage Counting Scheme ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb TSTG Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING –0.5 to +7.0 –0.5 to +7.0 –30 to +5 –0.5 to +VCC 40 0 to +70 –65 to +150 UNIT V V mA V mA °C °C RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER Min 4.5 2.0 0.8 –18 –1 20 70 LIMITS Nom 5.0 Max 5.5 V V V mA mA mA °C UNIT 1996 Jan 05 5 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TAG TEST CONDITIONSNO TAG MIN VCC = MIN, VIL = MAX, , , VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, , , VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V CET IIL IOS ICC Low-level input current Low level input current Others Short-circuit output currentNO TAG Supply current (total)4 VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX –60 TYP NO TAG UNIT MAX V VO OH High-level output voltage level output voltage ±10%VCC ±5%VCC ±10%VCC ±5%VCC 2.5 2.7 3.4 0.35 0.35 –0.73 0.50 0.50 –1.2 100 20 –1.2 –0.6 –150 35 52 V V V V µA µA mA mA mA mA VO OL VIK II IIH Low-level output voltage Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. ICC is measured after applying a momentary 4.5V, then ground to the clock input with all other inputs grounded and all outputs open. 1996 Jan 05 6 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C VCC = +5V CL = 50pF, RL = 500Ω MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CP to Qn (PE, High or Low) Propagation delay CP to TC Propagation delay CET to TC Propagation delay U/D to TC Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 3 100 3.0 4.0 5.5 4.0 2.5 2.5 3.5 4.0 TYP 115 6.5 9.0 12.0 8.5 4.5 6.0 8.5 8.0 8.5 11.5 15.5 11.0 6.0 8.0 15.0 10.5 MAX Tamb = 0°C to +70°C VCC = +5V ± 10% CL = 50pF, RL = 500Ω MIN 90 3.0 4.0 5.5 4.0 2.5 2.5 3.5 4.0 9.5 13.0 17.0 12.5 7.0 9.0 15.5 12.0 MAX MHz ns ns ns ns ns ns ns ns UNIT AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25°C VCC = +5.0V CL = 50pF, RL = 500Ω MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP Set-up time, High or Low CEP or CET to CP Hold time, High or Low CEP or CET to CP Set-up time, High or Low PE to CP Hold time, High or Low PE to CP Set-up time, High or Low U/D to CP Hold time, High or Low U/D to CP CPU or CPD pulse width, High or Low Waveform 4 Waveform 4 Waveform 5 Waveform 5 Waveform 4 Waveform 4 Waveform 6 Waveform 6 Waveform 1 4.0 4.0 3.0 3.0 5.0 5.0 0 0 8.0 8.0 0 0 11.0 7.0 0 0 5.0 5.0 TYP LIMITS Tamb= 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN 4.5 4.5 3.5 3.5 5.5 5.5 0 0 9.0 9.0 0 0 12.5 8.0 0 0 5.5 5.5 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT 1996 Jan 05 7 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 AC WAVEFORMS For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CET CP VM tW(H) tPLH VM Qn tPHL VM tPLH VM tW(L) tPHL VM TC VM tPHL VM tPLH VM VM VM SF00792 TC VM Waveform 2. Propagation Delays CET Input to Terminal Count Output SF00791A Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency Dn VM VM ts th U/D VM tPHL VM tPLH VM VM PE VM VM ts(L) th = 0 VM ts(H) VM th = 0 TC CPn VM VM SF00793 SF00794 Waveform 3. Propagation Delay U/D Input to Terminal Count Output Waveform 4. Parallel Data and Parallel Enable Setup and Hold Times CET VM CEP ts(L) th(L) ts(H) th(H) VM VM VM U/D VM ts(L) VM th(L) VM ts(H) VM th(H) CPn VM VM CPn VM VM Qn NO CHANGE VM COUNT VM NO CHANGE Qn COUNT DOWN COUNT UP SF00795 SF00796 Waveform 5. Count Enable Setup and Hold Times Waveform 6. Up/Down Control Setup and Hold Times 1996 Jan 05 8 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F169 TIMING DIAGRAM (Typical Load, Count, and Inhibit Sequences) PE D0 D1 D2 D3 CP U/D CEP and CET Q0 Q1 Q2 Q3 TC SEQUENCE 7 LOAD 8 9 0 1 2 2 INHIBIT 2 1 0 9 8 7 NOTES: The operation of the 74F169 is similar to the Illustration above. 1. Load (preset) to BCD seven 2. Count up to eight, nine (maximum), zero, one, and two 3. Inhibit 4. Count down to one, zero (minimum), nine, eight, and seven } TEST CIRCUIT AND WAVEFORM VCC COUNT UP COUNT DOWN SF00797 90% NEGATIVE PULSE VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 90% AMP (V) VIN PULSE GENERATOR RT D.U.T. VOUT 0V tTLH (tr ) 90% POSITIVE PULSE VM 10% tw tTHL (tf ) AMP (V) 90% VM 10% 0V Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns SF00006 1996 Jan 05 9 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F168*, 74F169 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. 1996 Jan 05 10 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F168*, 74F169 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. 1996 Jan 05 11 Philips Semiconductors Product specification 4-bit up/down binary synchronous counter 74F168*, 74F169 DEFINITIONS Data Sheet Identification Objective Specification Product Status Formative or in Design Definition This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Preliminary Specification Preproduction Product Product Specification Full Production Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. © Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. Date of release: July 1994 9397-750-05087