74F199

Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 FEATURES • Buffered clock and control inputs • Shift right and parallel load capability • Fully synchronous data transfers • J-K(D) inputs to first stage • Clock enable for hold (do nothing) mode • Asynchronous Master Reset DESCRIPTION The 74F199 is an 8-bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table. The device is useful in a variety of shifting, counting and storage applications. It performs serial, parallel, serial-to-parallel, or parallel–to-serial data transfers at very high speeds. The 74F199 operates in two primary modes: shift right (Q0→Q1) and parallel load, which are controlled by the state of the Parallel Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is High, and is shifted one bit in the direction Q0→Q1→Q2 following each Low-to-High clock transition. The J and K inputs provide the flexibility of the J-K type input for special applications, and by tying the two together the simple D-type input is made for general applications. The device appears as eight common clocked D flip-flops when the PE input is Low. After the Low-to-High clock transition, data on the parallel inputs (D0–D7) is transferred to the respective Q0–Q7 outputs. All parallel and serial data transfers are synchronous, occurring after each Low-to-High clock transition. The 74F199 utilizes edge-triggered, therefore there is no restriction on the activity of the J, K, Dn, and PE inputs for logic operation, other than the setup and hold time requirements. A Low on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously forcing all bit positions to a Low state. PIN CONFIGURATION K1 J D0 Q0 D1 Q1 D2 Q2 D3 2 3 4 5 6 7 8 9 24 VCC 23 PE 22 D7 21 Q7 20 D6 19 Q6 18 D5 17 Q5 16 D4 15 Q4 14 MR 13 CP Q3 10 CE 11 GND 12 SF00152 TYPE 74F199 TYPICAL fMAX 95MHz TYPICAL SUPPLY CURRENT (TOTAL) 70mA ORDERING INFORMATION DESCRIPTION 24-pin plastic slim DIP (300mil) 24-pin plastic SOL COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F199N N74F199D INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0–D7 J, K PE CE DP MR Q0–Q7 DESCRIPTION Parallel data inputs J and K inputs Parallel Enable input Clock Enable input Clock Pulse inputs (Active rising edge) Master Reset input (Active Low) Data outputs 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. June 15, 1988 1 853–0082 93568 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 LOGIC SYMBOL 3 5 7 9 16 18 20 22 IEEE/IEC SYMBOL SRG8 11 13 23 D0 D1 D2 D3 D4 D5 D6 D7 1 1 C3 R & C2/→ 23 2 1 13 11 14 PE J K CP CE MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 14 2 1 3 5 7 9 16 18 4 6 8 10 15 17 19 21 20 22 2J 2K 2, 3D 2, 3D 6 8 10 15 17 19 21 4 VCC = Pin 24 GND = Pin 12 SF00153 SF00154 FUNCTION TABLE INPUTS MR L H H H H H H H h L l X ↑ dn(qn) = = = = = = = CP X ↑ ↑ ↑ ↑ ↑ ↑ CE X l l l l l h PE X h h h h l X J X h l h l X X K X h l l h X X Dn X X X X X dn X Q0 L H L q0 q0 d0 q0 Q1 L q0 q0 q0 q0 d1 q1 OUTPUTS … … … … … … … … OPERATING MODES Q6 L q5 q5 q5 q5 d6 q6 Q7 L q6 q6 q6 q6 d7 q7 Reset (clear Shift, set First stage Shift, reset First stage Shift, toggle First stage Shift, retain First stage Parallel load Hold (do nothing) High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior t the Low-to-High clock transition Don’t care Low-to-High clock transition Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition June 15, 1988 2 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 LOGIC DIAGRAM CE 11 CP 13 PE 23 J K 2 1 R CP S Q Q 4 Q0 MR D0 14 3 RD D1 5 R CP RD S Q 6 Q1 D2 7 R CP RD S Q 8 Q2 D3 9 R CP RD S Q 10 Q3 D4 16 R CP RD S Q 15 Q4 D5 18 R CP RD S Q 17 Q5 D6 20 R CP RD S Q 19 Q6 D7 22 R CP RD S Q 21 Q7 SF00155 June 15, 1988 3 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 TYPICAL TIMING DIAGRAM CP CE MR SERIAL INPUTS J K PE D0 D1 D2 PARALLEL DATA INPUTS D3 D4 D5 D6 D7 Q0 Q1 Q2 OUTPUTS Q3 Q4 Q5 Q6 Q7 INHIBIT SERIAL SHIFT CLEAR LOAD SERIAL SHIFT H H L H L H L H H L H L H L H H Typical Load, Serial-Shift, Inhibit and Clear Sequences SF00156 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING –0.5 to +7.0 –0.5 to +7.0 –30 to +5 –0.5 to VCC 40 0 to +70 –65 to +150 UNIT V V mA V mA °C °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb June 15, 1988 Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 4 0 PARAMETER MIN 4.5 2.0 0.8 –18 –1 20 +70 NOM 5.0 MAX 5.5 V V V mA mA mA °C UNIT Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 MIN VOH High-level output voltage VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 Supply current (total) ICCH ICCL VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX –60 65 75 ±10%VCC ±5%VCC ±10%VCC ±5%VCC 2.5 V 2.7 3.4 0.35 0.35 –0.73 0.50 V 0.50 –1.2 100 20 –0.6 –150 90 105 mA V µA µA mA mA LIMITS TYP2 UNIT MAX VOL VIK II IIH IIL IOS ICC NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. June 15, 1988 5 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500Ω MIN fMAX tPLH tPHL tPHL Maximum clock frequency Propagation delay CP to Qn Propagation delay MR to Qn Waveform 1 Waveform 1 Waveform 2 80 5.5 6.5 5.5 TYP 95 8.0 9.5 8.0 11.0 12.5 10.5 MAX VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN 70 4.5 3.5 5.0 12.0 13.5 12.0 MAX MHz ns ns UNIT AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500Ω MIN tS(H) tS(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) trec Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP Setup time, High or Low J, K to CP Hold time, High or Low J, K to CP Setup time, High or Low CE to CP Hold time, High or Low CE to CP Setup time, High or Low PE to CP Hold time, High or Low PE to CP CP pulse width, High MR pulse width, Low Recovery time MR to CP Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 1 Waveform 2 Waveform 2 0.0 1.5 2.0 4.5 0.0 2.5 0.0 3.5 0.0 2.5 0.0 4.5 8.0 8.0 0.0 0.0 4.5 4.0 5.5 TYP MAX VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN 0.0 2.5 2.5 5.5 0.0 3.0 0.0 4.0 0.0 3.0 0.0 5.5 9.0 9.0 0.0 0.0 5.5 4.5 6.5 MAX ns ns ns ns ns ns ns ns ns ns ns UNIT June 15, 1988 6 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CP MR VM tw(L) VM tREC VM VM tw(H) tPHL VM CP tPLH tPHL VM Qn Qn VM SF00157 SF00158 Waveform 1. Propagation Delay, Clock Input to Output, Clock Widths, and Maximum Clock Frequency Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time CE VM VM VM ts(H) th = 0 ts(L) PE VM ts(L) Dn th VM th = 0 ts(L) th = 0 VM STABLE VM ts J, K th VM STABLE VM ts CP VM th VM VM SF00159 Waveform 3. Setup Time and Hold Time June 15, 1988 7 Philips Semiconductors FAST Products Product specification 8-bit parallel-access shift register 74F199 TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V) tTLH (tr ) 90% POSITIVE PULSE VM 10% tw tTHL (tf ) AMP (V) 90% VM 10% 0V Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns SF00006 June 15, 1988 8