74F410

Philips Semiconductors FAST Products Product specification Register stack – 16×4 RAM 3-State output register 74F410 FEATURES • Edge triggered output register • ypical access time of 19.5ns • Optimize for register stack operation • 3–state outputs • 18–pin package DESCRIPTION The 74F410 is a register oriented high speed 64–bit read/write memory organized as 16–words by 4–bits. An edge–triggered 4–bit output register allows new input data to be written while previous data is held. 3–state outputs are provided for maximum versatility. The 74F410 is fully compatible with all TTL families. TYPICAL SUPPLY CURRENT ( TOTAL) 45mA while WE, CS, and CP are low, the contents of the selected memory location follow these changes provided setup and hold time criteria are met. Read operation – When CS is low, WE is high, and CP goes from low–to–high, the contents of the memory location selected by the address inputs (A0–A3) are edge– triggered into the output register. When WE is low, CS is low, CP goes from low–to–high, the data at the data inputs is edge–triggered into the output register. The OE input controls the output buffers. When OE is high the four outputs (Q0–Q3) are in a high impedance or off state; when OE is low, the outputs are determined by the state of the output register. TYPE 74F410 TYPICAL ACCESS TIME 19.5ns FUNCTIONAL DESCRIPTION Write operation – When the three control inputs, write enable (WE), chip select (CS), and clock (CP), are low the information on the data inputs (D0–D3) is written into the memory location selected by the address inputs (A0–A3). If the input data changes ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 18–pin plastic DIP (300mil) N74F410N INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS D0 – D3 A0 – A3 CP CS OE WE Data inputs Address inputs Clock pulse input (active rising edge) Chip select input (active low) Output enable input (active low) Write enable input (active low) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/2.0 1.0/2.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/1.2mA 20µA/1.2mA 20µA/0.6mA 20µA/0.6mA 3mA/24mA Q0 – Q3 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. PIN CONFIGURATION LOGIC SYMBOL 17 15 13 11 IEC/IEEE SYMBOL 3 4 5 6 2 1 7 1C & G2 8 17 15 EN3 A1,2D A3 16 14 12 10 0 A 1 & G1 0 15 CS 1 WE 2 A0 3 A1 4 A2 5 A3 6 CP 7 OE 8 GND 9 18 V CC 17 D0 16 Q0 15 D1 14 Q1 13 D2 12 Q2 11 D3 10 Q3 VCC = Pin 18 GND = Pin 9 16 14 12 10 3 4 5 6 1 2 7 8 A0 A1 A2 A3 CS WE CP OE Q0 Q1 Q2 Q3 D0 D1 D2 D3 13 11 January 8, 1990 1 853-1310 98498 Philips Semiconductors FAST Products Product specification Register stack – 16×4 RAM 3-State output register 74F410 LOGIC DIAGRAM 8 OE A0 A1 A2 A3 3 4 5 6 Address decoder 16 RAM D0 D1 D2 D3 17 15 13 11 4 16 Q0 14 Data inputs 16 Q1 Register 12 Q2 10 Q3 15 WE 13 CS 11 CP VCC = pin 18 GND = pin 9 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Operating free air temperature range Storage temperature range PARAMETER RATING –0.5 to +7.0 –0.5 to +7.0 –30 to +5 –0.5 to VCC 48 0 to +70 –65 to +150 UNIT V V mA V mA °C °C January 8, 1990 2 Philips Semiconductors FAST Products Product specification Register stack – 16×4 RAM 3-State output register 74F410 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER MIN VCC VIH VIL IIk IOH IOL Tamb Supply voltage High–level input voltage Low–level input voltage Input clamp current High–level output current Low–level output current Operating free air temperature range 0 4.5 2.0 0.8 –18 –3 24 +70 LIMITS NOM 5.0 MAX 5.5 T UNIT A = –V 4 0V t V o + mA 8 5 mA ° mA C °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 MIN VOH High-level output voltage VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX VOL Low-level output voltage VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX VIK II IIH IIL Input clamp voltage Input current at maximum input voltage High–level input current Low–level input current others CP, CS IOZH IOZL IOS Offset–output current, high–level voltage applied Offset–output current, low–level voltage applied Short-circuit output current3 VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX -60 VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V LIMITS TYP2 MAX V V 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 -1.2 50 –50 -150 V V V UNIT ±10%VCC ±5%VCC ±10%VCC ±5%VCC 2.4 2.7 µA µA mA mA µA µA mA ICC Supply current (total) VCC = MAX 45 70 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. January 8, 1990 3 Philips Semiconductors FAST Products Product specification Register stack – 16×4 RAM 3-State output register 74F410 AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION CL = 50pF, RL = 500Ω MIN tPLH tPHL tPZH tPZL tPHZ tPHL Propagation dealy CP to Qn Output enable time OE to Qn Output disable time OE to Qn Waveform 1 Waveform 3, 4 Waveform 3, 4 4.0 4.5 3.0 4.5 2.0 2.0 TYP 6.5 6.5 4.5 6.0 3.5 3.5 MAX 8.5 9.0 7.5 9.0 6.0 6.5 VCC = +5.0V Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN 3.5 4.0 2.5 3.5 1.5 2.0 MAX 9.5 10.0 8.5 9.5 6.5 7.0 ns ns ns VCC = +5.0V ± 10% UNIT AC SETUP REQUIREMENTS FOR READ MODE LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION CL = 50pF, RL = 500Ω MIN tsu(L) th(L) tsu(H) tsu(L) th(H) th(L) tsu(H) th(H) Setup time, low, CS to CP1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 4.0 3.5 13.0 13.0 0 0 13.0 0 5.0 Hold time, low, CS to CP1 Setup time, high or low An to CP1 Hold time, high or low An to CP1 Setup time, high, WE to CP1 Hold time, high, WE to CP1 TYP MAX VCC = +5.0V Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN 4.5 4.5 15.0 15.0 0 0 15.0 0 6.0 MAX ns ns ns ns ns ns ns VCC = +5.0V ± 10% UNIT tw(L) CP pulse width, low NOTE: 1. Low–to–high clock transition. AC SETUP REQUIREMENTS FOR WRITE MODE LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION CL = 50pF, RL = 500Ω MIN tsu(H) tsu(L) th(H) th(L) tsu(H) tsu(L) th(H) th(L) tw(L) tw(L) tw(L) Setup time, high or low An to WE, CS, CP Hold time, high or low An to WE, CS, CP Setup time, high or low Dn to WE, CS, CP Hold time, high or low Dn to WE, CS, CP WE pulse width, low CS pulse width, low CP pulse width, low Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 Waveform 2 0 0 0 0 6.0 6.0 0 0 7.0 6.0 7.0 TYP MAX VCC = +5.0V Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN 0 0 0 0 8.0 8.0 0 0 8.0 7.0 8.0 MAX ns ns ns ns ns ns ns VCC = +5.0V ± 10% UNIT January 8, 1990 4 Philips Semiconductors FAST Products Product specification Register stack – 16×4 RAM 3-State output register 74F410 AC WAVEFORMS CS VM tsu(L) th(L) VM VM th(L) tsu(L) VM OE VM tPZH VM tPHZ VM 0V VOH -0.3V WE VM th(H) tsu(H) VM VM tsu(H) VM th(H) VM Qn An VM VM th(L) VM th(H) Waveform 3. 3-State output enable time to high level and output disable time from high level OE tsu(L) CP VM tsu(H) VM VM tPZL VM tPLZ VM tw(H) tPHL VM tPLH Qn Qn VM VM VOL +0.3V Waveform 1. Read cycle timing An, Dn Waveform 4. 3-State output enable time to low level and output disable time from low level VM VM VM th(L) tw(L) VM tsu(L) CS WE CP tsu(H) th(H) VM VM VM VM Waveform 2. Write cycle timing NOTES: 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance. TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) tW VM 10% tTLH (tr ) 0V 90% AMP (V) CL RL POSITIVE PULSE 10% tTLH (tr ) 90% tTHL (tf ) AMP (V) 90% VM tW 10% 0V Test circuit for 3–state outputs SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value RT = Termination resistance should be equal to ZOUT of pulse generators. VM Input pulse definition INPUT PULSE REQUIREMENTS family amplitude 74F 3.0V VM 1.5V rep. rate 1MHz tW tTLH tTHL 2.5ns 500ns 2.5ns January 8, 1990 5