74HC192D

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT192 Presettable synchronous BCD decade up/down counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter FEATURES • Synchronous reversible counting • Asynchronous parallel load • Asynchronous reset • Expandable without external logic • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT192 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT192 are synchronous BCD up/down counters. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time, or erroneous operation will result. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The “192” contains four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions. Each flip-flop contains JK feedback from slave to master, such that a LOW-to-HIGH transition on the CPD input will decrease the count by one, while a similar transition on the CPU input will advance the count by one. 74HC/HCT192 One clock should be held HIGH while counting with the other, otherwise the circuit will either count by two’s or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is LOW. Applications requiring reversible operation must make the reversing decision while the activating clock is HIGH to avoid erroneous counts. The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 9, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. December 1990 2 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT192 TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC −1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PARAMETER propagation delay CPD, CPU to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 20 40 3.5 24 HCT 20 45 3.5 28 ns MHz pF pF UNIT December 1990 3 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter PIN DESCRIPTION PIN NO. 3, 2, 6, 7 4 5 8 11 12 13 14 15, 1, 10, 9 16 Note 1. LOW-to-HIGH, edge triggered SYMBOL Q0 to Q3 CPD CPU GND PL TCU TCD MR D0 to D3 VCC NAME AND FUNCTION flip-flop outputs count down clock input(1) count up clock input(1) ground (0 V) 74HC/HCT192 asynchronous parallel load input (active LOW) terminal count up (carry) output (active LOW) terminal count down (borrow) output (active LOW) asynchronous master reset input (active HIGH) data inputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 4 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter FUNCTION TABLE INPUTS OPERATING MODE MR reset (clear) H H L parallel load L L L count up count down Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH clock transition 2. TCU = CPU at terminal count up (HLLH) 3. TCD = CPD at terminal count down (LLLL) L L PL X X L L L L H H CPU CPD X X X X L H ↑ H L H L H X X H ↑ D0 X X L L H H X X D1 X X L L X X X X D2 X X L L X X X X D3 X X L L H H X X Q0 L L L L Q1 L L L L 74HC/HCT192 OUTPUTS Q2 L L L L Q n = Dn Q n = Dn count up count down Q3 L L L L TCU H H H H L H H(2) H TCD L H L H H H H H(3) Fig.4 Functional diagram. December 1990 5 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT192 (1) Clear overrides load, data and count inputs. (2) When counting up the count down clock input (CPD) must be HIGH, when counting down the count up clock input (CPU) must be HIGH. Sequence Clear (reset outputs to zero); load (preset) to BCD seven; count up to eight, nine, terminal count up, zero, one and two; count down to one, zero, terminal count down, nine, eight, and seven. Fig.5 Typical clear, load and count sequence. Fig.6 Logic diagram. December 1990 6 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC SYMBOL 74HC/HCT192 TEST CONDITIONS UNIT V CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS PARAMETER +25 min. typ. −40 to +85 −40 to +125 max. 325 65 55 190 38 32 190 38 32 325 65 55 300 60 51 415 83 71 360 72 61 475 95 81 430 86 73 435 87 74 110 22 19 max. min. max. min. 215 43 37 125 25 21 125 25 21 215 43 37 200 40 34 275 55 47 240 48 41 315 63 54 285 57 48 290 58 49 75 15 13 270 54 46 155 31 26 155 31 26 270 54 46 250 50 43 345 69 59 300 60 51 395 79 67 355 71 60 365 73 62 95 19 16 tPHL/ tPLH propagation delay CPU, CPD to Qn propagation delay CPU to TCU propagation delay CPD to TCD propagation delay PL to Qn propagation delay MR to Qn propagation delay Dn to Qn propagation delay Dn to Qn propagation delay PL to TCU, PL to TCD propagation delay MR to TCU, MR to TCD propagation delay Dn to TCU, Dn to TCD output transition time 66 24 19 33 12 10 39 14 11 69 25 20 63 23 18 91 33 26 80 29 23 102 37 30 96 35 28 83 30 24 19 7 6 Fig.7 tPHL/ tPLH ns Fig.8 tPHL/ tPLH ns Fig.8 tPHL/ tPLH ns Fig.9 tPHL ns Fig.10 tPHL ns Fig.9 tPLH ns Fig.9 tPHL/ tPLH ns Fig.12 tPHL/ tPLH ns Fig.12 tPHL/ tPLH ns Fig.12 tTHL/ tTLH ns Fig.10 December 1990 7 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter Tamb (°C) 74HC SYMBOL 74HC/HCT192 TEST CONDITIONS UNIT V CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS PARAMETER +25 min. typ. −40 to +85 −40 to +125 max. max. min. max. min. 150 30 26 175 35 30 100 20 17 100 20 17 65 13 11 65 13 11 100 20 17 0 0 0 100 20 17 3.2 16 19 180 36 31 210 42 36 120 24 20 120 24 20 75 15 13 75 15 13 120 24 20 0 0 0 120 24 20 2.6 13 15 tW up clock pulse width HIGH or LOW down clock pulse width HIGH or LOW master reset pulse width HIGH parallel load pulse width LOW removal time PL to CPU, CPD removal time MR to CPU, CPD set-up time Dn to PL hold time Dn to PL hold time CPU to CPD, CPD to CPU 120 24 20 140 28 24 80 16 14 80 16 14 50 10 9 50 10 9 80 16 14 0 0 0 80 16 14 39 14 11 50 18 14 22 8 6 22 8 6 3 1 1 0 0 0 22 8 6 −14 −5 −4 19 7 6 12 36 43 Fig.7 tW ns Fig.7 tW ns Fig.10 tW ns Fig.9 trem ns Fig.9 trem ns Fig.10 tsu ns Fig.11 note: CPU = CPD = HIGH Fig.11 th ns th ns Fig.13 fmax maximum up, down clock 4.0 pulse frequency 20 24 MHz Fig.7 December 1990 8 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types 74HC/HCT192 The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT Dn CPU, CPD PL MR UNIT LOAD COEFFICIENT 0.35 1.40 0.65 1.05 December 1990 9 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HCT SYMBOL PARAMETER +25 −40 to +85 −40 to +125 max. 65 45 45 69 60 93 96 96 87 22 38 24 30 15 15 24 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74HC/HCT192 TEST CONDITIONS WAVEFORMS UNIT V CC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.8 Fig.8 Fig.9 Fig.10 Fig.9 Fig.12 Fig.12 Fig.12 Fig.10 Fig.7 Fig.10 Fig.9 Fig.9 Fig.10 Fig.11 note: CPU = CPD = HIGH Fig.11 Fig.13 Fig.7 min. typ. max. min. max. min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH tW tW tW trem trem tsu propagation delay CPU, CPD to Qn propagation delay CPU to TCU propagation delay CPD to TCD propagation delay PL to Qn propagation delay MR to Qn propagation delay Dn to Qn propagation delay PL to TCU, PL to TCD propagation delay MR to TCU, MR to TCD propagation delay Dn to TCU, Dn to TCD output transition time up, down clock pulse width 25 HIGH or LOW master reset pulse width HIGH parallel load pulse width LOW removal time PL to CPU, CPD removal time MR to CPU, CPD set-up time Dn to PL hold time Dn to PL hold time CPU to CPD, CPD to CPU maximum up, down clock pulse frequency 16 20 10 10 16 23 16 17 28 24 36 36 36 33 7 14 6 10 1 2 8 43 30 30 46 40 62 64 64 58 15 31 20 25 13 13 20 54 38 38 58 50 78 80 80 73 19 th th fmax 0 20 20 −6 9 41 0 25 16 0 30 13 ns ns MHz 4.5 4.5 4.5 December 1990 10 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter AC WAVEFORMS 74HC/HCT192 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock input (CPU, CPD). December 1990 11 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT192 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the data input (Dn) to parallel load input (PL) set-up and hold times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.12 Waveforms showing the data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs (TCU, TCD) propagation delays. December 1990 12 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT192 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.13 Waveforms showing the CPU to CPD or CPD to CPU hold times. APPLICATION INFORMATION Fig.14 Cascaded up/down counter with parallel load. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 13