74HC2G00DC

INTEGRATED CIRCUITS DATA SHEET 74HC2G00; 74HCT2G00 Dual 2-input NAND gate Product specification Supersedes data of 2002 Jul 10 2003 Feb 12 Philips Semiconductors Product specification Dual 2-input NAND gate FEATURES • Wide supply voltage range from 2.0 to 6.0 V • Symmetrical output impedance • High noise immunity • Low power dissipation • Balanced propagation delays • Very small 8 pins package • Output capability is standard • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns. DESCRIPTION 74HC2G00; 74HCT2G00 The 74HC2G/HCT2G00 is a high-speed Si-gate CMOS device. The 74HC2G/HCT2G00 provides the 2-input NAND function. TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; N = total load switching outputs; VCC = supply voltage in Volts; ∑ (CL × VCC2 × fo) = sum of outputs. 2. For 74HC2G00 the condition is VI = GND to VCC. For 74HCT2G00 the condition is VI = GND to VCC − 1.5 V. PARAMETER propagation delay nA, nB to nY input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS HC2G00 CL = 50 pF; VCC = 4.5 V 9 1.5 10 HCT2G00 12 1.5 10 ns pF pF UNIT 2003 Feb 12 2 Philips Semiconductors Product specification Dual 2-input NAND gate FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION PACKAGE TYPE NUMBER 74HC2G00DP 74HCT2G00DP 74HC2G00DC 74HCT2G00DC PINNING PIN 1 2 3 4 5 6 7 8 1A 1B 2Y GND 2A 2B 1Y VCC SYMBOL data input 1A data input 1B data output 2Y ground (0 V) data input 2A data input 2B data output 1Y supply voltage TEMPERATURE RANGE −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C PINS 8 8 8 8 nB L H L H 74HC2G00; 74HCT2G00 OUTPUT nY H H H L PACKAGE MATERIAL TSSOP8 TSSOP8 VSSOP8 VSSOP8 plastic plastic plastic plastic CODE SOT505-2 SOT505-2 SOT765-1 SOT765-1 MARKING P00 U00 P00 U00 DESCRIPTION 2003 Feb 12 3 Philips Semiconductors Product specification Dual 2-input NAND gate 74HC2G00; 74HCT2G00 handbook, halfpage 1A 1 1B 2 8 VCC 7 1Y 2B 2A handbook, halfpage 1 2 5 6 1A 1B 2A 2B 1Y 7 00 2Y GND 3 4 MNA711 6 5 2Y 3 MNA712 Fig.1 Pin configuration. Fig.2 Logic symbol. handbook, halfpage 1 2 & 7 handbook, halfpage B Y 5 6 & 3 A MNA099 MNA713 Fig.3 IEC logic symbol. Fig.4 Logic diagram (one driver). 2003 Feb 12 4 Philips Semiconductors Product specification Dual 2-input NAND gate RECOMMENDED OPERATING CONDITIONS 74HC2G00 SYMBOL VCC VI VO Tamb PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times CONDITIONS MIN. 2.0 0 0 see DC and AC −40 characteristics per device VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V − − − TYP. 5.0 − − +25 74HC2G00; 74HCT2G00 74HCT2G00 UNIT MIN. 4.5 0 0 −40 TYP. 5.0 − − +25 MAX. 5.5 VCC VCC +125 V V V °C MAX. 6.0 VCC VCC +125 tr, tf − 6.0 − 1000 500 400 − − − − 6.0 − − 500 − ns ns ns LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 110 °C the value of PD derates linearly with 8 mW/K. PARAMETER supply voltage input diode current output diode current output source or sink current VCC or GND current storage temperature power dissipation per package for temperature range from −40 to +125 °C; note 2 VI < −0.5 V or VI > VCC + 0.5 V; note 1 VO < −0.5 V or VO > VCC + 0.5 V; note 1 −0.5 V < VO < VCC + 0.5 V; note 1 note 1 CONDITIONS MIN. −0.5 − − − − −65 − MAX. +7.0 ±20 ±20 25 50 +150 300 UNIT V mA mA mA mA °C mW 2003 Feb 12 5 Philips Semiconductors Product specification Dual 2-input NAND gate DC CHARACTERISTICS 74HC2G00; 74HCT2G00 Type 74HC2G00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V); note 1. TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −20 µA IO = −20 µA IO = −4.0 mA IO = −5.2 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 20 µA IO = 20 µA IO = 4.0 mA IO = 5.2 mA ILI ICC input leakage current quiescent supply current VI = VCC or GND VI = VCC or GND; IO = 0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 − − − − − − − 0 0 0 0.15 0.16 − − 0.1 0.1 0.1 0.33 0.33 ±1.0 10 V V V V V µA µA 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 4.13 5.63 2.0 4.5 6.0 4.32 5.81 − − − − − V V V V V 1.5 3.15 4.2 − − − 1.2 2.4 3.2 0.8 2.1 2.8 − − − 0.5 1.35 1.8 V V V V V V VCC (V) MIN. TYP. MAX. UNIT 2003 Feb 12 6 Philips Semiconductors Product specification Dual 2-input NAND gate 74HC2G00; 74HCT2G00 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +125 °C VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −20 µA IO = −20 µA IO = −4.0 mA IO = −5.2 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 20 µA IO = 20 µA IO = 4.0 mA IO = 5.2 mA ILI ICC Note 1. All typical values are measured at Tamb = 25 °C. input leakage current quiescent supply current VI = VCC or GND VI = VCC or GND; IO = 0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 − − − − − − − − − − − − − − 0.1 0.1 0.1 0.4 0.4 ±1.0 20 V V V V V µA µA 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 3.7 5.2 − − − − − − − − − − V V V V V 1.5 3.15 4.2 − − − − − − − − − − − − 0.5 1.35 1.8 V V V V V V VCC (V) MIN. TYP. MAX. UNIT 2003 Feb 12 7 Philips Semiconductors Product specification Dual 2-input NAND gate 74HC2G00; 74HCT2G00 Type 74HCT2G00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V); note 1. TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 4.0 mA ILI ICC ∆ICC input leakage current quiescent supply current additional supply current per input VI = VCC or GND VI = VCC or GND; IO = 0 4.5 4.5 5.5 5.5 − − − − − 0 0.15 − − − 0.1 0.33 ±1.0 10 375 V V µA µA µA 4.5 4.5 4.4 4.13 4.5 4.32 − − V V 4.5 to 5.5 4.5 to 5.5 2.0 − 1.6 1.2 − 0.8 V V VCC (V) MIN. TYP. MAX. UNIT VI = VCC − 2.1 V; IO = 0 4.5 to 5.5 Tamb = −40 to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 4.0 mA ILI ICC ∆ICC Note 1. All typical values are measured at Tamb = 25 °C. input leakage current quiescent supply current additional supply current per input VI = VCC or GND VI = VCC or GND; IO = 0 4.5 4.5 5.5 5.5 − − − − − − − − − 0.1 0.4 ±1.0 20 410 V V µA µA µA 4.5 4.5 4.4 3.7 − − − − V V 4.5 to 5.5 4.5 to 5.5 2.0 − − − − 0.8 V V VI = VCC − 2.1 V; IO = 0 4.5 to 5.5 2003 Feb 12 8 Philips Semiconductors Product specification Dual 2-input NAND gate AC CHARACTERISTICS Type 74HC2G00 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF; note 1. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 to +85 °C tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 2.0 4.5 6.0 tTHL/tTLH output transition time see Figs 5 and 6 2.0 4.5 6.0 Tamb = −40 to +125 °C tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 2.0 4.5 6.0 tTHL/tTLH output transition time see Figs 5 and 6 2.0 4.5 6.0 Note 1. All typical values are measured at Tamb = 25 °C. Type 74HCT2G00 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF; note 1. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 to +85 °C tPHL/tPLH tTHL/tTLH propagation delay nA, nB to nY output transition time see Figs 5 and 6 see Figs 5 and 6 4.5 4.5 VCC (V) VCC (V) 74HC2G00; 74HCT2G00 MIN. TYP. MAX. UNIT − − − − − − − − − − − − 25 9 7 18 6 5 − − − − − − 95 19 16 95 19 16 ns ns ns ns ns ns 110 22 20 125 25 20 ns ns ns ns ns ns MIN. TYP. MAX. UNIT − − − − 12 6 − − 24 19 ns ns Tamb = −40 to +125 °C tPHL/tPLH tTHL/tTLH Note 1. All typical values are measured at Tamb = 25 °C. propagation delay nA, nB to nY output transition time see Figs 5 and 6 see Figs 5 and 6 4.5 4.5 29 22 ns ns 2003 Feb 12 9 Philips Semiconductors Product specification Dual 2-input NAND gate AC WAVEFORMS 74HC2G00; 74HCT2G00 V handbook, halfpage I nA, nB input GND t PHL VOH nY output VOL t THL VM VM 10% VM VM t PLH 90% t TLH MNA714 For 74HC2G00: VM = 50%; VI = GND to VCC. For 74HCT2G00: VM = 1.3 V; VI = GND to 3.0 V. Fig.5 The input (nA, nB) to output (nY) propagation delays and transition times. handbook, full pagewidth S1 VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF MNA742 VCC open GND RL VO 1 kΩ TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH open Vcc GND S1 Definitions for test circuit: CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.6 Load circuitry for switching times. 2003 Feb 12 10 Philips Semiconductors Product specification Dual 2-input NAND gate PACKAGE OUTLINES 74HC2G00; 74HCT2G00 TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 2003 Feb 12 11 Philips Semiconductors Product specification Dual 2-input NAND gate 74HC2G00; 74HCT2G00 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 2003 Feb 12 12 Philips Semiconductors Product specification Dual 2-input NAND gate SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept: • below 220 °C for all the BGA packages and packages with a thickness ≥ 2.5mm and packages with a thickness