74HC2G126DP

INTEGRATED CIRCUITS DATA SHEET 74HC2G126; 74HCT2G126 Dual buffer/line driver; 3-state Product specification 2003 Mar 03 Philips Semiconductors Product specification Dual buffer/line driver; 3-state FEATURES • Wide operating voltage from 2.0 to 6.0 V • Symmetrical output impedance • High noise immunity • Low power dissipation • Balanced propagation delays • Very small 8 pins package • Output capability: bus driver • ESD protection: – HBM EIA/JESD22-A114-A exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V • Specified from −40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = rf ≤ 6.0 ns. 74HC2G126; 74HCT2G126 DESCRIPTION The 74HC2G/HCT2G126 is a high-speed Si-gate CMOS device. The 74HC2G/HCT2G126 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input pin (OE). A LOW at pin OE causes the output as assume a high-impedance OFF-state. The bus driver output currents are equal compared to the 74HC/HCT126. TYPICAL SYMBOL tPHL/tPLH CI CO CPD PARAMETER propagation delay nA to nY input capacitance output capacitance power dissipation capacitance output enabled; notes 1 and 2 per buffer output disabled; notes 1 and 2 CONDITIONS HC2G CL = 15 pF; VCC = 5 V 10 1 1.5 11 1 1 1.5 11 1 HCT2G 12 ns pF pF pF pF UNIT Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For the 74HC2G126 the condition is VI = GND to VCC. For the 74HCT2G126 the condition is VI = GND to VCC − 1.5 V. 2003 Mar 03 2 Philips Semiconductors Product specification Dual buffer/line driver; 3-state FUNCTION TABLE See note 1. INPUT nOE H H L Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. ORDERING INFORMATION TYPE NUMBER 74HC2G126DP 74HCT2G126DP 74HC2G126DC 74HCT2G126DC PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 1A 2Y GND 2A 1Y 2OE VCC SYMBOL 1OE output enable input data input data output ground (0 V) data input data output output enable input supply voltage TEMPERATURE RANGE −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C nA L H X 74HC2G126; 74HCT2G126 OUTPUT nY L H Z PACKAGE PINS 8 8 8 8 PACKAGE TSSOP8 TSSOP8 VSSOP8 VSSOP8 MATERIAL plastic plastic plastic plastic CODE SOT505-2 SOT505-2 SOT765-1 SOT765-1 MARKING H26 T26 H26 T26 DESCRIPTION 2003 Mar 03 3 Philips Semiconductors Product specification Dual buffer/line driver; 3-state 74HC2G126; 74HCT2G126 handbook, halfpage handbook, halfpage 1OE 1 1A 2 8 VCC 7 2OE 2 1 5 7 1A 1OE 2A 2OE 1Y 6 2Y 3 126 2Y 3 GND 4 MNA945 6 1Y 5 2A MNA946 Fig.1 Pin configuration. Fig.2 Logic symbol. handbook, halfpage 2 1 5 3 7 MNA947 1 EN1 6 handbook, halfpage A Y OE MNA127 Fig.3 Logic symbol (IEEE/IEC). Fig.4 Logic diagram (one driver). 2003 Mar 03 4 Philips Semiconductors Product specification Dual buffer/line driver; 3-state RECOMMENDED OPERATING CONDITIONS 74HC2G126; 74HCT2G126 74HC2G126 SYMBOL VCC VI VO Tamb PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times see DC and AC characteristics per device VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CONDITIONS MIN. 2.0 0 0 −40 TYP. 5.0 − − +25 MAX. 6.0 VCC VCC +125 74HCT2G126 UNIT MIN. 4.5 0 0 −40 TYP. 5.0 − − +25 MAX. 5.5 VCC VCC +125 V V V °C tr, tf − − − − 6.0 − 1000 500 400 − − − − 6.0 − − 500 − ns ns ns LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK IOK IO ICC, IGND Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 110 °C the value of PD derates linearly with 8 mW/K. PARAMETER supply voltage input diode current output diode current output source or sink current VCC or GND current storage temperature power dissipation per package for temperature range from −40 to +125 °C; note 2 VI < −0.5 V or VI > VCC + 0.5 V; note 1 VO < −0.5 V or VO > VCC + 0.5 V; note 1 −0.5 V < VO < VCC + 0.5 V; note 1 note 1 CONDITIONS MIN. −0.5 − − − − −65 − MAX. +7.0 ±20 ±20 25 50 +150 300 UNIT V mA mA mA mA °C mW 2003 Mar 03 5 Philips Semiconductors Product specification Dual buffer/line driver; 3-state DC CHARACTERISTICS 74HC2G126; 74HCT2G126 Type 74HC2G126 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −20 µA IO = −20 µA IO = −6.0 mA IO = −7.8 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 20 µA IO = 20 µA IO = 6.0 mA IO = 7.8 mA ILI IOZ ICC input leakage current VI = VCC or GND 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current VI = VCC or GND; IO = 0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 6.0 − − − − − − − − 0 0 0 0.15 0.16 − − − 0.1 0.1 0.1 0.33 0.33 ±1.0 ±.5.0 10 V V V V V µA µA µA 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 4.13 5.63 2.0 4.5 6.0 4.32 5.81 − − − − − V V V V V 1.5 3.15 4.2 − − − 1.2 2.4 3.2 0.8 2.1 2.8 − − − 0.5 1.35 1.8 V V V V V V VCC (V) MIN. TYP.(1) MAX. UNIT 2003 Mar 03 6 Philips Semiconductors Product specification Dual buffer/line driver; 3-state 74HC2G126; 74HCT2G126 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +125 °C VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −20 µA IO = −20 µA IO = −6.0 mA IO = −7.8 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 20 µA IO = 20 µA IO = 6.0 mA IO = 7.8 mA ILI IOZ ICC Note 1. All typical values are measured at Tamb = 25°C. input leakage current VI = VCC or GND 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current VI = VCC or GND; IO = 0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 6.0 − − − − − − − − 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 3.7 5.2 1.5 3.15 4.2 − − − VCC (V) MIN. TYP.(1) MAX. UNIT − − − − − − − − − − − − − − − − − − − − − − 0.5 1.35 1.8 − − − − − 0.1 0.1 0.1 0.4 0.4 ±1.0 ±10.4 20 V V V V V V V V V V V V V V V V µA µA µA 2003 Mar 03 7 Philips Semiconductors Product specification Dual buffer/line driver; 3-state 74HC2G126; 74HCT2G126 Type 74HCT2G126 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −6.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 6.0 mA ILI IOZ ICC ∆ICC input leakage current VI = VCC or GND 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current additional supply current per input VI = VCC or GND; IO = 0 VI = VCC − 2.1 V; IO = 0 4.5 4.5 5.5 5.5 5.5 4.5 to 5.5 − − − − − − 0 0.15 − − − − 0.1 0.33 ±1.0 ±5.0 10 375 V V µA µA µA µA 4.5 4.5 4.4 4.13 4.5 4.32 − − V V 4.5 to 5.5 4.5 to 5.5 2.0 − 1.6 1.2 − 0.8 V V VCC (V) MIN. TYP.(1) MAX. UNIT Tamb = −40 to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −6.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 6.0 mA ILI IOZ ICC ∆ICC Note 1. All typical values are measured at Tamb = 25°C. input leakage current VI = VCC or GND 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current additional supply current per input VI = VCC or GND; IO = 0 VI = VCC − 2.1 V; IO = 0 4.5 4.5 5.5 5.5 5.5 4.5 to 5.5 − − − − − − − − − − − − 0.1 0.4 ±1.0 ±10.4 20 410 V V µA µA µA µA 4.5 4.5 4.4 3.7 − − − − V V 4.5 to 5.5 4.5 to 5.5 2.0 − − − − 0.8 V V 2003 Mar 03 8 Philips Semiconductors Product specification Dual buffer/line driver; 3-state AC CHARACTERISTICS Type 74HC2G126 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF. 74HC2G126; 74HCT2G126 TEST CONDITIONS SYMBOL Tamb = −40 to +85 °C tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 2.0 4.5 6.0 tPZH/tPZL 3-state output enable time nOE to nY see Figs 6 and 7 2.0 4.5 6.0 tPHZ/tPLZ 3-state output disable time nOE to nY see Figs 6 and 7 2.0 4.5 6.0 tTHL/tTLH output transition time see Figs 5 and 7 2.0 4.5 6.0 Tamb = −40 to +125 °C tPHL/tPLH propagation delay nA to nY see Figs 5 and 7 2.0 4.5 6.0 tPZH/tPZL 3-state output enable time nOE to nY see Figs 6 and 7 2.0 4.5 6.0 tPHZ/tPLZ 3-state output disable time nOE to nY see Figs 6 and 7 2.0 4.5 6.0 tTHL/tTLH output transition time see Figs 5 and 7 2.0 4.5 6.0 Note 1. All typical values are measured at Tamb = 25°C. − − − − − − − − − − − − − − − − − − − − − − − − PARAMETER WAVEFORMS VCC (V) MIN. TYP.(1) MAX. UNIT 35 11 8 40 11 8 25 12 10 18 6 5 − − − − − − − − − − − − 115 23 20 115 23 20 125 25 21 75 15 13 ns ns ns ns ns ns ns ns ns ns ns ns 135 27 23 135 27 23 150 30 26 90 18 15 ns ns ns ns ns ns ns ns ns ns ns ns 2003 Mar 03 9 Philips Semiconductors Product specification Dual buffer/line driver; 3-state Type 74HCT2G126 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF. 74HC2G126; 74HCT2G126 TEST CONDITIONS SYMBOL Tamb = −40 to +85 °C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tTHL/tTLH propagation delay nA to nY see Figs 5 and 7 4.5 4.5 4.5 4.5 − − − − − − − − PARAMETER WAVEFORMS VCC (V) MIN. TYP.(1) MAX. UNIT 15 11 11 6 − − − − 30 31 35 15 ns ns ns ns 3-state output enable time nOE to nY see Figs 6 and 7 3-state output disable time nOE to nY see Figs 6 and 7 output transition time see Figs 5 and 7 Tamb = −40 to +125 °C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tTHL/tTLH Note 1. All typical values are measured at Tamb = 25°C. AC WAVEFORMS propagation delay nA to nY see Figs 5 and 7 4.5 4.5 4.5 4.5 36 38 42 18 ns ns ns ns 3-state output enable time nOE to nY see Figs 6 and 7 3-state output disable time nOE to nY see Figs 6 and 7 output transition time see Figs 5 and 7 handbook, halfpage VI VM GND tPHL VOH 90% VM VOL 10% tTHL tTLH MNA948 nA input tPLH VI nY output For 74HC2G126: VM = 50%; VI = GND to VCC For 74HCT2G126: VM = 1.3 V; VI = GND to 3.0 V. Fig.5 The input (nA) to output (nY) propagation delays. 2003 Mar 03 10 Philips Semiconductors Product specification Dual buffer/line driver; 3-state 74HC2G126; 74HCT2G126 handbook, full pagewidth VI nOE input GND t PLZ VCC output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled MNA949 VM t PZL VM VX t PZH VY VM For 74HC2G126: VM = 50%; VI = GND to VCC For 74HCT2G126: VM = 1.3 V; VI = GND to 3.0 V. Fig.6 The 3-state enable and disable times. handbook, full pagewidth S1 VCC PULSE GENERATOR VI D.U.T. RT CL MNA232 VO RL = 1000 Ω VCC open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH open VCC GND S1 Definitions for test circuit: CL = Load capacitance including jig and probe capacitance (see “AC characteristics” for values). RL = Load resistance (see “AC characteristics” for values). RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.7 Load circuitry for switching times. 2003 Mar 03 11 Philips Semiconductors Product specification Dual buffer/line driver; 3-state PACKAGE OUTLINES 74HC2G126; 74HCT2G126 TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 2003 Mar 03 12 Philips Semiconductors Product specification Dual buffer/line driver; 3-state 74HC2G126; 74HCT2G126 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 2003 Mar 03 13 Philips Semiconductors Product specification Dual buffer/line driver; 3-state SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept: • below 220 °C for all the BGA packages and packages with a thickness ≥ 2.5mm and packages with a thickness