74HCHCT377

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT377 Octal D-type flip-flop with data enable; positive-edge trigger Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger FEATURES • Ideal for addressable register applications • Data enable for address and data synchronization applications • Eight positive-edge triggered D-type flip-flops • See “273” for master reset version • See “373” for transparent latch version • See “374” for 3-state version • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION 74HC/HCT377 The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT377 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 13 77 3.5 20 HCT 14 53 3.5 20 ns MHz pF pF UNIT December 1990 2 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger PIN DESCRIPTION PIN NO. 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 SYMBOL E Q0 to Q7 D0 to D7 GND CP VCC NAME AND FUNCTION data enable input (active LOW) flip-flop outputs data inputs ground (0 V) 74HC/HCT377 clock input (LOW-to-HIGH, edge-triggered) positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger FUNCTION TABLE OPERATING MODES load “1” load “0” hold (do nothing) Notes 74HC/HCT377 INPUTS CP ↑ ↑ ↑ X E l l h H Dn h l X X OUTPUTS Qn H L no change no change 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition ↑ = LOW-to-HIGH CP transition X = don’t care Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 max. 240 48 41 110 22 19 120 24 20 90 18 15 90 18 15 3 3 3 4 4 4 4 20 24 ns 74HC/HCT377 TEST CONDITIONS UNIT V WAVEFORMS CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 min. typ. max. min. max. min. tPHL/ tPLH propagation delay CP to Qn output transition time 44 16 13 19 7 6 80 16 14 60 12 10 60 12 10 3 3 3 4 4 4 6 30 35 14 5 4 14 5 4 6 2 2 −8 −3 −2 −3 −1 −1 23 70 83 160 32 27 75 15 13 100 20 17 75 15 13 75 15 13 3 3 3 4 4 4 5 24 28 200 40 34 95 19 16 tTHL/ tTLH ns Fig.6 tW clock pulse width HIGH or LOW set-up time Dn to CP set-up time E to CP hold time Dn to CP hold time E to CP maximum clock pulse frequency ns Fig.6 tsu ns Fig.7 tsu ns Fig.7 th ns Fig.7 th ns Fig.7 fmax MHz Fig.6 December 1990 5 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types 74HC/HCT377 The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT E CP Dn UNIT LOAD COEFFICIENT 1.50 0.50 0.20 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HCT SYMBOL PARAMETER +25 −40 to +85 −40 to +125 max. 48 22 30 18 33 2 3 18 ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.6 Fig.6 Fig.7 Fig.7 Fig.7 Fig.7 Fig.6 UNIT V WAVEFORMS CC (V) TEST CONDITIONS min. typ. max. min. max. min. tPHL/ tPLH tTHL/ tTLH tW tsu tsu th th fmax propagation delay CP to Qn output transition time clock pulse width HIGH or LOW set-up time Dn to CP set-up time E to CP hold time Dn to CP hold time E to CP maximum clock pulse frequency 20 12 22 2 3 27 17 7 8 4 12 −4 −2 48 32 15 25 15 28 2 3 22 40 19 December 1990 6 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger AC WAVEFORMS 74HC/HCT377 (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the data set-up and hold times from the data input (Dn) and from the data enable input (E) to the clock (CP). PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7