74HCT242

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT242 Quad bus transceiver; 3-state; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Quad bus transceiver; 3-state; inverting FEATURES • Inverting 3-state outputs • 2-way asynchronous data bus communication • Output capability: bus driver • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT242 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL 74HC/HCT242 (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT242 are quad bus transceivers featuring inverting 3-state bus compatible outputs in both send and receive directions. They are designed for 4-line asynchronous 2-way data communications between data buses. The output enable inputs (OEA and OEB) can be used to isolate the buses. The “242” is similar to the “243” but has inverting outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay An to Bn; Bn to An input capacitance input/output capacitance power dissipation capacitance per transceiver notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 7 HCT 10 ns UNIT CI CI/O CPD Notes 3.5 10 29 3.5 10 32 pF pF pF 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 Philips Semiconductors Product specification Quad bus transceiver; 3-state; inverting PIN DESCRIPTION PIN NO. 1 2, 12 3, 4, 5, 6 7 11, 10, 9, 8 13 14 SYMBOL OEA n.c. A0 to A3 GND B0 to B3 OEB VCC NAME AND FUNCTION output enable input (active LOW) not connected data inputs/outputs ground (0 V) data inputs/outputs output enable input positive supply voltage 74HC/HCT242 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Quad bus transceiver; 3-state; inverting FUNCTION TABLE INPUTS OEA L H L H Note OEB L L H H 74HC/HCT242 INPUTS/OUTPUTS An inputs Z Z A=B Bn B=A Z Z inputs 1. H = HIGH voltage level L = LOW voltage level Z = high impedance OFF-state Fig.4 Functional diagram. December 1990 4 Philips Semiconductors Product specification Quad bus transceiver; 3-state; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC SYMBOL PARAMETER +25 −40 to +85 max. 115 23 20 190 38 33 190 38 33 75 15 13 −40 to +125 min. max. 135 27 23 225 45 38 225 45 38 90 18 15 ns 74HC/HCT242 TEST CONDITIONS UNIT V WAVEFORMS CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.5 min. typ. max. min. tPHL/ tPLH propagation delay An to Bn; Bn to An 3-state output enable time OEA to An or Bn; OEB to An or Bn 3-state output disable time OEA to An or Bn; OEB to An or Bn output transition time 25 9 7 41 15 12 52 19 15 14 5 4 90 18 15 150 30 26 150 30 26 60 12 10 tPZH/ tPZL ns Figs 6 and 7 tPHZ/ tPLZ ns Figs 6 and 7 tTHL/ tTLH ns Fig.5 December 1990 5 Philips Semiconductors Product specification Quad bus transceiver; 3-state; inverting 74HC/HCT242 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT An Bn OEA OEB UNIT LOAD COEFFICIENT 1.10 1.10 1.00 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH propagation delay An to Bn; Bn to An 3-state output enable time OEA to An or Bn; OEB to An or Bn 3-state output disable time OEA to An or Bn; OEB to An or Bn output transition time +25 typ. 12 −40 to +85 −40 to +125 UNIT V WAVEFORMS CC (V) ns 4.5 Fig.5 TEST CONDITIONS max. min. max. min. max. 20 25 30 tPZH/ tPZL 16 34 43 51 ns 4.5 Figs 6 and 7 tPHZ/ tPLZ 22 35 44 53 ns 4.5 Figs 6 and 7 tTHL/ tTLH 5 12 15 18 ns 4.5 Fig.5 December 1990 6 Philips Semiconductors Product specification Quad bus transceiver; 3-state; inverting AC WAVEFORMS 74HC/HCT242 (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.5 Waveforms showing the input (An, Bn) to output (Bn, An) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the 3-state enable and disable times for input OEB. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times for input OEA. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7