74HCT2G86DC

INTEGRATED CIRCUITS DATA SHEET 74HC2G86; 74HCT2G86 Dual 2-input exclusive-OR gate Product specification Supersedes data of 2002 Jul 17 2003 Jul 28 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate FEATURES • Wide supply voltage range from 2.0 to 6.0 V • Symmetrical output impedance • High noise immunity • Low power dissipation • Balanced propagation delays • Very small 8 pins package • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns. DESCRIPTION 74HC2G86; 74HCT2G86 The 74HC2G/HCT2G86 is a high-speed Si-gate CMOS device. The 74HC2G/HCT2G86 provides dual 2-input exclusive-OR gate. TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total switching outputs; ∑ (CL × VCC2 × fo) = sum of outputs. 2. For 74HC2G86 the condition is VI = GND to VCC. For 74HCT2G86 the condition is VI = GND to VCC − 1.5 V. PARAMETER propagation delay nA to nY input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS HC2G86 CL = 50 pF; VCC = 4.5 V 11 1.5 10 HCT2G86 11 1.5 9 ns pF pF UNIT 2003 Jul 28 2 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION PACKAGE TYPE NUMBER 74HC2G86DP 74HCT2G86DP 74HC2G86DC 74HCT2G86DC PINNING PIN 1 2 3 4 5 6 7 8 1A 1B 2Y GND 2A 2B 1Y VCC SYMBOL data input 1A data input 1B data output 2Y ground (0 V) data input 2A data input 2B data output 1Y supply voltage TEMPERATURE RANGE −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C PINS 8 8 8 8 PACKAGE TSSOP8 TSSOP8 VSSOP8 VSSOP8 nA L H L H 74HC2G86; 74HCT2G86 OUTPUT nY L H H L MATERIAL plastic plastic plastic plastic CODE SOT505-2 SOT505-2 SOT765-1 SOT765-1 MARKING H86 T86 H86 H86 DESCRIPTION 2003 Jul 28 3 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate 74HC2G86; 74HCT2G86 handbook, halfpage 1A 1 1B 2 8 VCC 7 1Y 2B 2A handbook, halfpage 1 2 5 6 1A 1B 2A 2B 1Y 7 86 2Y GND 3 4 MNA736 6 5 2Y 3 MNA737 Fig.1 Pin configuration. Fig.2 Logic symbol. handbook, halfpage 1 2 =1 7 handbook, halfpage B 5 6 Y =1 3 A MNA040 MNA738 Fig.3 IEC logic symbol. Fig.4 Logic diagram (one driver). 2003 Jul 28 4 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate RECOMMENDED OPERATING CONDITIONS 74HC2G86 SYMBOL VCC VI VO Tamb PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times CONDITIONS MIN. 2.0 0 0 see DC and AC −40 characteristics per device VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V − − − TYP. 5.0 − − +25 74HC2G86; 74HCT2G86 74HCT2G86 UNIT MIN. 4.5 0 0 −40 TYP. 5.0 − − +25 MAX. 5.5 VCC VCC +125 V V V °C MAX. 6.0 VCC VCC +125 tr, tf − 6.0 − 1000 500 400 − − − − 6.0 − − 500 − ns ns ns LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 110 °C the value of PD derates linearly with 8 mW/K. PARAMETER supply voltage input diode current output diode current output source or sink current VCC or GND current storage temperature power dissipation Tamb = −40 to +125 °C; note 2 VI < −0.5 V or VI > VCC + 0.5 V; note 1 VO < −0.5 V or VO > VCC + 0.5 V; note 1 −0.5 V < VO < VCC + 0.5 V; note 1 note 1 CONDITIONS MIN. −0.5 − − − − −65 − MAX. +7.0 ±20 ±20 25 50 +150 300 UNIT V mA mA mA mA °C mW 2003 Jul 28 5 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate DC CHARACTERISTICS 74HC2G86; 74HCT2G86 Type 74HC2G86 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb = 25 °C VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −20 µA IO = −20 µA IO = −4.0 mA IO = −5.2 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 20 µA IO = 20 µA IO = 4.0 mA IO = 5.2 mA ILI ICC input leakage current quiescent supply current VI = VCC or GND VI = VCC or GND; IO = 0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 − − − − − − − 0 0 0 0.15 0.16 − − 0.1 0.1 0.1 0.26 0.26 ±0.1 1.0 V V V V V µA µA 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.32 5.81 − − − − − V V V V V 1.5 3.15 4.2 − − − 1.2 2.4 3.2 0.8 2.1 2.8 − − − 0.5 1.35 1.8 V V V V V V PARAMETER OTHER VCC (V) MIN. TYP. MAX. UNIT 2003 Jul 28 6 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate 74HC2G86; 74HCT2G86 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −20 µA IO = −20 µA IO = −4.0 mA IO = −5.2 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 20 µA IO = 20 µA IO = 4.0 mA IO = 5.2 mA ILI ICC input leakage current quiescent supply current VI = VCC or GND VI = VCC or GND; IO = 0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 − − − − − − − − − − − − − − 0.1 0.1 0.1 0.33 0.33 ±1.0 10 V V V V V µA µA 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 4.13 5.63 − − − − − − − − − − V V V V V 1.5 3.15 4.2 − − − − − − − − − − − − 0.5 1.35 1.8 V V V V V V VCC (V) MIN. TYP. MAX. UNIT 2003 Jul 28 7 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate 74HC2G86; 74HCT2G86 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +125 °C VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOH HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −20 µA IO = −20 µA IO = −4.0 mA IO = −5.2 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 20 µA IO = 20 µA IO = 4.0 mA IO = 5.2 mA ILI ICC input leakage current quiescent supply current VI = VCC or GND VI = VCC or GND; IO = 0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 − − − − − − − − − − − − − − 0.1 0.1 0.1 0.4 0.4 ±1.0 20 V V V V V µA µA 2.0 4.5 6.0 4.5 6.0 1.9 4.4 5.9 3.7 5.2 − − − − − − − − − − V V V V V 1.5 3.15 4.2 − − − − − − − − − − − − 0.5 1.35 1.8 V V V V V V VCC (V) MIN. TYP. MAX. UNIT 2003 Jul 28 8 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate 74HC2G86; 74HCT2G86 Type 74HCT2G86 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb = 25 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 4.0 mA ILI ICC ∆ICC input leakage current quiescent supply current additional supply current per input VI = VCC or GND VI = VCC or GND; IO = 0 VI = VCC − 2.1 V; IO = 0 4.5 4.5 5.5 5.5 4.5 to 5.5 − − − − − 0 0.15 − − − 0.1 0.26 ±0.1 1.0 300 V V µA µA µA 4.5 4.5 4.4 4.18 4.5 4.32 − − V V 4.5 to 5.5 4.5 to 5.5 2.0 − 1.6 1.2 − 0.8 V V PARAMETER OTHER VCC (V) MIN. TYP. MAX. UNIT Tamb = −40 to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 4.0 mA ILI ICC ∆ICC input leakage current quiescent supply current additional supply current per input VI = VCC or GND VI = VCC or GND; IO = 0 VI = VCC − 2.1 V; IO = 0 4.5 4.5 5.5 5.5 4.5 to 5.5 − − − − − − − − − − 0.1 0.33 ±1.0 10 375 V V µA µA µA 4.5 4.5 4.4 4.13 − − − − V V 4.5 to 5.5 4.5 to 5.5 2.0 − − − − 0.8 V V 2003 Jul 28 9 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate 74HC2G86; 74HCT2G86 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −20 µA IO = −4.0 mA VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA IO = 4.0 mA ILI ICC ∆ICC input leakage current quiescent supply current additional supply current per input VI = VCC or GND VI = VCC or GND; IO = 0 VI = VCC − 2.1 V; IO = 0 4.5 4.5 5.5 5.5 4.5 to 5.5 − − − − − − − − − − 0.1 0.4 ±1.0 20 410 V V µA µA µA 4.5 4.5 4.4 3.7 − − − − V V 4.5 to 5.5 4.5 to 5.5 2.0 − − − − 0.8 V V VCC (V) MIN. TYP. MAX. UNIT 2003 Jul 28 10 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate AC CHARACTERISTICS Type 74HC2G86 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF. TEST CONDITIONS SYMBOL Tamb = 25 °C tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 2.0 4.5 6.0 tTHL/tTLH output transition time see Figs 5 and 6 2.0 4.5 6.0 Tamb = −40 to +85 °C tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 2.0 4.5 6.0 tTHL/tTLH output transition time see Figs 5 and 6 2.0 4.5 6.0 Tamb = −40 to +125 °C tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 2.0 4.5 6.0 tTHL/tTLH output transition time see Figs 5 and 6 2.0 4.5 6.0 PARAMETER WAVEFORMS 74HC2G86; 74HCT2G86 MIN. VCC (V) − − − − − − − − − − − − − − − − − − TYP. MAX. UNIT 34 11 9 18 6 5 − − − − − − − − − − − − 120 20 17 75 15 13 ns ns ns ns ns ns 150 25 21 95 19 16 ns ns ns ns ns ns 180 36 30 110 22 20 ns ns ns ns ns ns 2003 Jul 28 11 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate Type 74HCT2G86 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF. TEST CONDITIONS SYMBOL Tamb = 25 °C tPHL/tPLH tTHL/tTLH propagation delay nA, nB to nY output transition time see Figs 5 and 6 see Figs 5 and 6 4.5 4.5 PARAMETER WAVEFORMS 74HC2G86; 74HCT2G86 MIN. VCC (V) − − − − − − TYP. MAX. UNIT 11 6 − − − − 19 15 ns ns Tamb = −40 to +85 °C tPHL/tPLH tTHL/tTLH propagation delay nA, nB to nY output transition time see Figs 5 and 6 see Figs 5 and 6 4.5 4.5 23 19 ns ns Tamb = −40 to +125 °C tPHL/tPLH tTHL/tTLH propagation delay nA, nB to nY output transition time see Figs 5 and 6 see Figs 5 and 6 4.5 4.5 48 22 ns ns AC WAVEFORMS V handbook, halfpage I nA, nB input GND t PHL VOH nY output VOL t THL VM VM 10% VM VM t PLH 90% t TLH MNA726 For HC2G: VM = 50%; VI = GND to VCC. For HCT2G: VM = 1.3 V; VI = GND to 3.0 V. Fig.5 The input (nA, nB) to output (nY) propagation delays. 2003 Jul 28 12 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate 74HC2G86; 74HCT2G86 handbook, full pagewidth S1 VCC PULSE GENERATOR VI D.U.T. RT CL = 50 pF MNA742 VCC open GND RL = VO 1 kΩ TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH open VCC GND S1 Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.6 Load circuitry for switching times. 2003 Jul 28 13 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate PACKAGE OUTLINES 74HC2G86; 74HCT2G86 TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 2003 Jul 28 14 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate 74HC2G86; 74HCT2G86 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 2003 Jul 28 15 Philips Semiconductors Product specification Dual 2-input exclusive-OR gate DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development 74HC2G86; 74HCT2G86 DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Jul 28 16 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/02/pp17 Date of release: 2003 Jul 28 Document order number: 9397 750 10567