74HCT401

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT40102 8-bit synchronous BCD down counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-bit synchronous BCD down counter FEATURES • Cascadable • Synchronous or asynchronous preset • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT40102 are high-speed Si-gate CMOS devices and are pin compatible with the “40102” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40102 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The “40102” is configured as two cascaded 4-bit BCD counters and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT40102 When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0 to P7) represent two 4-bit BCD words. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 99) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the function table. If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 clock pulses long. The “40102” may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode. APPLICATIONS • Divide-by-n counters • Programmable timers • Interrupt timers • Cycle/program counters TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V PARAMETER propagation delay CP to TC maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 30 30 3.5 20 HCT 31 30 3.5 25 ns MHz pF pF UNIT December 1990 2 Philips Semiconductors Product specification 8-bit synchronous BCD down counter 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PIN DESCRIPTION PIN NO. 1 2 3 4, 5, 6, 7, 10, 11, 12, 13 8 9 14 15 16 SYMBOL CP MR TE P0 to P7 GND PL TC PE VCC NAME AND FUNCTION 74HC/HCT40102 clock input (LOW-to-HIGH, edge-triggered) asynchronous master reset input (active LOW) terminal enable input jam inputs ground (0 V) asynchronous preset enable input (active LOW) terminal count output (active LOW) synchronous preset enable input (active LOW) positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 Fig.4 Functional diagram. FUNCTION TABLE CONTROL INPUTS PRESET MODE MR H H H H L Notes 1. Clock connected to CP. 2. Synchronous operation: changes occur on the LOW-to-HIGH CP transition. 3. Jam inputs: MSD = P7, LSD = P0. H = HIGH voltage level L = LOW voltage level X = don’t care PL H H H L X PE H H L X X TE H L X X X asynchronous synchronous inhibit counter count down preset on next LOW-to HIGH clock transition preset asynchronously clear to maximum count ACTION December 1990 4 Philips Semiconductors Product specification 8-bit synchronous BCD down counter 74HC/HCT40102 Fig.5 Logic diagram. Fig.6 Timing diagram. December 1990 5 Philips Semiconductors Product specification 8-bit synchronous BCD down counter DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. max. 450 90 77 300 60 51 510 102 87 415 83 71 110 22 19 250 50 43 225 45 38 190 38 32 75 15 13 150 30 26 265 53 45 74HC/HCT40102 TEST CONDITIONS UNIT V WAVEFORMS CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.8 min. typ. max. min. max. tPHL/ tPLH propagation delay CP to TC propagation delay TE to TC propagation delay Pn, PL to TC propagation delay MR to TC output transition time 96 35 28 50 18 14 110 40 32 83 30 24 9 7 6 165 33 28 150 30 26 125 25 21 50 10 9 100 20 17 175 35 30 22 8 6 30 11 9 39 14 11 8 3 2 36 13 10 50 18 14 300 60 51 200 40 34 240 68 58 275 55 47 75 15 13 205 41 35 190 38 33 155 31 26 65 13 11 125 25 21 220 44 37 375 75 64 250 50 43 425 85 72 345 69 59 95 19 16 tPHL/ tPLH ns Fig.8 tPHL/ tPLH ns Fig.8 tPLH ns Fig.8 tTHL/ tTLH ns Figs 8 and 8 tW clock pulse width HIGH or LOW master reset pulse width LOW preset enable pulse width PL; LOW removal time PL; MR to CP set-up time PE to CP set-up time TE to CP ns Fig.8 tW ns Fig.8 tW ns Fig.8 trem ns Fig.8 tsu ns Fig.8 tsu ns Fig.8 December 1990 6 Philips Semiconductors Product specification 8-bit synchronous BCD down counter Tamb (°C) 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. 150 30 26 2 2 2 0 0 0 2 2 2 2 10 12 max. 74HC/HCT40102 TEST CONDITIONS WAVEFORMS UNIT V CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.8 min. typ. max. min. max. tsu set-up time Pn to CP hold time PE to CP hold time TE to CP hold time Pn to CP maximum clock pulse frequency 100 20 17 2 2 2 0 0 0 2 2 2 3 15 18 33 12 10 −8 −3 −2 −41 −15 −12 −5 −5 −5 8.9 27 32 125 25 21 2 2 2 0 0 0 2 2 2 2 12 14 th ns Fig.8 th ns Fig.8 th ns Fig.8 fmax MHz Fig.8 December 1990 7 Philips Semiconductors Product specification 8-bit synchronous BCD down counter DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI 74HC/HCT40102 Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT CP, PE MR TE Pn PL UNIT LOAD COEFFICIENT 1.50 1.00 0.80 0.25 0.35 December 1990 8 Philips Semiconductors Product specification 8-bit synchronous BCD down counter AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HCT SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. max. 95 75 125 83 22 50 45 65 15 30 60 30 0 0 0 10 74HC/HCT40102 TEST CONDITIONS WAVEFORMS UNIT V CC (V) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Figs 8 and 8 Fig.8 Fig.8 Fig.8 Figs 8 and 8 Fig.8 Fig.8 Fig.8 Fig.8 Fig.8 Fig.8 Fig.8 Fig.8 Fig.8 Fig.8 Fig.8 min. typ. max. min. max. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPLH tTHL/ tTLH tW tW tW trem tsu tsu tsu th th th fmax propagation delay Pn; CP to TC propagation delay TE to TC propagation delay PL to TC propagation delay MR to TC output transition time clock pulse width HIGH or LOW master reset pulse width LOW 33 30 38 25 49 31 7 11 16 25 1 10 20 12 −4 −15 −6 27 63 50 83 55 15 41 38 54 13 25 50 25 0 0 0 12 79 63 104 69 19 preset enable pulse width 43 PL; LOW removal time PL; MR to CP set-up time PE to CP set-up time TE to CP set-up time Pn to CP hold time PE to CP hold time TE to CP hold time Pn to CP maximum clock pulse frequency 10 20 40 20 0 0 0 15 December 1990 9 Philips Semiconductors Product specification 8-bit synchronous BCD down counter AC WAVEFORMS 74HC/HCT40102 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock input (CP) to TC propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the TE to TC propagation delays. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing PL, MR, Pn to TC propagation delays. Fig.10 Waveforms showing removal time for MR and PL. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing hold and set-up times for MR or PE to CP. Fig.12 Waveforms showing hold and set-up times for Pn, PE to CP. December 1990 10 Philips Semiconductors Product specification 8-bit synchronous BCD down counter APPLICATION INFORMATION 74HC/HCT40102 Fig.13 Programmable timer. Fig.14 Divide-by-N counter. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 11