74LV03N

INTEGRATED CIRCUITS 74LV03 Quad 2-input NAND gate Product specification Supersedes data of 1997 Mar 28 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 FEATURES • Wide operating voltage: 1.0 to 5.5V • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, • Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, • Level shifter capability • Output capability: standard • ICC category: SSI Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV03 is a low–voltage Si–gate CMOS device and is pin and function compatible with 74HC/HCT03. The 74LV03 provides the 2–input NAND function. The 74LV03 has open–drain N–transistor outputs, which are not clamped by a diode connected to VCC. In the OFF–state, i.e. when one input is LOW, the output may be pulled to any voltage between GND and VOmax. This allows the device to be used as a LOW–to–HIGH or HIGH–to–LOW level shifter. For digital operation and OR–tied output applications, these devices must have a pull–up resistor to establish a logic HIGH level. (open drain) QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL tPZL/tPLZ CI CPD PARAMETER Propagation delay nA, nB to nY Input capacitance Power dissipation capacitance per gate Notes 1, 2 CONDITIONS CL = 15pF VCC = 3.3V TYPICAL 8 3.5 4 UNIT ns pF pF NOTES: 1 CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 x fi )S (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2 The condition is VI = GND to VCC 3 The given value of CPD is obtained with : CL = 0 pF and RL = ∞ ORDERING INFORMATION PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C OUTSIDE NORTH AMERICA 74LV03 N 74LV03 D 74LV03 DB 74LV03 PW NORTH AMERICA 74LV03 N 74LV03 D 74LV03 DB 74LV03PW DH PKG. DWG. # SOT27-1 SOT108-1 SOT337-1 SOT402-1 PIN DESCRIPTION PIN NUMBER 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC Data inputs Data inputs Data outputs Ground (0V) Positive supply voltage FUNCTION FUNCTION TABLE INPUTS nA L L H H NOTES: H = HIGH voltage level L = LOW voltage level Z = High impedance OFF-state nB L H L H OUTPUT nY Z Z Z L 1998 Apr 20 2 853–1963 19257 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 PIN CONFIGURATION LOGIC SYMBOL 1 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4B 4 4A 5 4Y 3B 3A 3Y 12 13 9 10 2 1A 1Y 1B 3 2A 2Y 2B 6 3A 3Y 3B 8 4A 4Y 4B 11 SV00354 SV00355 LOGIC SYMBOL (IEEE/IEC) LOGIC DIAGRAM Y 1 2 & 3 A 4 5 & 6 GND B 9 10 & 8 SV00357 12 13 & 11 SV00356 1998 Apr 20 3 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V PARAMETER DC supply voltage CONDITIONS See Note1 MIN 1.0 0 0 –40 –40 – – – – – – – TYP. 3.3 – – MAX 5.5 VCC VCC +85 +125 500 200 100 50 UNIT V V V °C tr, tf ns/V NOTES: 1 The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC ±IIK ±IOK ±IO ±IGND, ±ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current – standard outputs DC VCC or GND current for types with –standard outputs Storage temperature range Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI < –0.5 or VI > VCC + 0.5V VO < –0.5 or VO > VCC + 0.5V –0.5V < VO < VCC + 0.5V CONDITIONS RATING –0.5 to +7.0 20 50 25 50 –65 to +150 750 500 400 UNIT V mA mA mA mA °C mW NOTES: 1 Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 20 4 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 DC CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2V VIH HIGH level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5V VCC = 1.2V VIL LOW level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5 VCC = 1.2V; VI = VIH or VIL; –IO = 100µA VOH HIGH level output level output voltage; all outputs all out VCC = 2.0V; VI = VIH or VIL; –IO = 100µA VCC = 2.7V; VI = VIH or VIL; –IO = 100µA VCC = 3.0V; VI = VIH or VIL; –IO = 100µA VCC = 4.5V;VI = VIH or VIL; –IO = 100µA VOH HIGH level output voltage; g STANDARD outputs VCC = 3.0V;VI = VIH or VIL; –IO = 6mA VCC = 4.5V;VI = VIH or VIL; –IO = 12mA VCC = 1.2V; VI = VIH or VIL; IO = 100µA VCC = 2.0V; VI = VIH or VIL; IO = 100µA VCC = 2.7V; VI = VIH or VIL; IO = 100µA VCC = 3.0V;VI = VIH or VIL; IO = 100µA VCC = 4.5V;VI = VIH or VIL; IO = 100µA VOL LOW level output voltage; g STANDARD outputs HIGH level output leakage current HIGH level output leakage current Input leakage current Quiescent supply current; SSI Additional quiescent supply current per input VCC = 3.0V;VI = VIH or VIL; IO = 6mA VCC = 4.5V;VI = VIH or VIL; IO = 12mA VCC = 2.0 to 3.6V; VI = VIL; VO = VCC or GND VCC = 2.0 to 3.6V; VI = VIL; VO = 6.0V2 VCC = 5.5V; VI = VCC or GND VCC = 5.5V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC –0.6V 1.8 2.5 2.8 4.3 2.40 3.60 1.2 2.0 2.7 3.0 4.5 2.82 4.20 0 0 0 0 0 0.25 0.35 0.2 0.2 0.2 0.2 0.40 0.55 5.0 10 1.0 20.0 500 0.2 0.2 0.2 0.2 0.50 V 0.65 10 20 1.0 40 850 µA µA µA µA µA V 1.8 2.5 2.8 4.3 2.20 V 3.50 V 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC -40°C to +85°C TYP1 MAX -40°C to +125°C MIN 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC V V MAX UNIT VOL LOW level output level output all out voltage; all outputs IOZ IOZ II ICC ∆ICC NOTES: 1 All typical values are measured at Tamb = 25°C. 2 The maximum operating output voltage (VO(max)) is 6.0V. 1998 Apr 20 5 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 AC CHARACTERISTICS FOR 74LV03 GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER CONDITION VCC(V) 1.2 2.0 tPZL/tPLZ Propagation delay Propagation delay nA, nB, to nY nA, nB, to nY Figures, 1, 2 2.7 3.0 to 3.6 4.5 to 5.5 NOTE: 1 Unless otherwise stated, all typical values are at Tamb = 25°C. 2 Typical value measured at VCC = 3.3V. 3 Typical value measured at VCC = 5.0V. MIN – – – – – LIMITS –40 to +85 °C TYP1 50 17 13 102 –3 MAX – 26 19 16 13 LIMITS –40 to +125 °C MIN – – – – – MAX – 31 23 19 16 ns WAVEFORM UNIT AC WAVEFORMS VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5V * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V and v 3.6V VX = VOL + 0.1 * VCC at VCC t 2.7V and w 4.5V TEST CIRCUIT VCC 2 * VCC Open GND VO D.U.T. RT CL 50 pF R L = 1k R L = 1k VI PULSE GENERATOR Test Circuit for Outputs VI nA, nB INPUT VCC tPLZ GND tPLH/tPHL nY OUTPUT VX tPHZ/tPZH GND VM tPLZ/tPZL Open 2 * VCC < 2.7V 2.7–3.6V w 4.5V VCC 2.7V VCC tPZL VM DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitiance. RT = Termination resistance should be equal to ZOUT of pulse generators. SWITCH POSITION TEST S1 VCC VI VOL SV00896 Figure 2. Load circuitry for switching times SV00358 Figure 1. Input (nA, nB) to output (nY) propagation delays. 1998 Apr 20 6 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 1998 Apr 20 7 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 1998 Apr 20 8 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 1998 Apr 20 9 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 1998 Apr 20 10 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 NOTES 1998 Apr 20 11 Philips Semiconductors Product specification Quad 2-input NAND gate 74LV03 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 08-98 9397-750-04403 Philips Semiconductors yyyy mmm dd 12