74LV10DB

INTEGRATED CIRCUITS 74LV10 Triple 3-input NAND gate Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, • Output capability: standard • ICC category: SSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay nA, nB, nC to nY Input capacitance Power dissipation capacitance per gate Tamb = 25°C. Tamb = 25°C. DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. CONDITIONS CL = 15 pF; VCC = 3.3 V See Notes 1 and 2 TYPICAL 9 3.5 12 UNIT ns pF pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 fo) where: PD = CPD × VCC2 × fi ) (CL fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C OUTSIDE NORTH AMERICA 74LV10 N 74LV10 D 74LV10 DB 74LV10 PW NORTH AMERICA 74LV10 N 74LV10 D 74LV10 DB 74LV10PW DH PKG. DWG. # SOT27-1 SOT108-1 SOT337-1 SOT402-1 PIN DESCRIPTION PIN NUMBER 1, 3, 9 2, 4, 10 7 12, 6, 8 13, 5, 11 14 SYMBOL 1A – 3A 1B – 3B GND 1Y – 3Y 1C – 3C VCC NAME AND FUNCTION Data inputs Data inputs Ground (0 V) Data outputs Data inputs Positive supply voltage FUNCTION TABLE INPUTS nA L L L L H H H H NOTES: H = HIGH voltage level L = LOW voltage level nB L L H H L L H H nC L H L H L H L H OUTPUTS nY H H H H H H H L 1998 Apr 20 2 853–1919 19256 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 PIN CONFIGURATION 1A 1B 2A 2B 2C 2Y GND 1 2 3 4 5 6 7 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 8 3A LOGIC SYMBOL 1 2 13 1A 1B 1C 1Y 12 3 4 5 2A 2B 2C 2Y 6 9 3Y 10 11 3A 3B 3C 3Y 8 SV00416 SV00417 LOGIC SYMBOL (IEEE/IEC) 1 2 13 3 4 5 9 10 11 LOGIC DIAGRAM (ONE GATE) & 12 A & 6 B C 8 Y & SV00419 SV00418 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage Input voltage Output voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V CONDITIONS See Note1 MIN 1.0 0 0 –40 –40 – – – – – – TYP. 3.3 – – MAX 3.6 VCC VCC +85 +125 500 200 100 UNIT V V V °C ns/V Input rise and fall times NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V. 1998 Apr 20 3 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC "IIK "IOK "IO "IGND, "ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current – standard outputs DC VCC or GND current for types with – standard outputs Storage temperature range Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI < –0.5 or VI > VCC + 0.5V VO < –0.5 or VO > VCC + 0.5V –0.5V < VO < VCC + 0.5V CONDITIONS RATING –0.5 to +4.6 20 50 25 UNIT V mA mA mA 50 –65 to +150 750 500 400 mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2 V VIH HIGH l level I l Input t voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V VIL LOW l l Input t level I voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA VO OH HIGH level output voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA VCC = 2.7 V; VI = VIH or VIL; –IO = 100µA VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA VOH HIGH level output voltage; STANDARD outputs VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA VCC = 1.2 V; VI = VIH or VIL; IO = 100µA VO OL LOW level output voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; IO = 100µA VCC = 2.7 V; VI = VIH or VIL; IO = 100µA VCC = 3.0 V; VI = VIH or VIL; IO = 100µA VOL LOW level output voltage; STANDARD outputs Input leakage current Quiescent supply current; SSI VCC = 3.0 V; VI = VIH or VIL; IO = 6mA 1.8 2.5 2.8 2.40 1.2 2.0 2.7 3.0 2.82 0 0 0 0 0.25 0.2 0.2 0.2 0.40 0.2 0.2 0.2 0.50 V V 1.8 2.5 2.8 2.20 V V 0.9 1.4 2.0 0.3 0.6 0.8 -40°C to +85°C TYP1 MAX -40°C to +125°C MIN 0.9 1.4 2.0 0.3 0.6 0.8 V V MAX UNIT II ICC VCC = 3.6 V; VI = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 1.0 20.0 1.0 40 µA µA 1998 Apr 20 4 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 DC ELECTRICAL CHARACTERISTICS (Continued) Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER Additional quiescent supply current per input TEST CONDITIONS MIN ∆ICC VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V -40°C to +85°C TYP1 MAX 500 -40°C to +125°C MIN MAX 850 µA UNIT NOTE: 1. All typical values are measured at Tamb = 25°C. AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 tPHL/PLH / Propagation delay g y nA, nB, nC to nY Figure Figure 1, 2 2.0 2.7 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C. 2. Typical values are measured at VCC = 3.3 V. MIN LIMITS –40 to +85 °C TYP1 55 19 14 102 36 26 21 44 33 26 ns MAX –40 to +125 °C MIN MAX UNIT AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. VI nA, nB, nC INPUT GND t PHL VOH nY OUTPUT VOL VM t PLH VM TEST CIRCUIT VCC VI PULSE GENERATOR RT D.U.T. VO 50pF CL RL = 1k Test Circuit for switching times DEFINITIONS SV00420 RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. TEST tPLH/tPHL VCC < 2.7V 2.7–3.6V VI VCC 2.7V Figure 1. Input (nA, nB, nC) to output (nY) propagation delays. SV00901 Figure 2. Load circuitry for switching times. 1998 Apr 20 5 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 1998 Apr 20 6 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 1998 Apr 20 7 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 1998 Apr 20 8 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 1998 Apr 20 9 Philips Semiconductors Product specification Triple 3-input NAND gate 74LV10 DEFINITIONS Data Sheet Identification Objective Specification Product Status Formative or in Design Definition This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Preliminary Specification Preproduction Product Product Specification Full Production Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04407 Philips Semiconductors 1998 Apr 20 10