74LV161PWDH

INTEGRATED CIRCUITS 74LV161 Presettable synchronous 4-bit binary counter; asynchronous reset Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook 1997 May 15 Philips Semiconductors Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, • Asynchronous reset • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive-edge triggered clock • Output capability: standard • ICC category: MSI Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV161 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT161. The 74LV161 is a synchronous presettable binary counter which features an internal look-head carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascading stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: 1 f max + tp (max) (CP to TC) ) t su(CEP to CP) QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER Propagation delay CP to Qn CP to TC MR to Qn MR to TC CET to TC Maximum clock frequency Input capacitance Power dissipation capacitance per gate VI = GND to VCC1 CONDITIONS CL = 15 pF; VCC = 3.3 V TYPICAL 15 18 15 17 9 77 3.5 25 UNIT tPHL/tPLH ns fmax CI CPD MHz pF pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 fi ) (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. (CL ORDERING INFORMATION PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C OUTSIDE NORTH AMERICA 74LV161 N 74LV161 D 74LV161 DB 74LV161 PW NORTH AMERICA 74LV161 N 74LV161 D 74LV161 DB 74LV161PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1 1997 May 15 2 853–1917 18039 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 PIN CONFIGURATION MR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC TC Q0 Q1 Q2 Q3 CET LOGIC SYMBOL 15 TC 3 D0 Q0 14 4 D1 Q1 13 5 D2 Q2 12 6 D3 Q3 11 9 PE PE CEP CET CP MR SV00569 7 10 2 1 PIN DESCRIPTION PIN NUMBER 1 2 3, 4, 5, 6 7 8 9 10 14, 13, 12, 11 15 16 SYMBOL MR CP D0 to D3 CEP GND PE CET Q0 to Q3 TC VCC FUNCTION Asynchronous master reset (active LOW) 3 4 5 6 D3 SV00570 FUNCTIONAL DIAGRAM Clock input (LOW-to-HIGH, edge-triggered) 9 PE D0 D1 D2 Data inputs Count enable inputs Ground (0 V) Parallel enable input (active LOW) Count enable carry input Flip-flop outputs 2 CP 1 MR 10 CET 7 CEP PARALLEL LOAD CIRCUITRY TC BINARY COUNTER 15 Q0 Q1 Q2 13 12 Q3 11 Terminal count output Positive supply voltage 14 SV00572 LOGIC SYMBOL (IEEE/IEC) 1 9 7 10 2 3 1, 2D 4 5 6 CTR4 R M1 G3 G4 C2/1,3,4+ 14 13 12 11 15 4CT = 15 SV00571 1997 May 15 3 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 FUNCTION TABLE INPUTS OPERATING MODES MODES Reset (clear) Parallel load load Count Hold (do nothing) (do nothing) MR L H H H H H CP X ↑ ↑ ↑ X X CEP X X X h I X CET X X X h X I PE X I I h h h Dn X I h X X X Qn L L H Count qn qn OUTPUTS TC L L * * * L NOTES: * = The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH) H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = don’t care ↑ = LOW-to-HIGH clock transition STATE DIAGRAM 0 1 2 3 4 TYPICAL TIMING SEQUENCE MR PE 15 5 D0 D1 14 6 D2 D3 13 7 CP CEP 12 11 10 9 8 CET SV00573 Q0 Q1 Q2 Q3 TC 12 reset 13 14 15 0 1 2 inhibit preset count Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, on and two; inhibit. SV00574 1997 May 15 4 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 LOGIC DIAGRAM D0 D1 D2 D3 CET CEP PE FF0 Q D FF1 Q D CP FF2 Q D CP FF3 Q D CP CP CP RD Q RD Q RD Q RD Q MR Q0 Q1 Q2 Q3 TC SV00575 1997 May 15 5 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC "IIK "IOK "IO PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current – standard outputs – bus driver outputs DC VCC or GND current for types with – standard outputs – bus driver outputs Storage temperature range Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI < –0.5 or VI > VCC + 0.5V VO < –0.5 or VO > VCC + 0.5V –0.5V < VO < VCC + 0.5V CONDITIONS RATING –0.5 to +4.6 20 50 25 35 50 70 –65 to +150 750 500 400 UNIT V mA mA mA "IGND, "ICC Tstg PTOT mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER DC supply voltage Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times except for Schmitt-trigger inputs See DC and AC characteristics per device VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V CONDITIONS See Note 1 MIN 1.0 0 0 –40 –40 – – – – – – TYP 3.3 – – MAX 3.6 VCC VCC +85 +125 500 200 100 UNIT V V V °C ns/V NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V. 1997 May 15 6 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2 V VIH HIGH l level I l Input t voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V VIL LOW l level I l Input t voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA VO OH HIGH level output voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA VCC = 2.7 V; VI = VIH or VIL; –IO = 100µA VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA VOH HIGH level output voltage; STANDARD outputs HIGH level output voltage; BUS driver outputs VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA 1.8 2.5 2.8 2.40 1.2 2.0 2.7 3.0 2.82 1.8 2.5 2.8 2.20 V V 0.9 1.4 2.0 0.3 0.6 0.8 -40°C to +85°C TYP1 MAX -40°C to +125°C MIN 0.9 1.4 2.0 0.3 0.6 0.8 V V MAX UNIT VOH VCC = 3.0 V; VI = VIH or VIL; –IO = 8mA VCC = 1.2 V; VI = VIH or VIL; IO = 100µA 2.40 2.82 0 0 0 0 0.25 0.2 0.2 0.2 0.40 2.20 V VO OL LOW level output voltage; all outputs VCC = 2.0 V; VI = VIH or VIL; IO = 100µA VCC = 2.7 V; VI = VIH or VIL; IO = 100µA VCC = 3.0 V; VI = VIH or VIL; IO = 100µA 0.2 0.2 0.2 0.50 V VOL LOW level output voltage; STANDARD outputs LOW level output voltage; BUS driver outputs Input leakage current 3-State output OFF-state current Quiescent supply current; SSI Quiescent supply current; flip-flops Quiescent supply current; MSI Quiescent supply current; LSI VCC = 3.0 V; VI = VIH or VIL; IO = 6mA V VOL II IOZ VCC = 3.0 V; VI = VIH or VIL; IO = 8mA VCC = 3.6 V; VI = VCC or GND VCC = 3.6 V; VI = VIH or VIL; VO = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 3.6 V; VI = VCC or GND; IO = 0 VCC = 3.6 V; VI = VCC or GND; IO = 0 VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 0.20 0.40 1.0 5 20.0 20.0 20.0 500 500 0.50 1.0 10 40 V µA µA µA 80 160 µA 1000 850 µA ICC ∆ICC Additional quiescent supply current per input NOTE: 1. All typical values are measured at Tamb = 25°C. 1997 May 15 7 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 tPHL/tPLH Propagation delay g y CP to Qn Figures 1, 6 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH Propagation delay g y CP to TC Figures 1, 6 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH Propagation delay g y MR to Qn Figures 2, 6 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH Propagation delay g y MR to TC Figures 2, 6 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH Propagation delay g y CET to TC Figures 1, 6 2.0 2.7 3.0 to 3.6 2.0 tw Clock pulse width Clock pulse width or LOW HIGH or LOW Figures 2, 6 2.7 3.0 to 3.6 2.0 tw Master reset width; Master reset width; LOW Figures 2, 6 2.7 3.0 to 3.6 1.2 trem Removal time MR to CP Figures 2, 6 2.0 2.7 3.0 to 3.6 1.2 tsu Set-up time Dn to CP Figures 4, 6 2.0 2.7 3.0 to 3.6 1.2 tsu Set-up time PE to CP Figures 4, 6 2.0 2.7 3.0 to 3.6 1.2 tsu Set-up time CEP, CET to CP Figures 5, 6 2.0 2.7 3.0 to 3.6 22 16 13 22 16 13 22 16 13 22 16 13 34 25 20 34 25 20 MIN LIMITS –40 to +85 °C TYP1 95 32 24 182 115 39 29 222 95 32 24 182 105 36 26 202 55 19 14 102 10 8 62 14 10 82 25 9 6 52 25 9 6 52 30 10 8 62 30 10 8 62 26 19 15 ns 26 19 15 ns 26 19 15 ns 26 19 15 ns 36 26 21 41 30 24 41 30 24 ns ns 44 33 26 ns 68 50 40 82 60 48 ns 61 45 36 75 55 44 ns 75 55 44 90 66 53 ns 61 45 36 75 55 44 ns MAX –40 to +125 °C MIN MAX UNIT 1997 May 15 8 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 AC ELECTRICAL CHARACTERISTICS (Continued) SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 th Hold time PE CEP CET to Dn, PE, CEP, CET to CP Figures 4 – 6 2.0 2.7 3.0 to 3.6 2.0 fmax Maximum clock Maximum clock frequency pulse frequency Figures 1, 6 2.7 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. 0 0 0 14 19 24 MIN LIMITS –40 to +85 °C TYP1 –35 –12 –9 –72 40 58 70 0 0 0 12 16 20 MHz ns MAX –40 to +125 °C MIN MAX UNIT AC WAVEFORMS VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V; VOL and VOH are the typical output voltage drop that occur with the output load. 1/fmax VI CP INPUT GND tW tPHL VOH Qn, TC OUTPUT VOL VM TC OUTPUT VOL VM tPLH VOH VM CET INPUT GND tPLH tPHL VI VM SV00578 SV00576 Figure 3. Input (CET) to output (TC) propagation delays. Figure 1. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width and the maximum clock frequency. VI PE INPUT VM VI GND MR INPUT GND tW trem VI GND CP INPUT GND tPHL VOH Qn , TC OUTPUT VOL VM VM VI Dn INPUT GND The shaded areas indicate when the input is permitted to change for predictable output performance. VM tsu th tsu th CP INPUT VM VM VI tsu th tsu th SV00579 SV00577 Figure 2. Master reset (MR) pulse width, the master reset to output (Qn, TC) propagation delays and the master reset to clock (CP) removal times. Figure 4. Set-up and hold times for input (Dn) and parallel enable input (PE). 1997 May 15 9 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 VI CEP, CET INPUT GND VI CP INPUT GND The shaded areas indicate when the input is permitted to change for predictable output performance. VM VM tsu th tsu th SV00580 Figure 5. CEP and CET set-up and hold times. TEST CIRCUIT VCC S1 2 x VCC Open GND VI PULSE GENERATOR RT D.U.T. VO RL CL RL Test Circuit for switching times SWITCH POSITION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND DEFINITIONS VCC < 2.7V 2.7–3.6V VI VCC 2.7V RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. SV00776 Figure 6. Load circuitry for switching times. 1997 May 15 10 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 1997 May 15 11 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 1997 May 15 12 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 1997 May 15 13 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 1997 May 15 14 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 NOTES 1997 May 15 15 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter; asynchronous reset 74LV161 DEFINITIONS Data Sheet Identification Objective Specification Product Status Formative or in Design Definition This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Preliminary Specification Preproduction Product Product Specification Full Production Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 1997 May 15 16