74LV4040PW

INTEGRATED CIRCUITS 74LV4040 12-stage binary ripple counter Product specification IC24 Data Handbook 1998 Jun 23 Philips Semiconductors Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 FEATURES • Optimized for Low Voltage applications: 1.0 to 5.5V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, • Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, • Frequency dividing circuits • Time delay circuits • Control counters • Output capability: standard • ICC category: MSI QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL PARAMETER Propagation delay CP to Q0 Qn to Qn+1 MR to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per gate Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV4040 is a low–voltage Si–gate CMOS device and is pin and function compatible with 74HC/HCT4040. The 74LV4040 is a 12-stage binary ripple counter with a click input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q0 to Q11). The counter is advanced on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. CONDITIONS CL = 15pF VCC = 3.3V TYPICAL 12 7 16 100 3.5 UNIT tPHL/tPLH fmax CI CPD ns MHz pF pF Notes 1 and 2 30 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 x fi )S (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2. The condition is VI = GND to VCC ORDERING INFORMATION PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C OUTSIDE NORTH AMERICA 74LV4040 N 74LV4040 D 74LV4040 DB 74LV4040 PW NORTH AMERICA 74LV4040 N 74LV4040 D 74LV4040 DB 74LV4040PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1 1998 Jun 23 2 853-2075 19619 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 PIN CONFIGURATION LOGIC SYMBOL Q0 9 7 6 5 3 2 4 13 12 14 15 1 Q11 Q5 Q4 Q6 Q3 Q2 Q1 GND 1 2 3 4 5 6 7 8 16 VCC 15 Q10 14 Q9 13 Q7 12 Q8 11 MR 10 CP 9 Q0 11 MR 10 CP Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 SV00316 SV00317 Figure 1. Pin configuration Figure 3. Logic symbol PIN DESCRIPTION PIN NUMBER 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 8 10 11 16 SYMBOL FUNCTION FUNCTIONAL DIAGRAM Q0 to Q11 GND CP MR VCC Parallel outputs Ground (0V) Clock input (HIGH-to-LOW, edgetriggered) Master reset input (active HIGH) Positive supply voltage 10 11 CP T 12-STAGE COUNTER MR CD Q0 Q1 9 7 Q2 Q3 5 5 Q4 3 Q5 2 Q6 4 Q7 13 Q8 12 Q9 14 Q10 Q11 15 1 LOGIC SYMBOL (IEEE/IEC) SV00319 CTR12 10 11 + CT=0 0 9 7 5 5 3 2 CT 4 13 12 14 15 11 1 MR CP FF0 Q T Q RD T Q RD FF3 Q FF11 Q T Q RD Figure 4. Functional diagram LOGIC DIAGRAM SV00318 Figure 2. IEC Logic symbol Q0 Q1 Q11 SV00320 Figure 5. Logic diagram 1998 Jun 23 3 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 1 CP INPUT 2 4 8 16 32 64 128 256 512 1.024 2.048 4.096 MR INPUT Q0 OUTPUT Q1 OUTPUT Q2 OUTPUT Q3 OUTPUT Q4 OUTPUT Q5 OUTPUT Q6 OUTPUT Q7 OUTPUT Q8 OUTPUT Q9 OUTPUT Q10 OUTPUT Q11 OUTPUT SV00310 Figure 6. Timing diagram FUNCTION TABLE INPUTS CP ° ± X MR L L H OUTPUTS Q0, Q3 to Q13 no change count L NOTES: H = HIGH voltage level L = LOW voltage level X = Don’t care ° = LOW -to-HIGH clock transition ± = HIGH-to-LOW clock transition 1998 Jun 23 4 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC ±IIK ±IOK ±IO ±IGND, ±ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current – standard outputs DC VCC or GND current for types with –standard outputs Storage temperature range Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI < –0.5 or VI > VCC + 0.5V VO < –0.5 or VO > VCC + 0.5V –0.5V < VO < VCC + 0.5V CONDITIONS RATING –0.5 to +7.0 20 50 25 50 –65 to +150 750 500 400 UNIT V mA mA mA mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V PARAMETER DC supply voltage CONDITIONS See Note1 MIN 1.0 0 0 –40 –40 – – – – – – – – TYP. 3.3 – – MAX 5.5 VCC VCC +85 +125 500 200 100 50 UNIT V V V °C tr, tf ns/V NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1998 Jun 23 5 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 DC CHARACTERISTICS FOR THE LV FAMILY Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2V VIH HIGH level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5V VCC = 1.2V VIL LOW level Input voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 4.5 to 5.5 VCC = 1.2V; VI = VIH or VIL; –IO = 100µA VOH HIGH level output level output voltage; all outputs all out VCC = 2.0V; VI = VIH or VIL; –IO = 100µA VCC = 2.7V; VI = VIH or VIL; –IO = 100µA VCC = 3.0V; VI = VIH or VIL; –IO = 100µA VCC = 4.5V; VI = VIH or VIL; –IO = 100µA VOH HIGH level output voltage; g STANDARD outputs VCC = 3.0V; VI = VIH or VIL; –IO = 6mA VCC = 4.5V; VI = VIH or VIL; –IO = 12mA VCC = 1.2V; VI = VIH or VIL; IO = 100µA VOL LOW level output level output all out voltage; all outputs VCC = 2.0V; VI = VIH or VIL; IO = 100µA VCC = 2.7V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 100µA VCC = 4.5V; VI = VIH or VIL; IO = 100µA VOL LOW level output voltage; g STANDARD outputs Input leakage current Quiescent supply current; MSI Additional quiescent supply current per input VCC = 3.0V; VI = VIH or VIL; IO = 6mA VCC = 4.5V; VI = VIH or VIL; IO = 12mA VCC = 5.5V; VI = VCC or GND VCC = 5.5V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC –0.6V 1.8 2.5 2.8 4.3 2.40 3.60 1.2 2.0 2.7 3.0 4.5 2.82 4.20 0 0 0 0 0 0.25 0.35 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20.0 500 0.2 0.2 0.2 0.2 0.50 V 0.65 1.0 160 850 µA µA µA V 1.8 2.5 2.8 4.3 2.20 V 3.50 V 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC -40°C to +85°C TYP1 MAX -40°C to +125°C MIN 0.9 1.4 2.0 0.7*VCC 0.3 0.6 0.8 0.3*VCC V V MAX UNIT II ICC ∆ICC NOTE: 1. All typical values are measured at Tamb = 25°C. 1998 Jun 23 6 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 500W SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 tPHL/tPLH Propagation delay Propagation delay CP to Q0 to Figure 7, 9 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tPHL/tPLH Propagation delay Propagation delay to Qn to Qn+1 Figure 7, 9 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 tPHL Propagation delay Propagation delay to MR to Qn Figure 8, 9 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tW Clock pulse width HIGH to LOW Figure 7 2.7 3.0 to 3.6 4.5 to 5.5 2.0 tW Master reset pulse width HIGH Figure 8 2.7 3.0 to 3.6 4.5 to 5.5 1.2 2.0 trem Removal time Removal time MR to CP to CP Figure 8 2.7 3.0 to 3.6 4.5 to 5.5 2.0 fmax Maximum clock pulse frequency Figure 7 2.7 3.0 to 3.6 4.5 to 5.5 NOTES: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 3. Typical value measured at VCC = 5.0V. MIN – – – – – – – – – – – – – – – 35 25 20 15 35 25 20 15 – 22 16 13 10 14 19 24 36 LIMITS –40 to +85 °C TYP1 60 27 19 162 13 40 18 13 112 73 55 27 19 162 113 7 5 42 33 11 9 82 73 10 5 4 32 23 60 76 942 1123 MAX – 43 31 26 17 – 29 21 18 12 – 44 31 26 17 – – – – – – – – – – – – – – – – – LIMITS –40 to +125 °C MIN – – – – – – – – – – – – – – – 41 30 24 18 41 30 24 18 – 26 19 15 12 12 16 20 30 MAX – 54 38 32 22 – 54 38 32 22 – 54 38 32 22 54 – – – – – – – – – – – – – – – – MHz ns ns ns ns ns ns UNIT 1998 Jun 23 7 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 AC WAVEFORMS VM = 1.5V at VCC w 2.7V v 3.6V VM = 0.5V * VCC at VCC t 2.7V and w 4.5V VOL and VOH are the typical output voltage drop that occur with the output load. TEST CIRCUIT VCC VI 1/fmax VI RT CP INPUT GND tW tPHL VOH Qn OUTPUT VOL VM tPLH VM PULSE GENERATOR D.U.T. VO 50pF CL RL = 1k Test Circuit for switching times DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. TEST VCC < 2.7V 2.7–3.6V VI VCC 2.7V SV00322 Figure 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency tPLH/tPHL SV00901 Figure 9.Load circuitry for switching times VI MR INPUT GND tW trem VI CP INPUT GND tPHL VOH Qn OUTPUT GND SV00908 Figure 8. Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time 1998 Jun 23 8 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 1998 Jun 23 9 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 1998 Jun 23 10 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 1998 Jun 23 11 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 1998 Jun 23 12 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 NOTES 1998 Jun 23 13 Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04458 Philips Semiconductors yyyy mmm dd 14