74LV4316N

INTEGRATED CIRCUITS 74LV4316 Quad bilateral switches Product specification Supersedes data of 1994 Dec 01 IC24 Data Handbook 1998 Jun 23 Philips Semiconductors Philips Semiconductors Product specification Quad bilateral switches 74LV4316 FEATURES DESCRIPTION The 74LV4316 is a low-voltage CMOS device that is pin and function compatible with 74HC/HCT4316. The 74LV4316 has four independent analog switches. Each switch has two input/output terminals (nY, nZ) and an active HIGH select input (nS). When the enable input (E) is HIGH, all four analog switches are turned off. Current through a switch will not cause additional VCC current provided the voltage at the terminals of the switch is maintained within the supply voltage range; VCC > (VY, VZ) > VEE. Inputs nY and nZ are electrically equivalent terminals. VCC and GND are the supply voltage pins for the digital control inputs (E and nS). The VCC to GND ranges are 1.0 to 6.0 V. The analog inputs/outputs (nY and nZ) can swing between VCC as a positive limit and VEE as a negative limit. VCC – VEE may not exceed 6.0 V. • Optimized for Low Voltage applications: 1.0V to 6.0V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Low typ “ON” resistance: • Logic level translation: to enable 3V logic to communicate • Typical “break before make” built in • Output capability: non-standard • ICC category: MSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf v 2.5 ns SYMBOL tPZH/tPZL PARAMETER Turn “ON” time: E to VOS nS to VOS Turn “OFF” time: E to VOS nS to VOS Input capacitance Power dissipation capacitance per switch Maximum switch capacitance with "3V analog signals 80W at VCC – VEE = 4.5V 120W at VCC – VEE = 3.0V 295W at VCC – VEE = 2.0V CONDITIONS CL = 15pF RL = 1KW VCC= 3.3V TYPICAL 19 UNIT ns tPHZ/tPLZ CI CPD CS 20 3.5 Notes 1, 2 13 5 ns pF pF pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC = supply voltage in V: (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C OUTSIDE NORTH AMERICA 74LV4316 N 74LV4316 D 74LV4316 DB 74LV4316 PW NORTH AMERICA 74LV4316 N 74LV4316 D 74LV4316 DB 74LV4316PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1 PIN CONFIGURATION 1Z 1Y 2Y 2Z 2S 3S E 1 2 3 4 5 6 7 16 VCC 15 1S 14 4S 13 4Z 12 4Y 11 3Y 10 3Z 9 VEE PIN DESCRIPTION PIN NUMBER 1, 4, 10, 13 2, 3, 11, 12 7 8 9 15, 5, 6, 14 16 SYMBOL 1Z – 4Z 1Y – 4Y E GND VEE 1S – 4S VCC FUNCTION Independent inputs/outputs Independent inputs/outputs Enable input (active LOW) Ground (0V) Negative supply voltage Select inputs (active HIGH) Positive supply voltage GND 8 SV01650 1998 Jun 23 2 853-2079 19619 Philips Semiconductors Product specification Quad bilateral switches 74LV4316 IEC LOGIC SYMBOL 7 G1 7 G1 FUNCTIONAL DIAGRAM 16 V CC 1Z 1 1 2 15 # 3 5# 11 6# 12 14 # 1 2 15 # 2 1X2 2 15 1S 1Y 2Z 2 4 4 3 5# 4 5 2S 2Y 10 6 3S 3Y LOGIC LEVEL CONVERSION AND CONTROL 3Z 3 10 10 11 6# 11 13 13 12 14 # 13 14 4S 4Z 4Y (a) (b) E GND 8 V EE 9 12 SV01658 7 SV01653 LOGIC SYMBOL 1Y 15 1S 1Z 2Y 5 2S 2Z 3Y 6 3S 3Z 4Y 14 4S 4Z 13 10 12 4 11 1 3 2 7 E SV01651 SCHEMATIC DIAGRAM (ONE SWITCH) nY to other switches VCC VEE E LOGIC LEVEL CONVERSION nS LOGIC LEVEL CONVERSION VCC VEE nZ SV01654 1998 Jun 23 3 Philips Semiconductors Product specification Quad bilateral switches 74LV4316 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb Input voltage Output voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V PARAMETER DC supply voltage CONDITIONS See Note 1 MIN 1.0 0 0 –40 –40 – – – – – – – – TYP 3.3 – – MAX 6.0 VCC VCC +85 +125 500 200 100 50 UNIT V V V °C tr, tf Input rise and fall times ns/V NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC "IIK "IOK "IO Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC switch current Storage temperature range Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI < –0.5 or VI > VCC + 0.5V VO < –0.5 or VO > VCC + 0.5V –0.5V < VO < VCC + 0.5V CONDITIONS RATING –0.5 to +7.0 20 20 25 –65 to +150 750 500 400 UNIT V mA mA mA °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jun 23 4 Philips Semiconductors Product specification Quad bilateral switches 74LV4316 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2 V VIH HIGH level Input level Input voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 4.5 V VCC = 6.0 V VCC = 1.2 V VIL LOW level Input level Input voltage VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 4.5 V VCC = 6.0 V ±II ±IS Input leakage current Analog switch OFF-state current per channel Analog switch ON-state current per channel Quiescent supply current Additional quiescent supply current per input VCC = 3.6 V; VI = VCC or GND VCC = 6.0 V; VI = VCC or GND VCC = 3.6 V; VI = VIH or VIL VCC = 6.0 V; VI = VIH or VIL VCC = 3.6 V; VI = VIH or VIL VCC = 6.0 V; VI = VIH or VIL VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 6.0V; VI = VCC or GND; IO = 0 VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V VCC = 1.2 V; VI = VIH or VIL VCC = 2.0 V; VI = VIH or VIL VCC = 2.7 V; VI = VIH or VIL VCC = 3.0 to 3.6 V; VI = VIH or VIL VCC = 4.5 V; VI = VIH or VIL VCC = 6.0 V; VI = VIH or VIL VCC = 1.2 V; VI = VIH or VIL VCC = 2.0 V; VI = VIH or VIL VCC = 2.7 V; VI = VIH or VIL VCC = 3.0 to 3.6 V; VI = VIH or VIL VCC = 4.5 V; VI = VIH or VIL VCC = 6.0 V; VI = VIH or VIL VCC = 1.2 V; VI = VIH or VIL VCC = 2.0 V; VI = VIH or VIL VCC = 2.7 V; VI = VIH or VIL VCC = 3.0 to 3.6 V; VI = VIH or VIL VCC = 4.5 V; VI = VIH or VIL VCC = 6.0 V; VI = VIH or VIL VCC = 1.2 V; VI = VIH or VIL VCC = 2.0 V; VI = VIH or VIL VCC = 2.7 V; VI = VIH or VIL VCC = 3.0 to 3.6 V; VI = VIH or VIL VCC = 4.5 V; VI = VIH or VIL VCC = 6.0 V; VI = VIH or VIL 295 120 110 80 70 225 110 85 55 40 35 250 120 75 60 45 40 – 5 4 4 3 2 0.90 1.40 2.00 3.15 4.20 0.30 0.60 0.80 1.35 1.80 1.0 2.0 1.0 2.0 1.0 2.0 20 40 500 – 860 300 270 200 180 – 240 150 135 100 90 – 270 170 155 115 105 -40°C to +85°C TYP1 MAX -40°C to +125°C MIN 0.90 1.4 2.0 3.15 4.20 0.30 0.60 0.80 1.35 1.80 1.0 2.0 1.0 2.0 1.0 2.0 40 80 850 – 990 360 325 240 215 – 290 180 180 120 110 – 325 205 180 135 120 µA µA V V MAX UNIT ±IS ICC ∆ICC µA µA µA RON ON-resistance (peak) Ω RON ON-resistance (rail) Ω RON ON-resistance (rail) Ω ∆RON Maximum variation of ON-resistance between any two channels Ω NOTE: 1. All typical values are measured at Tamb = 25°C. 2. At supply voltage approaching 1.2V, the analog switch ON-resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital signals only, when using these supply voltages. 1998 Jun 23 5 Philips Semiconductors Product specification Quad bilateral switches 74LV4316 HIGH (from select inputs) V LOW (from select inputs) nY nY nZ A I V VI = VCC or VEE nZ A Vis = 0 to VCC – VEE is EE VO= VEE or VCC V EE SV01655 SV01656 Figure 1. Test circuit for measuring ON-resistance (Ron). Figure 2. Test circuit for measuring OFF-state current. 300 HIGH (from select inputs) RON (W) 250 200 nY A nZ V O 150 VCC = 3.0 V 100 50 VCC = 4.5 V VEE 0 0 1.2 2.4 3.6 Vis (V) 4.8 VCC = 2.0 V (open circuit) VI = VCC or VEE SV01657 Figure 3. Test circuit for measuring ON-state current. SV01658 Figure 4. Typical ON-resistance (RON) as a function of input voltage (Vis) for Vis = 0 to VCC – VEE. 1998 Jun 23 6 Philips Semiconductors Product specification Quad bilateral switches 74LV4316 AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5ns; CL = 50pF LIMITS SYMBOL PARAMETER MIN –40 to +85 °C TYP1 30 10 tPHL/tPLH Propagation delay g y Vis to Vos 8 6* 5 4 110 37 28 212 19 15 95 32 24 182 16 12 105 37 28 222 20 16 90 32 24 192 17 14 19 14 11 9 7 70 51 41 35 27 61 45 36 31 23 68 51 41 35 28 59 44 36 31 24 24 18 14 12 9 85 63 50 43 33 75 55 44 37 29 80 59 48 41 32 70 52 42 36 28 ns MAX –40 to +125 °C MIN MAX UNIT VCC(V) 1.2 2.0 2.7 3.0 to 3.6 4.5 6.0 1.2 2.0 2.7 3.0 to 3.6 4.5 6.0 1.2 2.0 2.7 3.0 to 3.6 4.5 6.0 1.2 2.0 2.7 3.0 to 3.6 4.5 6.0 1.2 2.0 2.7 3.0 to 3.6 4.5 6.0 RL = ∞ ; CL = 50 pF 50 Figure 12 g CONDITION OTHER tPZH/tPZL Turn-on time E to Vos ns RL = 1 kW; CL = 50 pF 50 Figures 13 a d 14 gu es 3 and tPZH/tPZL Turn-on time nS to Vos ns RL = 1 kW; CL = 50 pF 50 Figures 13 a d 14 gu es 3 and tPHZ/tPLZ Turn-off time E to Vos ns RL = 1 kW; CL = 50 pF 50 Figures 13 a d 14 gu es 3 and tPHZ/tPLZ Turn-off time nS to Vos ns RL = 1 kW; CL = 50 pF 50 Figures 13 a d 14 gu es 3 and NOTES: 1. All typical values are measured at Tamb = 25°C. 2. All typical values are measured at VCC = 3.3V 1998 Jun 23 7 Philips Semiconductors Product specification Quad bilateral switches 74LV4316 ADDITIONAL AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5ns; CL = 50pF SYMBOL PARAMETER Sine-wave distortion Sine-wave distortion f = 1 kHz kHz Sine-wave distortion Sine-wave distortion f = 10 kHz 10 kHz Switch “OFF” signal feed through OFF signal feed through Crosstalk between any two switches between any two switches V( ) (p–p) fmax CS Crosstalk voltage between enable or address g input to any switch (peak-to-peak value) Minimum frequency response (–3 dB) frequency res (–3 dB) Maximum switch capacitance TYP 0.80 0.40 2.40 1.20 –50 –50 –60 –60 110 mV 220 180 200 5 mHz pF 6.0 3.0 6.0 Note 2 UNIT % % dB dB VCC (V) 3.0 6.0 3.0 6.0 3.0 6.0 3.0 6.0 3.0 VIS(P–P) (V) 2.75 5.50 2.75 5.50 Note 1 Note 1 CONDITIONS RL = 10 kW; CL = 50 pF Figure 10 RL = 10 kW; CL = 50 pF Figure 10 RL = 600 kW; CL = 50 pF; f=1 MHz Figures 5 and 11 RL = 600 kW; CL = 50 pF; f=1 MHz Figure 7 RL = 600 kW; CL = 50 pF; f=1 MHz (nS or E, square wave between VCC or square wave between and GND, Tr = tf = 6 ns) Figure 8 RL = 50 kW; CL = 50 pF Figures 6 and 9 GENERAL NOTES: Vis is the input voltage at nY or nZ terminal, whichever is assigned as an input. Vos is the output voltage at nY or nZ terminal, whichever is assigned as an output. NOTES: 1. Adjust input voltage Vis is 0 dBm level (0 dBm = 1 mW into 600 W). 2. Adjust input voltage Vis is 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 W). 0 (dB) 5 (dB) –50 0 –100 10 10 2 10 3 10 4 f (kHz) 10 5 10 6 – 5 10 10 2 10 3 10 4 10 5 f (kHz) 10 6 SV01635 SV01664 Figure 5. Typical switch “OFF” signal feed-through as a function of frequency. NOTES TO FIGURES 5 AND 6: Test conditions: VCC = 3.0 V; GND = 0 V; RL = 50 W; RSOURCE = 1kW. VCC Figure 6. Typical frequency response. VCC VCC 0.1 mF V is RL 2RL nY/nZ nZ/nY nY/nZ 2RL 2RL nZ/nY Vos channel ON 2RL CL GND RL channel OFF 2RL CL dB GND (b) (a) SV01665 Figure 7. Test circuit for measuring crosstalk between any two switches. (a) channel ON condition; (b) channel OFF condition. 1998 Jun 23 8 Philips Semiconductors Product specification Quad bilateral switches 74LV4316 VCC 2R L nY/nZ nS or E VCC 2R L nZ/nY 0.1 mF ~ Vis sine-wave 2R L CL oscilloscope channel ON GND VEE nY/nZ VCC 2RL DUT 2R L nZ/nY Vos 2RL CL dB GND SV01667 SV01666 Figure 8. Test circuit for measuring crosstalk between control and any switch. NOTE TO FIGURE 8: The crosstalk is defined as follows (oscilloscope output): Figure 9. Test circuit for measuring minimum frequency response. NOTE TO FIGURE 9: Adjust input voltage to obtain 0 dBm at VOS when Fin = 1 MHz. After set-up frequency of fin is increased to obtain a reading of –3 dB at VOS. V(p – p) SV01642 VCC VCC 10 mF nY/nZ 2RL nZ/nY Vos 2RL CL distortion meter GND V is 0.1 mF Yn/Z fin ≅ 1 kHz sine-wave 2RL Z/Yn VOS channel ON channel OFF 2RL CL dB SV01668 GND Figure 10. Test circuit for measuring sine-wave distortion. SV01639 Figure 11. Test circuit for measuring switch “OFF” signal feed-through. 1998 Jun 23 9 Philips Semiconductors Product specification Quad bilateral switches 74LV4316 WAVEFORMS VM = 1.5 V at 2.7 V ≤ VCC ≤ 3.6 V VM = 0.5 × VCC at 2.7 V > VCC > 3.6 V VOL and VOH are the typical output voltage drop that occur with the output load Vx = VOL + 0.3 V at 2.7 V ≤ VCC ≤ 3.6 V VX = VOL + 0.1 × VCC at 2.7 V >VCC > 3.6 V VY = VOH – 0.3 V at 2.7 V ≤ VCC ≤ 3.6 V VY = VOH – 0.1 × VCC at 2.7 V >VCC > 3.6 V VI INPUTS GND t PLH V OH OUTPUTS V OL VM t PHL tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ tPZL VM VX tPZH VM VI INPUTS GND VM SV01638 VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM outputs disabled outputs enabled Figure 12. Input (Vis) to output (Vos) propagation delays. SV01640 Figure 13. Turn-on and turn-off times for the inputs (nS, E) to the output (Vos). TEST CIRCUIT 90% VS1 Open GND VO D.U.T. RT CL= 50pF RL = 1k POSITIVE PULSE 10% RL = 1k NEGATIVE PULSE VM 10% tTHL (tf) tTLH (tr) 90% VM tW 90% VM 10% 0V 10% 0V Vl PULSE GENERATOR tTLH (tr) tTHL (tf) VI tW 90% VM VI Vcc S1 Test Circuit for Outputs VM = 1.5V Input Pulse Definition SWITCH POSITION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VS1 GND VCC < 2.7V 2.7–3.6V ≥ 4.5 V VI VCC 2.7V VCC VS1 2 < VCC 2 < VCC 2 < VCC DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. SY00044 Figure 14. Load circuitry for switching times. 1998 Jun 23 10 Philips Semiconductors Product specification Quad bilateral latches 74LV4316 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 1998 Jun 23 11 Philips Semiconductors Product specification Quad bilateral latches 74LV4316 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 1998 Jun 23 12 Philips Semiconductors Product specification Quad bilateral latches 74LV4316 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 1998 Jun 23 13 Philips Semiconductors Product specification Quad bilateral latches 74LV4316 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 1998 Jun 23 14 Philips Semiconductors Product specification Quad bilateral latches 74LV4316 NOTES 1998 Jun 23 15 Philips Semiconductors Product specification Quad bilateral switches 74LV4316 DEFINITIONS Data Sheet Identification Objective Specification Product Status Formative or in Design Definition This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Preliminary Specification Preproduction Product Product Specification Full Production Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. © Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04663 Philips Semiconductors yyyy mmm dd 16