74LVC157ADB

INTEGRATED CIRCUITS DATA SHEET 74LVC157A Quad 2-input multiplexer Product specification Supersedes data of 2003 Jun 17 2003 Dec 02 Philips Semiconductors Product specification Quad 2-input multiplexer FEATURES • 5 V tolerant inputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption • Direct interface with TTL levels • Inputs accept voltages up to 5.5 V • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION The 74LVC157A is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. 74LVC157A Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment. The 74LVC157A is a quad 2-input multiplexer which select four bits of data from two sources under the control of a common select input (S). The four outputs present the selected data in the true (non-inverted) form. The enable input (E) is active LOW. When pin E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other input conditions. Moving the data from two groups of registers to four common output buses is a common use of the 74LVC157A. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. The device is useful for implementing highly irregular logic by generating any 4 of the 16 different functions of two variables with one variable common. The 74LVC157A is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is determined by the logic levels applied to pin S. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay nI0, nI1 to nY E to nY S to nY CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. input capacitance power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V 2.6 2.8 2.6 5.0 15 ns ns ns pF pF CONDITIONS TYPICAL UNIT 2003 Dec 02 2 Philips Semiconductors Product specification Quad 2-input multiplexer FUNCTION TABLE See note 1. INPUT E H L L L L Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care. ORDERING INFORMATION TYPE NUMBER 74LVC157AD 74LVC157ADB 74LVC157APW 74LVC157ABQ PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2003 Dec 02 S 1I0 1I1 1Y 2I0 2I1 2Y GND 3Y 3I1 3I0 4Y 4I1 4I0 E VCC SYMBOL common data select input data input from source 0 data input from source 1 multiplexer output data input from source 0 data input from source 1 multiplexer output ground (0 V) multiplexer output data input from source 1 data input from source 0 multiplexer output data input from source 1 data input from source 0 enable input (active LOW) supply voltage 3 DESCRIPTION TEMPERATURE RANGE −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C PACKAGE PINS 16 16 16 16 PACKAGE SO16 SSOP16 TSSOP16 DHVQFN16 MATERIAL plastic plastic plastic plastic S X L L H H nI0 X L H X X nI1 X X X L H 74LVC157A OUTPUT nY L L H L H CODE SOT109-1 SOT338-1 SOT403-1 SOT763-1 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A handbook, halfpage S 1 VCC 16 15 14 13 E 4I0 4I1 4Y 3I0 3I1 handbook, halfpage S1 1I0 2 1I1 3 1Y 4 16 VCC 15 E 14 4I0 13 4I1 1I0 1I1 1Y 2I0 2 3 4 GND(1) 5 6 7 8 Top view GND 9 3Y MDB106 157 2I0 5 2I1 6 2Y 7 GND 8 MNA480 12 11 10 12 4Y 11 3I0 10 3I1 9 3Y 2I1 2Y (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO16 and (T)SSOP16. Fig.2 Pin configuration DHVQFN16. handbook, halfpage 1 15 G1 EN handbook, halfpage 2 3 5 6 11 10 14 13 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 1 15 S E 1Y 4 2Y 7 3Y 9 4Y 12 MNA481 2 3 5 6 11 10 14 13 1 1 MUX 4 7 9 12 MNA482 Fig.3 Logic symbol. Fig.4 Logic symbol (IEEE/IEC). 2003 Dec 02 4 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A handbook, halfpage 2 3 5 6 11 10 14 13 1I0 1I1 2I0 2Y 2I1 3I0 3I1 4I0 4I1 4Y 12 SELECTOR MULTIPLEXER OUTPUTS 7 1Y 4 3Y 9 S 1 E 15 MNA483 Fig.5 Functional diagram. handbook, halfpage S E 1I1 1Y 1I0 2I1 2Y 2I0 3I1 3Y 3I0 4I1 4Y 4I0 MNA484 Fig.6 Logic diagram. 2003 Dec 02 5 Philips Semiconductors Product specification Quad 2-input multiplexer RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times VCC = 1.2 to 2.7 V VCC = 2.7 to 3.6 V CONDITIONS for low voltage applications MIN. 1.2 0 0 −40 0 0 74LVC157A MAX. 3.6 3.6 5.5 VCC +125 20 10 V V V V °C UNIT for maximum speed performance 2.7 ns/V ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO16 packages: above 70 °C the value of PD derates linearly with 8 mW/K. For (T)SSOP16 packages: above 60 °C the value of PD derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C the value of PD derates linearly with 4.5 mW/K. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation Tamb = −40 to +125 °C; note 2 VI < 0 note 1 VO > VCC or VO < 0 note 1 VO = 0 to VCC CONDITIONS − −0.5 − −0.5 − − −65 − MIN. −0.5 MAX. +6.5 −50 +6.5 ±50 VCC + 0.5 ±50 ±100 +150 500 V mA V mA V mA mA °C mW UNIT 2003 Dec 02 6 Philips Semiconductors Product specification Quad 2-input multiplexer DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −12 mA IO = −18 mA IO = −24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 12 mA IO = 24 mA ILI ICC ∆ICC input leakage current quiescent supply current VI = 5.5 V or GND VI = VCC or GND; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 2.7 to 3.6 − − − − − − − − − ±0.1 0.1 5 2.7 to 3.6 2.7 3.0 3.0 VCC − 0.2 VCC − 0.5 VCC − 0.6 VCC − 0.8 − − − − 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 − − − − − − VCC (V) MIN. TYP.(1) 74LVC157A MAX. UNIT − − GND 0.8 − − − − 0.2 0.4 0.55 ±5 10 500 V V V V V V V V V V V µA µA µA additional quiescent VI =VCC − 0.6 V; supply current per IO = 0 input pin 2003 Dec 02 7 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −12 mA IO = −18 mA IO = −24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 12 mA IO = 24 mA ILI ICC ∆ICC input leakage current quiescent supply current VI = 5.5 V or GND VI = VCC or GND; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 2.7 to 3.6 − − − − − − − − − − − − 2.7 to 3.6 2.7 3.0 3.0 VCC − 0.3 VCC − 0.65 VCC − 0.75 VCC − 1 − − − − 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 − − − − − − VCC (V) MIN. TYP.(1) MAX. UNIT − − GND 0.8 − − − − 0.3 0.6 0.8 ±20 40 5000 V V V V V V V V V V V µA µA µA additional quiescent VI =VCC − 0.6 V; supply current per IO = 0 input pin Note 1. All typical values are measured at Tamb = 25 °C. 2003 Dec 02 8 Philips Semiconductors Product specification Quad 2-input multiplexer AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 to +85 °C; note 1 tPHL/tPLH propagation delay nI0, nI1 to nY see Figs 8 and 9 1.2 2.7 3.0 to 3.6 propagation delay E to nY see Figs 7 and 9 1.2 2.7 3.0 to 3.6 propagation delay S to nY see Figs 8 and 9 1.2 2.7 3.0 to 3.6 tsk(0) skew note 3 3.0 to 3.6 Tamb = −40 to +125 °C tPHL/tPLH propagation delay nI0, nI1 to nY see Figs 8 and 9 1.2 2.7 3.0 to 3.6 propagation delay E to nY see Figs 7 and 9 1.2 2.7 3.0 to 3.6 propagation delay S to nY see Figs 8 and 9 1.2 2.7 3.0 to 3.6 tsk(0) Notes 1. All typical values are measured at Tamb = 25 °C. 2. This typical value is measured at VCC = 3.3 V and Tamb = 25 °C. skew note 3 3.0 to 3.6 − 1.0 1.0 − 1.0 1.0 − 1.0 1.0 − − − − − − − − − − − − 1.0 1.0 − 1.0 1.0 − 1.0 1.0 − 16 3.0 2.6(2) 17 3.4 2.8(2) 16 3.0 2.6(2) − VCC (V) MIN. TYP. 74LVC157A MAX. UNIT − 5.9 5.2 − 7.8 6.5 − 7.3 6.3 1.0 − 7.5 6.5 − 10.0 8.5 − 9.5 8.0 1.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2003 Dec 02 9 Philips Semiconductors Product specification Quad 2-input multiplexer AC WAVEFORMS 74LVC157A handbook, halfpage VCC E input GND VM t PHL VOH nY output VOL VM t PLH MNA485 INPUT VCC 1.2 V 2.7 V 3.0 to 3.6 V VM 0.5 × VCC 1.5 V 1.5 V VCC 2.7 V 2.7 V VI tr = tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 Enable input (E) to output (nY) propagation delays. handbook, halfpage VI VM GND t PHL VOH t PLH nI0, nI1, S input nY output VOL VM MNA486 INPUT VCC 1.2 V 2.7 V 3.0 to 3.6 V VM 0.5 × VCC 1.5 V 1.5 V VCC 2.7 V 2.7 V VI tr = tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns VOL and VOH are typical output voltage drop that occur with the output load. Fig.8 Data inputs (nI0, nI1) and common data select input (S) to output (nY) propagation delays. 2003 Dec 02 10 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A handbook, full pagewidth S1 VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 500 Ω VO RL 500 Ω 2 × VCC open GND MNA368 VCC 1.2 V 2.7 V 3.0 to 3.6 V Note VI VCC 2.7 V 2.7 V CL 50 pF 50 pF 50 pF RL 500 Ω(1) VEXT tPLH/tPHL tPZH/tPHZ open open open GND GND GND tPZL/tPLZ 2 × VCC 2 × VCC 2 × VCC 500 Ω 500 Ω 1. The circuit performs better when RL = 1000 Ω. Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.9 Load circuitry for switching times. 2003 Dec 02 11 Philips Semiconductors Product specification Quad 2-input multiplexer PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm 74LVC157A SOT109-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index θ Lp 1 e bp 8 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 θ 0.010 0.057 0.004 0.049 0.019 0.0100 0.39 0.014 0.0075 0.38 0.244 0.041 0.228 8 0o o ISSUE DATE 99-12-27 03-02-19 2003 Dec 02 12 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y HE vM A Z 16 9 Q A2 pin 1 index Lp L 1 bp 8 wM detail X A1 (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 θ 8 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2003 Dec 02 13 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE vMA Z 16 9 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 8 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 θ 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 2003 Dec 02 14 Philips Semiconductors Product specification Quad 2-input multiplexer 74LVC157A DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 7 vMCAB wM C y1 C C y 1 Eh 16 8 e 9 15 Dh 10 X 2.5 scale 5 mm 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 2003 Dec 02 15 Philips Semiconductors Product specification Quad 2-input multiplexer DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION 74LVC157A This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Dec 02 16 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/05/pp17 Date of release: 2003 Dec 02 Document order number: 9397 750 12371