74LVC16244ADGG

INTEGRATED CIRCUITS DATA SHEET 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state Product specification Supersedes data of 2003 Jan 30 2003 Dec 08 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state FEATURES • 5 V tolerant inputs/outputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • All data inputs have bushold (74LVCH16244A only). • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION 74LVC16244A; 74LVCH16244A The 74LVC(H)16244A is a high-performance, low power, low voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 Volt. These features allow the use of these devices as a mixed 3.3 and 5 V environment. The 74LVC(H)16244A is a 16-bit non-inverting buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four Output Enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. The 74LVC(H)16244A is identical to the 74LVC16240A but has non-inverting outputs. The 74LVCH16244A bushold data inputs eliminates the need for external pull-up resistors to hold unused inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPHL/tPLH tPZH/tPZL tPHZ/tPLZ CI CPD PARAMETER propagation delay nAn to nYn 3-state output enable time nOE to nYn 3-state output disable time nOE to nYn input capacitance power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 outputs enabled outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 12 4.0 pF pF CONDITIONS CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V TYPICAL 3.0 3.5 3.7 5.0 ns ns ns pF UNIT 2003 Dec 08 2 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state FUNCTION TABLE See note 1. INPUT nOE L L H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74LVC16244ADL 74LVCH16244ADL 74LVC16244ADGG 74LVCH16244ADGG 74LVC16244AEV 74LVCH16244AEV −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C PINS 48 48 48 48 56 56 nAn L H X 74LVC16244A; 74LVCH16244A OUTPUT nYn L H Z PACKAGE MATERIAL SSOP48 SSOP48 TSSOP48 TSSOP48 VFBGA56 VFBGA56 plastic plastic plastic plastic plastic plastic CODE SOT370-1 SOT370-1 SOT362-1 SOT362-1 SOT702-1 SOT702-1 2003 Dec 08 3 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state PINNING SYMBOL 1OE n.c. 1Y0 1Y1 GND 1Y2 1Y3 VCC 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3 4OE 3OE 4A3 4A2 4A1 4A0 3A3 3A2 3A1 3A0 2A3 2A2 2A1 2A0 1A3 1A2 1A1 1A0 2OE 1 − 2 3 4, 10, 15, 21, 28, 34, 39, 45 5 6 7, 18, 31, 42 8 9 11 12 13 14 16 17 19 20 22 23 24 25 26 27 29 30 32 33 35 36 37 38 40 41 43 44 46 47 48 PIN A1 A2, A3, A4, A5, K2, K3, K4, K5 B2 B1 B3, B4, D3, D4, G3, G4, J3, J4 C2 C1 C3, H3, C4, H4 D2 D1 E2 E1 F1 F2 G1 G2 H1 H2 J1 J2 K1 K6 J5 J6 H5 H6 G5 G6 F5 F6 E6 E5 D6 D5 C6 C5 B6 B5 A6 BALL 74LVC16244A; 74LVCH16244A DESCRIPTION output enable input (active LOW) not connected data output data output ground (0 V) data output data output supply voltage data output data output data output data output data output data output data output data output data output data output data output data output output enable input (active LOW) output enable input (active LOW) data input data input data input data input data input data input data input data input data input data input data input data input data input data input data input data input output enable input (active LOW) 2003 Dec 08 4 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 74LVC16244A; 74LVCH16244A 1OE 1Y0 1Y1 GND 1Y2 1Y3 VCC 2Y0 2Y1 1 2 3 4 5 6 7 8 9 48 2OE 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC 41 2A0 40 2A1 39 GND 38 2A2 K J H G F E D C B A ball A1 123456 index area 001aaa196 16244 GND 10 2Y2 11 2Y3 12 3Y0 13 3Y1 14 GND 15 3Y2 16 3Y3 17 VCC 18 4Y0 19 4Y1 20 GND 21 4Y2 22 4Y3 23 4OE 24 mna706 16244 37 2A3 36 3A0 35 3A1 34 GND 33 3A2 32 3A3 31 VCC 30 4A0 29 4A1 28 GND 27 4A2 26 4A3 25 3OE Fig.1 Pin configuration SSOP48 and TSSOP48. Fig.2 Pin configuration VFBGA56. 2003 Dec 08 5 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 74LVC16244A; 74LVCH16244A 47 handbook, halfpage 1A0 2 1Y0 3 1Y1 3A1 3A0 36 13 3Y0 1OE 1 48 25 24 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 mna704 1EN 2EN 3EN 4EN 1 1 2 3 5 6 12 8 9 11 12 13 13 14 16 17 14 19 20 22 23 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3Y0 3Y1 3Y2 3Y3 4Y0 4Y1 4Y2 4Y3 46 1A1 44 35 14 3Y1 2OE 3OE 4OE 5 1Y2 3A2 1A2 33 16 3Y2 1A0 1A1 1A3 1OE 43 1 6 1Y3 3A3 3OE 32 25 17 3Y3 1A2 1A3 2A0 2A1 41 2A0 40 2A1 38 8 2Y0 9 2Y1 11 2Y2 4A2 4A1 4A0 30 19 4Y0 2A2 2A3 3A0 29 20 4Y1 3A1 3A2 2A2 27 22 4Y2 3A3 4A0 2A3 2OE 37 48 12 2Y3 4A3 4OE 26 24 23 4Y3 4A1 4A2 4A3 MNA996 Fig.3 Logic symbol. Fig.4 Logic symbol (IEEE/IEC). handbook, halfpage VCC data input to internal circuit MNA705 Fig.5 Bushold circuit. 2003 Dec 08 6 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage CONDITIONS for maximum speed performance for low voltage applications VI VO Tamb tr, tf input voltage output voltage operating ambient temperature input rise and fall times output HIGH or LOW state output 3-state in free air VCC = 1.2 to 2.7 V VCC = 2.7 to 3.6 V 2.7 1.2 0 0 0 −40 0 0 MIN. 74LVC16244A; 74LVCH16244A MAX. 3.6 3.6 5.5 VCC 5.5 +125 20 10 V V V V V °C UNIT ns/V ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO PARAMETER supply voltage input diode current input voltage output diode current output voltage VI < 0 note 1 VO > VCC or VO < 0 output HIGH or LOW state; note 1 output 3-state; note 1 IO ICC, IGND Tstg Ptot output source or sink current VCC or GND current storage temperature power dissipation SSOP and TSSOP package Tamb = −40 to +125 °C; note 2 VFBGA package Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. 3. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. Tamb = −40 to +125 °C; note 3 − − 500 1000 mW mW VO = 0 to VCC CONDITIONS − −0.5 − −0.5 −0.5 − − −65 MIN. −0.5 MAX. +6.5 −50 +6.5 ±50 VCC + 0.5 +6.5 ±50 ±100 +150 V mA V mA V V mA mA °C UNIT 2003 Dec 08 7 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C; note 1 VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −12 mA IO = −18 mA IO = −24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 12 mA IO = 24 mA ILI IOZ input leakage current 3-state output OFF-state current power-off leakage supply current quiescent supply current VI = 5.5 V or GND; note 2 VI = VIH or VIL; VO = 5.5 V or GND; note 2 VI or VO = 5.5 V VI = VCC or GND; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 − − − − − 0 − − 2.7 to 3.6 2.7 3.0 3.0 VCC − 0.2 VCC − 0.5 VCC − 0.6 VCC − 0.8 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 − − − − − − VCC (V) MIN. 74LVC16244A; 74LVCH16244A TYP. MAX. UNIT − − 0 0.8 − − − − 0.20 0.40 0.55 ±5 ±5 V V V V V V V V V V V µA µA VCC − − − ±0.1 0.1 Ioff ICC ∆ICC IBH IBHH IBHLO IBHHO 0.0 3.6 2.7 to 3.6 3.0 3.0 3.6 3.6 − − − 75 −75 500 −500 0.1 0.1 5 − − − − ±10 20 500 − − − − µA µA µA µA µA µA µA additional quiescent supply VI = VCC − 0.6 V; current per input pin IO = 0 bushold LOW sustaining current bushold HIGH sustaining current bushold LOW overdrive current bushold HIGH overdrive current VI = 0.8 V; notes 3 and 4 VI = 2.0 V; notes 3 and 4 notes 3 and 5 notes 3 and 5 2003 Dec 08 8 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −12 mA IO = −18 mA IO = −24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 12 mA IO = 24 mA ILI IOZ input leakage current 3-state output OFF-state current power-off leakage supply current quiescent supply current VI = 5.5 V or GND; note 2 VI = VIH or VIL; VO = 5.5 V or GND; note 2 VI or VO = 5.5 V VI = VCC or GND; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 − − − − − − − − − − 2.7 to 3.6 2.7 3.0 3.0 VCC − 0.3 VCC − 0.65 VCC − 0.75 VCC − 1 − − − − 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 − − − − − − VCC (V) MIN. 74LVC16244A; 74LVCH16244A TYP. MAX. UNIT − − 0 0.8 − − − − 0.3 0.6 0.8 ±20 ±20 V V V V V V V V V V V µA µA Ioff ICC ∆ICC IBH IBHH IBHLO IBHHO Notes 0.0 3.6 2.7 to 3.6 3.0 3.0 3.6 3.6 − − − 60 −60 500 −500 − − − − − − − ±20 80 5000 − − − − µA µA µA µA µA µA µA additional quiescent supply VI = VCC − 0.6 V; current per input pin IO = 0 bushold LOW sustaining current bushold HIGH sustaining current bushold LOW overdrive current bushold HIGH overdrive current VI = 0.8 V; notes 3 and 4 VI = 2.0 V; notes 3 and 4 notes 3 and 5 notes 3 and 5 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2. For bushold parts, the bushold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. 3. Valid for data inputs of bushold parts (74LVCH16244A) only. For data inputs only, control inputs do not have a bushold circuit. 4. The specified sustaining current at the data inputs holds the input below the specified VI level. 5. The specified overdrive current at the data input forces the data input to the opposite logic input state. 2003 Dec 08 9 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 500 Ω. CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 to +85 °C; note1 tPHL/tPLH propagation delay nAn to nYn see Figs 6 and 8 1.2 2.7 3.0 to 3.6 tPZH/tPZL 3-state output enable time nOE to nYn see Figs 7 and 8 1.2 2.7 3.0 to 3.6 tPHZ/tPLZ 3-state output disable time nOE to nYn see Figs 7 and 8 1.2 2.7 3.0 to 3.6 Tamb = −40 to +125 °C tPHL/tPLH propagation delay nAn to nYn see Figs 6 and 8 1.2 2.7 3.0 to 3.6 tPZH/tPZL 3-state output enable time nOE to nYn see Figs 7 and 8 1.2 2.7 3.0 to 3.6 tPHZ/tPLZ 3-state output disable time nOE to nYn see Figs 7 and 8 1.2 2.7 3.0 to 3.6 Notes 1. All typical values are measured at Tamb = 25 °C. 2. These typical values are measured at VCC = 3.3 V and Tamb = 25 °C. − 1.0 1.1 − 1.0 1.0 − 1.0 1.8 − 1.0 1.1 − 1.0 1.0 − 1.0 1.8 VCC (V) MIN. 74LVC16244A; 74LVCH16244A TYP. MAX. UNIT 11.0 − 3.0(2) 15.0 − 3.5(2) 10.0 − 3.7(2) − − − − − − − − − − 4.7 4.1 − 5.8 4.6 − 6.2 5.2 − 6.0 5.5 − 7.5 6.0 − 8.0 6.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2003 Dec 08 10 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state AC WAVEFORMS 74LVC16244A; 74LVCH16244A handbook, halfpage VI nAn input GND tPLH VOH nYn output VOL VM VM tPHL VM VM MNA171 INPUT VCC 1.2 V 2.7 V 3.0 to 3.6 V VM 0.5 × VCC 1.5 V 1.5 V VCC 2.7 V 2.7 V VI tr = tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 The input nAn to output nYn propagation delays. 2003 Dec 08 11 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 74LVC16244A; 74LVCH16244A handbook, full pagewidth VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM outputs disabled outputs enabled MNA362 INPUT VCC 1.2 V 2.7 V 3.0 to 3.6 V VM 0.5 × VCC 1.5 V 1.5 V VCC 2.7 V 2.7 V VI tr = tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns VX = VOL + 0.3 V at VCC ≥ 2.7 V; VX = VOL + 0.1 V at VCC < 2.7 V; VY = VOH − 0.3 V at VCC ≥ 2.7 V; VY = VOH − 0.1 V at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 3-state enable and disable times. 2003 Dec 08 12 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 74LVC16244A; 74LVCH16244A handbook, full pagewidth VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL MNA616 VCC 1.2 V 2.7 V 3.0 to 3.6 V Note VI VCC 2.7 V 2.7 V CL 50 pF 50 pF 50 pF RL 500 Ω(1) VEXT tPLH/tPHL tPZH/tPHZ open open open GND GND GND tPZL/tPLZ 2 × VCC 2 × VCC 2 × VCC 500 Ω 500 Ω 1. The circuit performs better when RL = 1000 Ω. Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.8 Load circuitry for switching times. 2003 Dec 08 13 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state PACKAGE OUTLINES 74LVC16244A; 74LVCH16244A SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE vM A Z 48 25 Q A2 A1 (A 3) θ Lp 1 bp 24 wM L detail X A pin 1 index e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2003 Dec 08 14 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 74LVC16244A; 74LVCH16244A TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c y HE vMA Z 48 25 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp 24 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2003 Dec 08 15 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state 74LVC16244A; 74LVCH16244A VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm SOT702-1 D B A ball A1 index area E A A2 A1 detail X e1 e 1/2 e b ∅v M C A B ∅w M C C y1 C y K J H e G F E D C B A ball A1 index area 1 2 3 4 5 6 1/2 e e2 X DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.3 0.2 A2 0.7 0.6 b 0.45 0.35 D 4.6 4.4 E 7.1 6.9 e 0.65 e1 3.25 e2 5.85 v 0.15 w 0.08 y 0.08 y1 0.1 0 2.5 scale 5 mm OUTLINE VERSION SOT702-1 REFERENCES IEC JEDEC MO-225 JEITA EUROPEAN PROJECTION ISSUE DATE 02-08-08 03-07-01 2003 Dec 08 16 Philips Semiconductors Product specification 16-bit buffer/line driver; 5 V input/output tolerant; 3-state DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION 74LVC16244A; 74LVCH16244A This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Dec 08 17 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/07/pp18 Date of release: 2003 Dec 08 Document order number: 9397 750 12369