74LVC16245A

74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state Rev. 08 — 6 November 2008 Product data sheet 1. General description The 74LVC16245A; 74LVCH16245A are 16-bit transceivers featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for direction control. nOE controls the outputs so that the buses are effectively isolated. This device can be used as two 8-bit transceivers or one 16-bit transceiver. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The 74LVCH16245A bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features I I I I I I I I I I 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption MULTIBYTE flow-through standard pin-out architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels High-impedance when VCC = 0 V All data inputs have bus hold. (74LVCH16245A only) Complies with JEDEC standard JESD8-B / JESD36 ESD protection: N HBM JESD22-A114E exceeds 2000 V N CDM JESD22-C101C exceeds 1000 V Specified from −40 °C to +85 °C and −40 °C to +125 °C I NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 3. Ordering information Table 1. Ordering information Temperature range Package Name 74LVC16245ADL 74LVCH16245ADL 74LVC16245ADGG 74LVCH16245ADGG 74LVC16245AEV 74LVCH16245AEV 74LVC16245ABQ 74LVCH16245ABQ −40 °C to +125 °C −40 °C to +125 °C VFBGA56 −40 °C to +125 °C TSSOP48 −40 °C to +125 °C SSOP48 Description plastic shrink small outline package; 48 leads; body width 7.5 mm plastic thin shrink small outline package; 48 leads; body width 6.1 mm Version SOT370-1 SOT362-1 Type number plastic very thin fine-pitch ball grid array package; SOT702-1 56 balls; body 4.5 × 7 × 0.65 mm SOT1025-1 HUQFN60U plastic thermal enhanced ultra thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.55 mm 4. Functional diagram 1DIR 1OE 1A0 1B0 1A1 1B1 1A2 1B2 1A3 1B3 1A4 1B4 1A5 1B5 1A6 1B6 1A7 1B7 2DIR 2OE 2A0 2B0 2A1 2B1 2A2 2B2 2A3 2B3 2A4 2B4 2A5 2B5 2A6 2B6 2A7 2B7 001aaa789 Fig 1. Logic symbol 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 2 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 1OE 1DIR 2OE 2DIR G3 3EN1[BA] 3EN2[AB] G6 6EN1[BA] 6EN2[AB] 1A0 1 2 1B0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 2A0 4 5 2A1 2A2 2A3 2A4 2A5 2A6 2A7 1B1 1B2 1B3 1B4 1B5 1B6 1B7 2B0 2B1 2B2 2B3 2B4 2B5 2B6 2B7 001aaa790 Fig 2. IEC logic symbol VCC data input to internal circuit mna705 Fig 3. Bus hold circuit 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 3 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 5. Pinning information 5.1 Pinning 74LVC16245A 74LVCH16245A 1DIR 1B0 1B1 GND 1B2 1B3 VCC 1B4 1B5 1 2 3 4 5 6 7 8 9 48 1OE 47 1A0 46 1A1 45 GND 44 1A2 43 1A3 42 VCC 41 1A4 40 1A5 39 GND 38 1A6 37 1A7 36 2A0 35 2A1 34 GND 33 2A2 32 2A3 31 VCC 30 2A4 29 2A5 28 GND 27 2A6 26 2A7 25 2OE 001aad110 GND 10 1B6 11 1B7 12 2B0 13 2B1 14 GND 15 2B2 16 2B3 17 VCC 18 2B4 19 2B5 20 GND 21 2B6 22 2B7 23 2DIR 24 74LVC16245A ball A1 74LVCH16245A index area 123456 A B C D E F G H J K 001aad111 Transparent top view Fig 4. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48) Fig 5. Pin configuration SOT702-1 (VFBGA56) 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 4 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state terminal 1 index area D1 A32 A31 A30 A29 A28 A27 D4 A1 D5 B20 B19 B18 D8 A26 A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 A9 GND(1) B11 B12 B15 B16 B17 A25 A24 A23 A22 74LVC16245A 74LVCH16245A B14 A21 B13 A20 A19 A18 A10 D6 B8 B9 B10 D7 A17 D2 A11 A12 A13 A14 A15 A16 D3 001aai894 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 6. Pin configuration SOT1025-1 (HUQFN60U) 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 5 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 5.2 Pin description Table 2. Symbol Pin description Pin SOT370-1 and SOT362-1 1DIR, 2DIR 1, 24 SOT702-1 A1, K1 SOT1025-1 A30, A13 B20, A31, D5, D1, A2, B2, B3, A5 A6, B5, B6, A9, D2, D6, A12, B8 A32, A3, A8, A11, A16, A19, A24, A27 A1, A10, A17, A26 A29, A14 B18, A28, D8, D4, A25, B16, B15, A22 direction control input data input/output data input/output ground (0 V) supply voltage output enable input (active LOW) data input/output Description 1B0 to 1B7 2, 3, 5, 6, 8, 9, 11, B2, B1, C2, C1, D2, D1, 12 E2, E1 2B0 to 2B7 13, 14, 16, 17, 19, F1, F2, G1, G2, H1, H2, 20, 22, 23 J1, J2 GND VCC 1OE, 2OE 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 48, 25 B3, B4, D3, D4, G3, G4, J3, J4 C3, C4, H3, H4 A6, K6 1A0 to 1A7 47, 46, 44, 43, 41, B5, B6, C5, C6, D5, D6, 40, 38, 37 E5, E6 2A0 to 2A7 36, 35, 33, 32, 30, F6, F5, G6, G5, H6, H5, 29, 27, 26 J6, J5 n.c. A2, A3, A4, A5, K2, K3, K4, K5 A21, B13, B12, A18, D3, data input/output D7, A15, B10 A4, A7, A20, A23, B1, B4, B7, B9, B11, B14, B17, B19 not connected 6. Functional description Table 3. Inputs nOE L L H [1] Function table[1] Outputs nDIR L H X nAn A=B inputs Z nBn inputs B=A Z H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 6 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C; (T)SSOP48 package VFBGA56 package HUQFN60U package [1] [2] [3] [4] [3] [4] [4] Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [2] [2] Max +6.5 +6.5 ±50 VCC + 0.5 +6.5 ±50 100 +150 500 1000 1000 Unit V mA V mA V V mA mA mA °C mW mW mW VO > VCC or VO < 0 V output HIGH or LOW output 3-state VO = 0 V to VCC −0.5 −0.5 −100 −65 - The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Symbol VCC Recommended operating conditions Parameter supply voltage Conditions maximum speed performance functional VI VO Tamb ∆t/∆V input voltage output voltage ambient temperature input transition rise and fall rate output HIGH or LOW output 3-state in free air VCC = 1.2 V to 2.7 V VCC = 2.7 V to 3.6 V Min 2.7 1.2 0 0 0 −40 0 0 Typ Max 3.6 3.6 5.5 VCC 5.5 +125 20 10 Unit V V V V V °C ns/V ns/V 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 7 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol VIH VIL VOH Parameter HIGH-level input voltage LOW-level input voltage Conditions VCC = 1.2 V VCC = 2.7 V to 3.6 V VCC = 1.2 V VCC = 2.7 V to 3.6 V −40 °C to +85 °C Min VCC 2.0 VCC − 0.2 2.2 2.4 2.2 [2] −40 °C to +125 °C Unit Min VCC 2.0 VCC − 0.3 2.05 2.25 2.0 Max 0 0.8 0.3 0.6 0.8 ±20 ±20 V V V V V V V V V V V µA µA 0 Typ[1] VCC 0 ±0.1 ±0.1 Max 0.8 0.20 0.40 0.55 ±5 ±5 HIGH-level output VI = VIH or VIL voltage IO = −100 µA; VCC = 2.7 V to 3.6 V IO = −12 mA; VCC = 2.7 V IO = −18 mA; VCC = 3.0 V IO = −24 mA; VCC = 3.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 2.7 V to 3.6 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V II IOZ input leakage current OFF-state output current VI = 5.5 V or GND; VCC = 3.6 V VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V - [2][3] IOFF ICC ∆ICC CI CI/O IBHL IBHH IBHLO power-off leakage VI or VO = 5.5 V; VCC = 0.0 V supply supply current additional supply current VI = VCC or GND; IO = 0 A; VCC = 3.6 V per input pin; VI = VCC − 0.6 V; IO = 0 A; VCC = 2.7 V to 3.6 V [4][5] ±0.1 0.1 5 5.0 10 - ±10 10 500 - 60 −60 500 ±20 40 5000 - µA µA µA pF pF µA µA µA input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC input/output capacitance bus hold current LOW bus hold current HIGH bus hold overdrive current LOW VCC = 0 V to 3.6 V; VI = GND to VCC VCC = 3.0 V; VI = 0.8 V VCC = 3.0 V; VI = 2.0 V VCC = 3.6 V 75 −75 500 [4][5] [4][6] 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 8 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol IBHHO Parameter bus hold overdrive current HIGH Conditions VCC = 3.6 V [4][6] −40 °C to +85 °C Min −500 Typ[1] Max - −40 °C to +125 °C Unit Min −500 Max µA [1] [2] [3] [4] [5] [6] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. The bus hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. For I/O ports the parameter IOZ includes the input leakage current. Valid for data inputs of bus hold parts only (74LVCH16245A). Note that control inputs do not have a bus hold circuit. The specified sustaining current at the data input holds the input below the specified VI level. The specified overdrive current at the data input forces the data input to the opposite input state. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter tpd propagation delay Conditions nAn to nBn; nBn to nAn; see Figure 7 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V ten enable time nOE to nAn, nBn; see Figure 8 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V tdis disable time nOE to nAn, nBn; see Figure 8 VCC = 1.2 V VCC = 2.7 V VCC = 3.0 V to 3.6 V [2] [2] [1] [2] [1] [1] −40 °C to +85 °C Min 1.0 1.0 1.5 1.0 1.5 1.5 Typ 13.0 2.7 2.2 15.0 3.6 2.8 11.0 3.4 3.2 Max 4.7 4.5 6.7 5.5 6.6 5.6 −40 °C to +125 °C Unit Min 1.0 1.0 1.5 1.0 1.5 1.5 Max 6.0 6.0 8.5 7.0 8.5 7.0 ns ns ns ns ns ns ns ns ns 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 9 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter CPD power dissipation capacitance Conditions per buffer; VI = GND to VCC VCC = 3.3 V [3] −40 °C to +85 °C Min Typ 30 Max - −40 °C to +125 °C Unit Min Max pF [1] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. Typical values are measured at Tamb = 25 °C and VCC = 3.3 V. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs. [2] [3] 11. Waveforms VI nAn, nBn input GND t PHL VOH nBn, nAn output VOL VM mna477 VM t PLH Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The input (nAn, nBn) to output (nBn, nAn) propagation delays 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 10 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM outputs disabled outputs enabled mna362 Measurement points are given in Table 8. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Table 8. VCC 1.2 V 2.7 V 3-state enable and disable times. Measurement points Input VI VCC 2.7 V 2.7 V VM 0.5 × VCC 1.5 V 1.5 V Output VM 0.5 × VCC 1.5 V 1.5 V VX VOL + 0.1 V VOL + 0.3 V VOL + 0.3 V VY VOH − 0.1 V VOH − 0.3 V VOH − 0.3 V Supply voltage 3.0 V to 3.6 V 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 11 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 9. Load circuit for measuring switching times Test data Input VI tr, tf ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns VCC 2.7 V 2.7 V Load CL 50 pF 50 pF 50 pF RL 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open tPLZ, tPZL 2 × VCC 2 × VCC 2 × VCC tPHZ, tPZH GND GND GND Supply voltage 1.2 V 2.7 V 3.0 V to 3.6 V [1] The circuit performs better when RL = 1 kΩ, 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 12 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE vM A Z 48 25 Q A2 A1 (A 3) θ Lp 1 bp 24 wM L detail X A pin 1 index e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT370-1 (SSOP48) 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 13 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c y HE vMA Z 48 25 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp 24 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT362-1 (TSSOP48) 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 14 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm SOT702-1 D B A ball A1 index area E A A2 A1 detail X e1 e 1/2 e b ∅v M C A B ∅w M C C y1 C y K J H e G F E D C B A ball A1 index area 1 2 3 4 5 6 1/2 e e2 X DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.3 0.2 A2 0.7 0.6 b 0.45 0.35 D 4.6 4.4 E 7.1 6.9 e 0.65 e1 3.25 e2 5.85 v 0.15 w 0.08 y 0.08 y1 0.1 0 2.5 scale 5 mm OUTLINE VERSION SOT702-1 REFERENCES IEC JEDEC MO-225 JEITA EUROPEAN PROJECTION ISSUE DATE 02-08-08 03-07-01 Fig 12. Package outline SOT702-1 (VFBGA56) 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 15 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state HUQFN60U: plastic thermal enhanced ultra thin quad flat package; no leads 60 terminals; UTLP based; body 4 x 6 x 0.55 mm D B A SOT1025-1 terminal 1 index area E A A1 detail X e2 v w M M CAB C e e1 1/2 e b v w M M CAB C C L1 L eR D2 D6 A11 B8 B10 A16 D3 D7 y1 C y A10 B7 A17 B11 e Eh 1/2 e B1 A1 B17 A26 e3 e4 terminal 1 index area D5 D1 A32 B20 B18 A27 Dh D8 D4 k X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.6 A1 0.05 0.00 b 0.35 0.25 D 4.1 3.9 Dh 1.9 1.8 E 6.1 5.9 Eh 3.9 3.8 e 0.5 e1 1 e2 2.5 e3 3 e4 4.5 eR 0.5 k 0.25 0.15 L L1 v w 0.05 y 0.08 y1 0.1 0.35 0.125 0.07 0.25 0.025 EUROPEAN PROJECTION OUTLINE VERSION SOT1025-1 REFERENCES IEC --JEDEC --JEITA --- ISSUE DATE 07-08-28 07-11-14 Fig 13. Package outline SOT1025-1 (HUQFN60U) 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 16 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 13. Abbreviations Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20081106 Data sheet status Preliminary data sheet Change notice Supersedes 74LVC_LVCH16245A_7 Document ID 74LVC_LVCH16245A_8 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74LVC16245ABQ and 74LVCH16245ABQ (HUQFN60U package) Product specification Product specification Product specification Product specification Product specification Product specification 74LVC_LVCH16245A_6 74LVC_LVCH16245A_5 74LVC_H16245A_4 74LVC16245A_ 74LVCH16245A_3 74LVC16245A_2 74LVC16245A_1 - 74LVC_LVCH16245A_7 74LVC_LVCH16245A_6 74LVC_LVCH16245A_5 74LVC_H16245A_4 74LVC16245A_ 74LVCH16245A_3 74LVC16245A_2 74LVC16245A_1 20031125 20030130 20021030 19970925 19970925 19970801 - 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 17 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC_LVCH16245A_8 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 08 — 6 November 2008 18 of 19 NXP Semiconductors 74LVC16245A; 74LVCH16245A 16-bit bus transceiver with direction pin; 5 V tolerant; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 November 2008 Document identifier: 74LVC_LVCH16245A_8