74LVC1G125

INTEGRATED CIRCUITS DATA SHEET 74LVC1G125 Bus buffer/line driver; 3-state Product specification Supersedes data of 2002 Nov 18 2004 Sep 15 Philips Semiconductors Product specification Bus buffer/line driver; 3-state FEATURES • Wide supply voltage range from 1.65 V to 5.5 V • High noise immunity • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V). • ±24 mA output drive (VCC = 3.0 V) • CMOS low power consumption • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V • Multiple package options • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 °C to +85 °C and −40 °C to +125 °C. DESCRIPTION 74LVC1G125 The 74LVC1G125 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G125 provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay input A to output Y CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω VCC = 5.0 V; CL = 50 pF; RL = 500 Ω CI CPD input capacitance power dissipation capacitance per buffer output enabled; notes 1 and 2 output disabled; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. TYPICAL 3.3 2.2 2.5 2.1 1.7 5 25 6 UNIT ns ns ns ns ns pF pF pF 2004 Sep 15 2 Philips Semiconductors Product specification Bus buffer/line driver; 3-state FUNCTION TABLE See note 1. INPUT OE L L H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC1G125GW 74LVC1G125GV 74LVC1G125GM PINNING PIN SC-88A; SC-74A 1 2 3 4 5 PIN XSON6 1 2 3 4 5 6 SYMBOL OE A GND Y n.c. VCC data input A ground (0 V) data output Y not connected supply voltage TEMPERATURE RANGE −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C PINS 5 5 6 PACKAGE SC-88A SC-74A XSON6 MATERIAL plastic plastic plastic A L H X 74LVC1G125 OUTPUT Y L H Z CODE SOT353 SOT753 SOT886 MARKING VM V25 VM DESCRIPTION output enable input 2004 Sep 15 3 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74LVC1G125 125 1 2 5 OE 1 6 VCC OE A VCC 125 4 001aab651 A 2 5 n.c. GND 3 Y GND 3 4 Y 001aab652 Transparent top view Fig.1 Pin configuration SC-88A and SC-74A. Fig.2 Pin configuration XSON6. handbook, halfpage 2 A Y 4 handbook, halfpage 2 4 1 OE MNA119 1 OE MNA118 Fig.3 Logic symbol. Fig.4 IEE/IEC logic symbol. 2004 Sep 15 4 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74LVC1G125 handbook, halfpage A Y OE MNA120 Fig.5 Logic diagram. 2004 Sep 15 5 Philips Semiconductors Product specification Bus buffer/line driver; 3-state RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO PARAMETER supply voltage input voltage output voltage VCC = 1.65 V to 5.5 V; enable mode VCC = 1.65 V to 5.5 V; disable mode VCC = 0 V; Power-down mode Tamb tr, tf operating ambient temperature input rise and fall times VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V CONDITIONS 0 0 0 0 −40 0 0 MIN. 1.65 74LVC1G125 MAX. 5.5 5.5 VCC 5.5 5.5 +125 20 10 V V V V V UNIT °C ns/V ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO PARAMETER supply voltage input diode current input voltage output diode current output voltage VI < 0 V note 1 VO > VCC or VO < 0 V enable mode; notes 1 and 2 disable mode; notes 1 and 2 IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. output source or sink current VCC or GND current storage temperature power dissipation Tamb = −40 °C to +125 °C VO = 0 V to VCC CONDITIONS − −0.5 − −0.5 −0.5 − − −65 − MIN. −0.5 MAX. +6.5 −50 +6.5 ±50 +6.5 +6.5 ±50 ±100 +150 250 V mA V mA V V mA mA °C mW UNIT VCC + 0.5 V Power-down mode; notes 1 and 2 −0.5 2004 Sep 15 6 Philips Semiconductors Product specification Bus buffer/line driver; 3-state DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 °C to +85 °C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −4 mA IO = −8 mA IO = −12 mA IO = −24 mA IO = −32 mA ILI IOZ input leakage current 3-state output OFF-state current power OFF leakage current VI = 5.5 V or GND VI = VIH or VIL; VO = 5.5 V or GND VI or VO = 5.5 V 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 5.5 VCC − 0.1 1.2 1.9 2.2 2.7 3.8 − − − − − − − − ±0.1 ±0.1 − − − − − − 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 − − − − − − − − − − − − 0.65 × VCC 1.7 2.0 0.7 × VCC − − − − − − − − − − − − − − − − VCC (V) MIN. TYP.(1) 74LVC1G125 MAX. UNIT V V V V V V V V V V V V V V V V V V V V µA µA 0.35 × VCC 0.7 0.8 0.3 × VCC 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 Ioff ICC ∆ICC 0 5.5 2.3 to 5.5 − − − ±0.1 0.1 5 ±10 10 500 µA µA µA quiescent supply VI = VCC or GND; current IO = 0 A additional VI = VCC − 0.6 V; quiescent supply IO = 0 A current per pin 2004 Sep 15 7 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74LVC1G125 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 °C to +125 °C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA VOH HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −4 mA IO = −8 mA IO = −12 mA IO = −24 mA IO = −32 mA ILI IOZ input leakage current 3-state output OFF-state current power OFF leakage current VI = 5.5 V or GND VI = VIH or VIL; VO = 5.5 V or GND VI or VO = 5.5 V 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 5.5 VCC − 0.1 0.95 1.7 1.9 2.0 3.4 − − 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 − − − − − − 0.65 × VCC 1.7 2.0 0.7 × VCC − − − − VCC (V) MIN. TYP.(1) MAX. UNIT − − − − − − − − − − − − − − − − − − − − − − − − − − 0.35 × VCC 0.7 0.8 0.3 × VCC 0.1 0.70 0.45 0.60 0.80 0.80 − − − − − − ±100 ±200 V V V V V V V V V V V V V V V V V V V V µA µA Ioff ICC ∆ICC 0 5.5 2.3 to 5.5 − − − − − − ±200 200 5000 µA µA µA quiescent supply VI = VCC or GND; current IO = 0 A additional VI = VCC − 0.6 V; quiescent supply IO = 0 A current per pin Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2004 Sep 15 8 Philips Semiconductors Product specification Bus buffer/line driver; 3-state AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 °C to +85 °C tPHL/tPLH propagation delay A, B to Y see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPZH/tPZL 3-state output enable time input OE to Y see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPHZ/tPLZ 3-state output disable time input OE to Y see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Tamb = −40 °C to +125 °C tPHL/tPLH propagation delay A, B to Y see Figs 6 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPZH/tPZL 3-state output enable time input OE to Y see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPHZ/tPLZ 3-state output disable time input OE to Y see Figs 7 and 8 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 1.0 0.5 0.5 0.5 0.5 1.0 0.5 0.5 0.5 0.5 1.0 0.5 0.5 0.5 0.5 − − − − − − − − − − − − − − − 1.0 0.5 0.5 0.5 0.5 1.0 0.5 0.5 0.5 0.5 1.0 0.5 0.5 0.5 0.5 3.3 2.2 2.5 2.1 1.7 4.1 2.8 3.3 2.4 2.1 4.3 2.7 3.0 3.1 2.2 VCC (V) MIN. TYP. 74LVC1G125 MAX. UNIT 8.0 5.5 5.5 4.5 4.0 9.4 6.6 6.6 5.3 5.0 9.2 5.0 5.0 5.0 4.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10.5 7 7 6 5.5 12 8.5 8.5 7 6.5 12 6.5 6.5 6.5 5.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2004 Sep 15 9 Philips Semiconductors Product specification Bus buffer/line driver; 3-state AC WAVEFORMS 74LVC1G125 handbook, halfpage VI VM(1) A input GND tPHL tPLH Y output VM(1) MNA128 INPUT VCC VM VI VCC VCC 2.7 V 2.7 V VCC tr = tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns 1.65 V to 1.95 V 0.5 × VCC 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 Input A to output Y propagation delay times. 2004 Sep 15 10 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74LVC1G125 handbook, full pagewidth VI OE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled MNA644 VM tPZL VM VX tPZH VY VM INPUT VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC VI VCC VCC 2.7 V 2.7 V VCC tr = tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns VX = VOL + 0.3 V at VCC ≥ 2.7 V; VX = VOL + 0.15 V at VCC < 2.7 V; VY = VOH − 0.3 V at VCC ≥ 2.7 V; VY = VOH − 0.15 V at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.7 3-state enable and disable times. 2004 Sep 15 11 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74LVC1G125 handbook, full pagewidth VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL MNA616 VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VI VCC VCC 2.7 V 2.7 V VCC CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH/tPHL open open open open open tPZH/tPHZ GND GND GND GND GND tPZL/tPLZ 2 × VCC 2 × VCC 6V 6V 2 × VCC Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.8 Load circuitry for switching times. 2004 Sep 15 12 Philips Semiconductors Product specification Bus buffer/line driver; 3-state PACKAGE OUTLINES Plastic surface mounted package; 5 leads 74LVC1G125 SOT353 D B E A X y HE vMA 5 4 Q A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E (2) 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT353 REFERENCES IEC JEDEC EIAJ SC-88A EUROPEAN PROJECTION ISSUE DATE 97-02-28 2004 Sep 15 13 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74LVC1G125 Plastic surface mounted package; 5 leads SOT753 D B E A X y HE vMA 5 4 Q A A1 c 1 2 3 detail X Lp e bp wM B 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.100 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT753 REFERENCES IEC JEDEC JEITA SC-74A EUROPEAN PROJECTION ISSUE DATE 02-04-16 2004 Sep 15 14 Philips Semiconductors Product specification Bus buffer/line driver; 3-state 74LVC1G125 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 2004 Sep 15 15 Philips Semiconductors Product specification Bus buffer/line driver; 3-state DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION 74LVC1G125 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2004 Sep 15 16 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2004 SCA76 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/05/pp17 Date of release: 2004 Sep 15 Document order number: 9397 750 13758