74LVC1G3157

74LVC1G3157 2-channel analog multiplexer/demultiplexer Rev. 4 — 6 December 2011 Product data sheet 1. General description The 74LVC1G3157 provides one analog multiplexer/demultiplexer with one digital select input (S), two independent inputs/outputs (Y0, Y1) and a common input/output (Z). Schmitt trigger action at the select input makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V. 2. Features and benefits  Wide supply voltage range from 1.65 V to 5.5 V  Very low ON resistance:  7.5  (typical) at VCC = 2.7 V  6.5  (typical) at VCC = 3.3 V  6  (typical) at VCC = 5 V  Switch current capability of 32 mA  Break-before-make switching  High noise immunity  CMOS low power consumption  TTL interface compatibility at 3.3 V  Latch-up performance meets requirements of JESD 78 Class I  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Control input accepts voltages up to 5.5 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 3. Ordering information Table 1. Ordering information Package Temperature range 74LVC1G3157GW 74LVC1G3157GV 74LVC1G3157GM 74LVC1G3157GF 74LVC1G3157GN 74LVC1G3157GS 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C Name SC-88 SC-74 XSON6 XSON6 XSON6 XSON6 Description plastic surface-mounted package; 6 leads plastic surface-mounted package (TSOP6); 6 leads plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.45  0.5 mm plastic extremely thin small outline package; no leads; 6 terminals; body 1  1  0.5 mm extremely thin small outline package; no leads; 6 terminals; body 0.9  1.0  0.35 mm extremely thin small outline package; no leads; 6 terminals; body 1.0  1.0  0.35 mm Version SOT363 SOT457 SOT886 SOT891 SOT1115 SOT1202 Type number 4. Marking Table 2. Marking Marking code[1] YJ YJ YJ YJ YJ YJ Type number 74LVC1G3157GW 74LVC1G3157GV 74LVC1G3157GM 74LVC1G3157GF 74LVC1G3157GN 74LVC1G3157GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y1 S Z S6 1 Y1 Z4 3 Y0 001aac354 001aac355 Y0 Fig 1. Logic symbol Fig 2. Logic diagram 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 2 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning 74LVC1G3157 74LVC1G3157 Y1 GND 1 2 6 5 S VCC Y1 1 6 S 74LVC1G3157 Y1 GND 1 2 3 6 5 4 S VCC Z GND 2 5 VCC Y0 Y0 3 001aac356 3 4 Z Y0 001aaf546 4 Z Transparent top view 001aac357 Transparent top view Fig 3. Pin configuration SOT363 and SOT457 Fig 4. Pin configuration SOT886 Fig 5. Pin configuration SOT891, SOT1115 and SOT1202 6.2 Pin description Table 3. Symbol Y1 GND Y0 Z VCC S Pin description Pin 1 2 3 4 5 6 Description independent input or output ground (0 V) independent input or output common output or input supply voltage select input 7. Functional description Table 4. Input S L H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Channel on Y0 Y1 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 3 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK ISK VSW ISW ICC IGND Tstg Ptot [1] [2] [3] Parameter supply voltage input voltage input clamping current switch clamping current switch voltage switch current supply current ground current storage temperature total power dissipation Conditions [1] Min 0.5 0.5 50 [2] Max +6.5 +6.5 50 VCC + 0.5 50 100 +150 250 Unit V V mA mA V mA mA mA C mW VI < 0.5 V or VI > VCC + 0.5 V VI < 0.5 V or VI > VCC + 0.5 V enable and disable mode VSW > 0.5 V or VSW < VCC + 0.5 V 0.5 100 65 Tamb = 40 C to +125 C [3] - The minimum input voltage rating may be exceeded if the input current rating is observed. The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed. For SC-88 and SC-74 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC VI VSW Tamb t/V Recommended operating conditions Parameter supply voltage input voltage switch voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V [1] [2] [2] Conditions Min 1.65 0 Typ - Max 5.5 5.5 VCC +125 20 10 Unit V V V C ns/V ns/V enable and disable mode [1] 0 40 - To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit for the voltage drop across the switch. Applies to control signal levels. [2] 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 4 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V II IS(OFF) input leakage current OFF-state leakage current ON-state leakage current pin S; VI = 5.5 V or GND; VCC = 0 V to 5.5 V VCC = 5.5 V; see Figure 6 [2] 40 C to +85 C Min 0.65VCC 1.7 2.0 0.7VCC Typ[1] 0.1 0.1 Max 0.35VCC 0.7 0.8 0.3VCC 2 5 40 C to +125 C Min 0.65VCC 1.7 2.0 0.7VCC Max 0.7 0.8 0.3VCC 10 20 Unit V V V V V V V A A 0.35VCC V [2] IS(ON) VCC = 5.5 V; see Figure 7 [2] - 0.1 5 - 20 A ICC supply current VI = 5.5 V or GND; VSW = GND or VCC; VCC = 1.65 V to 5.5 V additional pin S; VI = VCC  0.6 V; supply current VCC = 5.5 V; VSW = GND or VCC input capacitance OFF-state capacitance ON-state capacitance [2] - 0.1 10 - 40 A ICC CI CS(OFF) CS(ON) [2] - 5 2.5 6.0 18 500 - - 5000 - A pF pF pF [1] [2] Typical values are measured at Tamb = 25 C. These typical values are measured at VCC = 3.3 V 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 5 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 10.1 Test circuits switch 1 VIL or VIH S Z Y0 Y1 1 2 2 switch IS S VIH VIL VCC VI VO GND 001aac358 VI = VCC or GND and VO = GND or VCC. Fig 6. Test circuit for measuring OFF-state leakage current VCC S Z Y0 Y1 1 2 switch 1 S VIH VIL VIL or VIH IS VI 2 switch VO GND 001aac359 VI = VCC or GND and VO = open circuit. Fig 7. Test circuit for measuring ON-state leakage current 10.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14. Symbol RON(peak) Parameter ON resistance (peak) Conditions VI = GND to VCC; see Figure 8 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V 34.0 12.0 10.4 7.8 6.2 130 30 25 20 15 195 45 38 30 23      40 C to +85 C Min Typ[1] Max 40 C to +125 C Unit Min Max 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 6 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer Table 8. ON resistance …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 to Figure 14. Symbol RON(rail) Parameter ON resistance (rail) Conditions VI = GND; see Figure 8 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V VI = VCC; see Figure 8 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(flat) ON resistance (flatness) VI = GND to VCC ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V [1] [2] Typical values are measured at Tamb = 25 C and nominal VCC. Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. [2] 40 C to +85 C Min Typ[1] 8.2 7.1 6.9 6.5 5.8 10.4 7.6 7.0 6.1 4.9 26.0 5.0 3.5 2.0 1.5 Max 18 16 14 12 10 30 20 18 15 10 - 40 C to +125 C Unit Min Max 27 24 21 18 15 45 30 27 23 15                74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 7 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 10.3 ON resistance test circuit and graphs 40 RON (Ω) 30 VSW mna673 V VCC S Z Y0 Y1 1 2 switch 1 S VIL VIH 20 (1) VIL or VIH 2 switch (2) (3) 10 (4) ISW VI (5) GND 001aac360 0 0 1 2 3 4 VI (V) 5 RON = VSW / ISW. (1) VCC = 1.8 V. (2) VCC = 2.5 V. (3) VCC = 2.7 V. (4) VCC = 3.3 V. (5) VCC = 5.0 V. Fig 8. Test circuit for measuring ON resistance Fig 9. Typical ON resistance as a function of input voltage; Tamb = 25 C 55 RON (Ω) 45 001aaa712 15 RON (Ω) 13 001aaa708 35 (4) (3) (2) (1) 11 (1) (2) 25 9 (3) (4) 15 7 5 0 0.4 0.8 1.2 1.6 VI (V) 2.0 5 0 0.5 1.0 1.5 2.0 VI (V) 2.5 (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 10. ON resistance as a function of input voltage; VCC = 1.8 V Fig 11. ON resistance as a function of input voltage; VCC = 2.5 V 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 8 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 13 RON (Ω) 11 001aaa709 10 RON (Ω) 8 001aaa710 (1) (1) (2) 9 (2) (3) 6 (3) 7 (4) (4) 5 0 0.5 1.0 1.5 2.0 2.5 3.0 VI (V) 4 0 1 2 3 VI (V) 4 (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 12. ON resistance as a function of input voltage; VCC = 2.7 V Fig 13. ON resistance as a function of input voltage; VCC = 3.3 V 7 RON (Ω) 6 001aaa711 5 (1) (2) 4 (3) (4) 3 0 1 2 3 4 VI (V) 5 (1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = 40 C. Fig 14. ON resistance as a function of input voltage; VCC = 5.0 V 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 9 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 11. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18. Symbol Parameter tpd propagation delay Conditions Z to Yn or Yn to Z; see Figure 15 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V ten enable time S to Yn; see Figure 16 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V tdis disable time S to Yn; see Figure 16 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V tb-m break-before-make time see Figure 17 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V [1] [2] [3] [4] [5] [6] Typical values are measured at Tamb = 25 C and nominal VCC. tpd is the same as tPLH and tPHL. Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when driven by an ideal voltage source (zero output impedance). ten is the same as tPZH and tPZL. tdis is the same as tPLZ and tPHZ. Break-before-make specified by design. [6] [5] [4] [2][3] 40 C to +85 C Min 1.0 1.0 1.0 0.5 0.5 2.5 2.0 1.5 1.5 0.8 0.5 0.5 0.5 0.5 0.5 Typ[1] 8.7 5.3 4.9 4.0 3.0 6.0 4.4 4.2 3.6 2.9 Max 2 1.2 1.0 0.8 0.6 14 7.5 6.0 5.5 4.0 8.5 6.0 5.0 4.5 3.5 - 40 C to +125 C Unit Min 1.0 1.0 1.0 0.5 0.5 2.5 2.0 1.5 1.5 0.8 0.5 0.5 0.5 0.5 0.5 Max 3.0 2.0 1.5 1.5 1.0 14.0 7.5 6.0 5.5 4.0 8.5 6.0 5.0 4.5 3.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 10 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 11.1 Waveforms and test circuits VI Yn or Z input GND tPLH VOH Z or Yn output VOL 001aac361 VM VM tPHL VM VM Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 15. Input (Yn or Z) to output (Z or Yn) propagation delays VI S input GND tPLZ VCC Yn output LOW to OFF OFF to LOW VOL tPHZ VOH Yn output HIGH to OFF OFF to HIGH GND switch enabled switch disabled switch enabled 001aac362 VM tPZL VM VX tPZH VY VM Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 16. Enable and disable times Table 10. VCC 1.65 V to 5.5 V Measurement points Input VM 0.5VCC Output VM 0.5VCC VX VOL + 0.3 V VY VOH  0.3 V Supply voltage 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 11 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer VCC S Z G Y0 Y1 0.5VCC VI VO RL CL GND 001aac367 a. Test circuit VI 0.5VI 0.9VO VO tb-m 0.9VO 001aag572 b. Input and output measurement points Fig 17. Test circuit for measuring break-before-make timing VEXT VCC VI VO DUT RT CL RL RL G mna616 Test data is given in Table 11. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = External voltage for measuring switching times. Fig 18. Test circuit for measuring switching times 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 12 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer Table 11. VCC Test data Input VI VCC VCC VCC VCC VCC tr, tf  2.0 ns  2.0 ns  2.5 ns  2.5 ns  2.5 ns Load CL 50 pF 50 pF 50 pF 50 pF 50 pF RL 500  500  500  500  500  VEXT tPLH, tPHL open open open open open tPZH, tPHZ GND GND GND GND GND tPZL, tPLZ 2VCC 2VCC 2VCC 2VCC 2VCC Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol THD Parameter total harmonic distortion Conditions fi = 600 Hz to 20 kHz; RL = 600 ; CL = 50 pF; VI = 0.5 V (p-p); see Figure 19 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V f(-3dB) 3 dB frequency response RL = 50 ; CL = 5 pF; see Figure 20 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V iso isolation (OFF-state) RL = 50 ; CL = 5 pF; fi = 10 MHz; see Figure 21 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V Qinj charge injection CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ; fi = 1 MHz; RL = 1 M; see Figure 22 VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 4.5 V VCC = 5.5 V 3.3 4.1 5.0 6.4 7.5 pC pC pC pC pC 42 42 40 40 dB dB dB dB 200 300 300 300 MHz MHz MHz MHz 0.260 0.078 0.078 0.078 % % % % Min Typ Max Unit 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 13 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 11.3 Test circuits VCC 0.5VCC RL switch 10 μF switch 1 2 S VIL VIH VIL or VIH S 0.1 μF Y0 Y1 1 2 Z fi 600 Ω CL GND D 001aac363 Fig 19. Test circuit for measuring total harmonic distortion VCC 0.5VCC RL switch switch 1 2 S VIL VIH VIL or VIH S 0.1 μF Y0 Y1 1 2 Z fi 50 Ω CL GND dB 001aac364 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB. Fig 20. Test circuit for measuring the frequency response when switch is in ON-state 0.5VCC VCC 0.5VCC switch S VIH VIL 1 2 switch RL RL VIL or VIH S 0.1 μF Y0 Y1 1 2 Z fi 50 Ω CL dB GND 001aac365 Adjust fi voltage to obtain 0 dBm level at input. Fig 21. Test circuit for measuring isolation (OFF-state) 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 14 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer VCC S Z Y0 Y1 1 2 Rgen VI switch G VO RL CL Vgen GND 001aac366 a. Test circuit logic (S) off input on off VO ΔVO 001aac478 b. Input and output pulse definitions Qinj = VO  CL. VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. Fig 22. Test circuit for measuring charge injection 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 15 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 12. Package outline Plastic surface-mounted package; 6 leads SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 23. Package outline SOT363 (SC-88) 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 16 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer Plastic surface-mounted package (TSOP6); 6 leads SOT457 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 c 1 2 3 Lp e bp wM B detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.1 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT457 REFERENCES IEC JEDEC JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Fig 24. Package outline SOT457 (SC-74) 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 17 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× L1 L (2) e 6 e1 5 e1 4 6× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 Fig 25. Package outline SOT886 (XSON6) 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 18 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm SOT891 1 2 b 3 4× (1) L1 e L 6 e1 5 e1 4 6× (1) A A1 D E terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 Fig 26. Package outline SOT891 (XSON6) 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 19 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm SOT1115 1 2 b 3 (4×)(2) L1 e L 6 e1 5 e1 4 (6×)(2) A1 A D E terminal 1 index area 0 Dimensions Unit mm A(1) A1 b D E e e1 0.3 L L1 0.5 scale 1 mm max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1115 References IEC JEDEC JEITA European projection sot1115_po Issue date 10-04-02 10-04-07 Fig 27. Package outline SOT1115 (XSON6) 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 20 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm SOT1202 1 2 b 3 (4×)(2) L L1 e 6 e1 5 e1 4 (6×)(2) A1 A D E terminal 1 index area 0 Dimensions Unit mm A(1) A1 b D E e e1 L L1 0.5 scale 1 mm max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version SOT1202 References IEC JEDEC JEITA European projection sot1202_po Issue date 10-04-02 10-04-06 Fig 28. Package outline SOT1202 (XSON6) 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 21 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 13. Abbreviations Table 13. Acronym CMOS TTL HBM ESD MM DUT Abbreviations Description Complementary Metal Oxide Semiconductor Transistor-Transistor Logic Human Body Model ElectroStatic Discharge Machine Model Device Under Test 14. Revision history Table 14. Revision history Release date 20111206 Data sheet status Product data sheet Change notice Supersedes 74LVC1G3157 v.3 Document ID 74LVC1G3157 v.4 Modifications: 74LVC1G3157 v.3 74LVC1G3157 v.2 74LVC1G3157 v.1 • • Legal pages updated. Figure 17: Graphic b replaced. Product data sheet Product data sheet Product data sheet 74LVC1G3157 v.2 74LVC1G3157 v.1 - 20100916 20070918 20050207 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 22 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. © NXP B.V. 2011. All rights reserved. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or 74LVC1G3157 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 4 — 6 December 2011 23 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74LVC1G3157 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 6 December 2011 24 of 25 NXP Semiconductors 74LVC1G3157 2-channel analog multiplexer/demultiplexer 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveforms and test circuits . . . . . . . . . . . . . . 11 Additional dynamic characteristics . . . . . . . . . 13 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information. . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 December 2011 Document identifier: 74LVC1G3157