74LVC245ABQ

INTEGRATED CIRCUITS DATA SHEET 74LVC245A; 74LVCH245A Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) Product specification Supersedes data of 2002 Jun 20 2003 May 07 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) FEATURES • 5 V tolerant inputs/outputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption • Direct interface with TTL levels • Inputs accept voltages up to 5.5 V • High-impedance when VCC = 0 V • bus-hold on all data inputs (74LVCH245A only) • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V • Specified from −40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPHL/tPLH CI CI/O CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. PARAMETER propagation delay An to Bn, Bn to An input capacitance input/output capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 CONDITIONS CL = 50 pF; VCC = 3.3 V DESCRIPTION 74LVC245A; 74LVCH245A The 74LVC245A/74LVCH245A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation outputs can handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 and 5 V environment. The 74LVC245A/74LVCH245A is an octal transceiver with non-inverting 3-state bus compatible outputs in both send and receive directions. The 74LVC245A/74LVCH245A has an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated. TYPICAL 2.9 4.0 10.0 15 ns pF pF pF UNIT 2003 May 07 2 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC245AD 74LVCH245AD 74LVC245ADB 74LVCH245ADB 74LVC245APW 74LVCH245APW 74LVC245ABQ 74LVCH245ABQ FUNCTION TABLE See note 1. INPUT OE L L H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. PINNING PIN 1 2 3 4 5 6 7 8 9 10 SYMBOL DIR A0 A1 A2 A3 A4 A5 A6 A7 GND DESCRIPTION direction control input data input/output data input/output data input/output data input/output data input/output data input/output data input/output data input/output ground (0 V) 20 VCC PIN 11 12 13 14 15 16 17 18 19 SYMBOL B7 B6 B5 B4 B3 B2 B1 B0 OE DIR L H X An A=B input Z TEMPERATURE RANGE PINS −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C 20 20 20 20 20 20 20 20 PACKAGE SO20 SO20 SSOP20 SSOP20 TSSOP20 TSSOP20 DHVQFN20 DHVQFN20 74LVC245A; 74LVCH245A MATERIAL plastic plastic plastic plastic plastic plastic plastic plastic CODE SOT163-1 SOT163-1 SOT339-1 SOT339-1 SOT360-1 SOT360-1 SOT764-1 SOT764-1 INPUT/OUTPUT Bn input B=A Z DESCRIPTION data input/output data input/output data input/output data input/output data input/output data input/output data input/output data input/output output enable input (active LOW) supply voltage 2003 May 07 3 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A handbook, halfpage DIR 1 VCC 20 19 18 17 16 OE B0 B1 B2 B3 B4 B5 B6 handbook, halfpage DIR 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 GND 10 MNA173 20 VCC 19 OE 18 B0 17 B1 16 B2 A0 A1 A2 A3 A4 A5 A6 A7 2 3 4 5 245 15 B3 14 B4 13 B5 12 B6 11 B7 GND* 6 7 8 9 10 GND 11 B7 MCE182 15 14 13 12 * The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO20 and (T)SSOP20. Fig.2 Pin configuration DHVQFN20. 2003 May 07 4 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A handbook, halfpage 1 DIR OE 19 2 handbook, halfpage A0 B0 18 19 1 G3 3EN1 3EN2 3 A1 B1 4 A2 B2 A3 5 B3 6 A4 B4 7 A5 B5 8 A6 B6 9 A7 B7 17 1 2 3 4 5 6 7 8 9 MNA175 2 18 17 16 15 14 13 12 11 16 15 14 13 12 11 MNA174 Fig.3 Logic symbol (IEEE/IEC). Fig.4 Logic symbol. 2003 May 07 5 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times VCC = 1.2 to 2.7 V VCC = 2.7 to 3.6 V output HIGH or LOW state output 3-state CONDITIONS for maximum speed performance for low-voltage applications MIN. 2.7 1.2 0 0 0 −40 0 0 74LVC245A; 74LVCH245A MAX. 3.6 3.6 5.5 VCC 5.5 +125 20 10 V V V V V UNIT °C ns/V ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO20 packages: above 70 °C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation Tamb = −40 to +125 °C; note 2 VI < 0 note 1 VO > VCC or VO < 0 output 3-state; note 1 VO = 0 to VCC CONDITIONS − −0.5 − −0.5 − − −65 − MIN. −0.5 MAX. +6.5 −50 +6.5 ±50 +6.5 ±50 ±100 +150 500 V mA V mA V mA mA °C mW UNIT output HIGH or LOW state; note 1 −0.5 VCC + 0.5 V 2003 May 07 6 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −12 mA IO = −18 mA IO = −24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 12 mA IO = 24 mA ILI IOZ input leakage current 3-state output OFF-state current power off leakage supply quiescent supply current additional quiescent supply current per pin bus-hold LOW sustaining current bus-hold HIGH sustaining current VI = 5.5 V or GND; note 2 VI = VIH or VIL; VO = 5.5 V or GND; notes 2 and 3 VI or VO = 5.5 V VI = VCC or GND; IO = 0 VI = VCC − 0.6 V; IO = 0 VI = 0.8 V; notes 4, 5 and 6 VI = 2.0 V; notes 4, 5 and 6 2.7 to 3.6 2.7 3.0 3.6 3.6 − − − − − 0 − − 2.7 to 3.6 2.7 3.0 3.0 VCC − 0.2 VCC − 0.5 VCC − 0.6 VCC − 0.8 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 − − − − − − VCC (V) MIN. 74LVC245A; 74LVCH245A TYP.(1) MAX. UNIT − − 0 0.8 − − − − 0.2 0.4 0.55 ±5 ±5 V V V V V V V V V V V µA µA VCC − − − ±0.1 ±0.1 Ioff ICC ∆ICC IBH(L) IBH(H) IBH(LO) IBH(HO) 0.0 3.6 2.7 to 3.6 3.0 3.0 3.6 3.6 − − − 75 −75 500 −500 ±0.1 0.1 5 − − − − ±10 10 500 − − − − µA µA µA µA µA µA µA bus-hold LOW overdrive notes 4, 5 and 7 current bus-hold HIGH overdrive current notes 4, 5 and 7 2003 May 07 7 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +125 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = −100 µA IO = −12 mA IO = −18 mA IO = −24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 12 mA IO = 24 mA ILI IOZ input leakage current 3-state output OFF-state current power off leakage supply quiescent supply current additional quiescent supply current per in. pin bus-hold LOW sustaining current bus-hold HIGH sustaining current VI = 5.5 V or GND; note 2 VI = VIH or VIL; VO = 5.5 V or GND; notes 2 and 3 VI or VO = 5.5 V VI = VCC or GND; IO = 0 VI = VCC − 0.6 V; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 − − − − − − − − − − 2.7 to 3.6 2.7 3.0 3.0 VCC − 0.3 − 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 − − − − − − VCC (V) MIN. 74LVC245A; 74LVCH245A TYP.(1) MAX. UNIT − − 0 0.8 − − − − 0.3 0.6 0.8 ±20 ±20 V V V V V V V V V V V µA µA VCC − 0.65 − VCC − 0.75 − VCC − 1 − Ioff ICC ∆ICC 0.0 3.6 2.7 to 3.6 − − − − − − ±20 40 5000 µA µA µA IBH(L) IBH(H) IBH(LO) IBH(HO) Notes VI = 0.8 V; notes 4, 5 and 6 VI = 2.0 V; notes 4, 5 and 6 3.0 3.0 3.6 3.6 60 −60 500 −500 − − − − − − − − µA µA µA µA bus-hold LOW overdrive notes 4, 5 and 7 current bus-hold HIGH overdrive current notes 4, 5 and 7 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2. For bus-hold parts, the bus-hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. 3. For I/O ports the parameter IOZ includes the input leakage current. 4. Valid for data inputs of bus-hold parts (74LVCH245A) only. 5. For data inputs only, control inputs do not have a bus-hold circuit. 6. The specified sustaining current at the data input holds the input below the specified VI level. 7. The specified overdrive current at the data input forces the data input to the opposite logic input state. 2003 May 07 8 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns. TEST CONDITIONS SYMBOL Tamb = −40 to +85 °C tPHL/tPLH propagation delay An to Bn, Bn to An see Figs 5 and 7 1.2 2.7 3.0 to 3.6 tPZH/tPZL 3-state output enable time OE to An, OE to Bn 3-state output disable time OE to An, OE to Bn skew see Figs 6 and 7 1.2 2.7 3.0 to 3.6 tPHZ/tPLZ see Figs 6 and 7 1.2 2.7 3.0 to 3.6 tsk(0) note 2 Tamb = −40 to +125 °C tPHL/tPLH propagation delay An to Bn, Bn to An see Figs 5 and 7 1.2 2.7 3.0 to 3.6 tPZH/tPZL 3-state output enable time OE to An, OE to Bn 3-state output disable time OE to An, OE to Bn skew see Figs 6 and 7 1.2 2.7 3.0 to 3.6 tPHZ/tPLZ see Figs 6 and 7 1.2 2.7 3.0 to 3.6 tsk(0) Notes 1. Typical values are measured at VCC = 3.3 V. note 2 − 1.5 1.5 − 1.5 1.5 − 1.5 1.7 − − 1.5 1.5 − 1.5 1.5 − 1.5 1.7 − PARAMETER WAVEFORMS VCC (V) MIN. 74LVC245A; 74LVCH245A TYP. MAX. UNIT 17 3.4 2.9(1) 22 5.0 4.0(1) 12 3.6 3.4(1) − − − − − − − − − − − − 7.3 6.3 − 9.5 8.5 − 8.0 7.0 1.0 − 9.5 8.0 − 12.0 11.0 − 10.0 9.0 1.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2003 May 07 9 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) AC WAVEFORMS 74LVC245A; 74LVCH245A handbook, halfpage VI An, Bn input GND tPLH VOH Bn, An output VOL VM VM tPHL VM VM MNA176 VM = 1.5 V at VCC ≥ 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 The inputs An, Bn to outputs Bn, An propagation delays. handbook, full pagewidth VI nOE input GND tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM VM VX tPZH tPZL VM outputs disabled outputs enabled MNA362 VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5VCC at VCC < 2.7 V; VX = VOL + 0.3 V at VCC ≥ 2.7 V; VX = VOL + 0.1 V at VCC < 2.7 V; VY = VOH − 0.3 V at VCC ≥ 2.7 V; VY = VOH − 0.1 V at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 3-state enable and disable times. 2003 May 07 10 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A handbook, full pagewidth S1 VCC PULSE GENERATOR VI D.U.T. RT CL 50 pF RL 500 Ω VO RL 500 Ω 2 × VCC open GND MNA368 SWITCH POSITION TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH SWITCH open 2 x VCC GND VCC < 2.7 V 2.7 - 3.6 V VCC 2.7 V VI Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.7 Load circuitry for switching times. 2003 May 07 11 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm 74LVC245A; 74LVCH245A SOT163-1 D E A X c y HE vMA Z 20 11 Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) θ 0.9 0.4 0.035 0.016 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2003 May 07 12 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) θ Lp L 1 e bp 10 wM detail X A 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 7.4 7.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.9 0.5 θ 8 0o o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2003 May 07 13 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE vMA Z 20 11 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 10 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2003 May 07 14 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 9 vMCAB wM C y1 C C y 1 Eh 20 10 e 11 19 Dh 0 12 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 2003 May 07 15 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept: • below 220 °C for all the BGA packages and packages with a thickness ≥ 2.5mm and packages with a thickness