74LVC2G38

INTEGRATED CIRCUITS DATA SHEET 74LVC2G38 Dual 2-input NAND gate (open drain) Product specification Supersedes data of 2003 Oct 27 2004 Oct 18 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) FEATURES • Wide supply voltage range from 1.65 V to 5.5 V • 5 V tolerant outputs for interfacing with 5 V logic • High noise immunity • Complies with JEDEC standard: – JESD8-7 (1.65 V to 1.95 V) – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V). • ESD protection: – HBM EIA/JESD22-A114-B exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V. • ±24 mA output drive (VCC = 3.0 V) • CMOS low power consumption • Open drain outputs • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • Inputs accept voltages up to 5 V • Multiple package options • Specified from −40 °C to +85 °C and −40 °C to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPZL/tPLZ PARAMETER propagation delay inputs nA and nB to output nY CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω VCC = 5.0 V; CL = 50 pF; RL = 500 Ω CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. input capacitance power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 DESCRIPTION 74LVC2G38 The 74LVC2G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. These feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC2G38 provides the 2-input NAND function. The outputs of the 74LVC2G38 devices are open drain and can be connected to other open-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. TYPICAL 3.0 1.8 2.5 2.1 1.5 2.5 5 ns ns ns ns ns UNIT pF pF 2004 Oct 18 2 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74LVC2G38DP 74LVC2G38DC 74LVC2G38GM PINNING PIN 1 2 3 4 5 6 7 8 1A 1B 2Y GND 2A 2B 1Y VCC SYMBOL data input data input data output ground (0 V) data input data input data output supply voltage DESCRIPTION −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C PINS 8 8 8 PACKAGE TSSOP8 VSSOP8 XSON8 MATERIAL plastic plastic plastic nB L H L H 74LVC2G38 OUTPUT nY Z Z Z L CODE SOT505-2 SOT765-1 SOT833-1 MARKING Y38 Y38 Y38 2004 Oct 18 3 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) 74LVC2G38 38 1A 1 8 VCC 1A 1B 2Y GND 1 2 3 4 001aab829 8 7 VCC 1Y 2B 2A 1B 2 7 1Y 38 6 5 2Y 3 6 2B GND 4 5 2A 001aab830 Transparent top view Fig.1 Pin configuration TSSOP8 and VSSOP8. Fig.2 Pin configuration XSON8. handbook, halfpage 1 2 5 6 1A 1B 2A 2B handbook, halfpage 1 2 5 6 & 1Y 7 7 2Y 3 & 3 MNB129 MNB130 Fig.3 Logic symbol. Fig.4 Logic symbol (IEEE/IEC). 2004 Oct 18 4 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) 74LVC2G38 handbook, halfpage Y A B GND MNB131 Fig.5 Logic diagram (one gate). 2004 Oct 18 5 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO PARAMETER supply voltage input voltage output voltage active mode VCC = 1.65 V to 5.5 V; disable mode VCC = 0 V; Power-down mode Tamb tr, tf operating ambient temperature input rise and fall times VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V CONDITIONS 0 0 0 0 −40 0 0 MIN. 1.65 74LVC2G38 MAX. 5.5 5.5 VCC 5.5 5.5 +125 20 10 V V V V V UNIT °C ns/V ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation Tamb = −40 °C to +125 °C VI < 0 V note 1 VO > VCC or VO < 0 V active mode; notes 1 and 2 VO = 0 V to VCC CONDITIONS − −0.5 − −0.5 − − −65 − MIN. −0.5 MAX. +6.5 −50 +6.5 ±50 +6.5 +6.5 ±50 ±100 +150 300 V mA V mA V V mA mA °C mW UNIT Power-down mode; notes 1 and 2 −0.5 2004 Oct 18 6 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 °C to +85 °C; note 1 VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA ILI Ioff ICC ∆ICC input leakage current power OFF leakage current quiescent supply current additional quiescent supply current per pin VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 A VI = VCC − 0.6 V; IO = 0 A 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 0 5.5 2.3 to 5.5 − − − − − − − − − − − 0.08 0.14 0.19 0.37 0.43 ±0.1 ±0.1 0.1 5 0.65 × VCC − 1.7 2.0 0.7 × VCC − − − − − − − − − − − VCC (V) MIN. TYP. 74LVC2G38 MAX. UNIT − − − − 0.7 0.8 0.3 × VCC 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 10 500 V V V V V V V V V V V V V µA µA µA µA 0.35 × VCC V 2004 Oct 18 7 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) 74LVC2G38 TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 °C to +125 °C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA ILI Ioff ICC ∆ICC Note 1. All typical values are measured at Tamb = 25 °C. input leakage current power OFF leakage current quiescent supply current additional quiescent supply current per pin VI = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 A VI = VCC − 0.6 V; IO = 0 A 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 0 5.5 2.3 to 5.5 − − − − − − − − − − − − − − − − − − − − 0.1 0.70 0.45 0.60 0.80 0.80 ±20 ±20 40 5000 V V V V V V µA µA µA µA 0.65 × VCC − 1.7 2.0 0.7 × VCC − − − − − − − − − − − − − − − 0.7 0.8 0.3 × VCC V V V V V V V VCC (V) MIN. TYP. MAX. UNIT 0.35 × VCC V 2004 Oct 18 8 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) AC CHARACTERISTICS GND = 0 V. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 °C to +85 °C; note 1 tPZL/tPLZ propagation delay inputs nA and nB to output nY see Figs 6 and 7 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Tamb = −40 °C to +125 °C tPZL/tPLZ propagation delay inputs nA and nB to output nY see Figs 6 and 7 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Note 1. All typical values are measured at Tamb = 25 °C. AC WAVEFORMS 1.2 0.7 0.7 0.7 0.5 − − − − − 1.2 0.7 0.7 0.7 0.5 3.0 1.8 2.5 2.1 1.5 VCC (V) MIN. 74LVC2G38 TYP. MAX. UNIT 8.6 4.8 4.4 4.1 3.3 ns ns ns ns ns 10.8 6.0 5.5 5.2 4.2 ns ns ns ns ns handbook, full pagewidth VI nA, nB input GND t PLZ VCC nY output VOL VX MNB132 VM t PZL VM INPUT VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC VX VOL + 0.15 V VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VOL + 0.3 V VCC VCC 2.7 V 2.7 V VCC VI tr = tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Fig.6 Inputs nA and nB to output nY propagation delay times. 2004 Oct 18 9 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) 74LVC2G38 handbook, full pagewidth VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL MNA616 VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V VI VCC VCC 2.7 V 2.7 V VCC CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH/tPHL open open open open open tPZH/tPHZ GND GND GND GND GND tPZL/tPLZ 2 × VCC 2 × VCC 6V 6V 2 × VCC Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.7 Load circuitry for switching times. 2004 Oct 18 10 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) PACKAGE OUTLINES 74LVC2G38 TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 2004 Oct 18 11 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) 74LVC2G38 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 2004 Oct 18 12 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) 74LVC2G38 XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 0.95 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.0 0.9 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 2004 Oct 18 13 Philips Semiconductors Product specification Dual 2-input NAND gate (open drain) DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION 74LVC2G38 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2004 Oct 18 14 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2004 SCA76 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/02/pp15 Date of release: 2004 Oct 18 Document order number: 9397 750 13785