74LVC2G74DP

74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Rev. 01 — 3 November 2005 Product data sheet 1. General description The 74LVC2G74 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times. 2. Features s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) ESD protection: x HBM EIA/JESD22-A114-C exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C s s s s s s s s Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. Symbol Parameter CP to Q, Q SD to Q, Q RD to Q, Q fmax Ci CPD [1] Conditions CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V Min - Typ 3.5 3.0 3.0 280 4.0 15 Max - Unit ns ns ns MHz pF pF tPHL, tPLH propagation delay maximum input clock CL = 50 pF; VCC = 3.3 V frequency input capacitance power dissipation capacitance VCC = 3.3 V [1] [2] - CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. The condition is VI = GND to VCC. [2] 4. Ordering information Table 2: Ordering information Package Temperature range Name 74LVC2G74DP 74LVC2G74DC 74LVC2G74GT −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C TSSOP8 VSSOP8 XSON8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; body width 2.3 mm plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm Version SOT505-2 SOT765-1 SOT833-1 Type number 5. Marking Table 3: Marking Marking code V74 V74 V74 Type number 74LVC2G74DP 74LVC2G74DC 74LVC2G74GT 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 2 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 6. Functional diagram 7 SD 2 1 D CP SD D CP FF Q RD RD 6 mnb139 Q Q 5 7 1 2 S C1 1D R mnb140 5 Q 3 6 3 Fig 1. Logic symbol Fig 2. IEC logic symbol Q C C C C D C RD C C Q C SD mna421 CP C C Fig 3. Logic diagram 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 3 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 7. Pinning information 7.1 Pinning 74 CP 1 8 VCC D 2 7 SD CP D Q GND 1 2 3 4 001aab659 8 7 VCC SD RD Q Q 3 6 RD 74 6 5 GND 4 5 Q 001aab658 Transparent top view Fig 4. Pin configuration TSSOP8 and VSSOP8 Fig 5. Pin configuration XSON8 7.2 Pin description Table 4: Symbol CP D Q GND Q RD SD VCC Pin description Pin 1 2 3 4 5 6 7 8 Description clock input (LOW-to-HIGH, edge-triggered) data input complement flip-flop output ground (0 V) true flip-flop output asynchronous reset-direct input (active LOW) asynchronous set-direct input (active LOW) supply voltage 8. Functional description 8.1 Function table Table 5: Input SD L H L [1] Function table for asynchronous operation RD H L L CP X X X D X X X [1] Output Q H L H Q L H H H = HIGH voltage level; L = LOW voltage level; X = don’t care. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 74LVC2G74_1 Product data sheet Rev. 01 — 3 November 2005 4 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Function table for synchronous operation RD H H CP ↑ ↑ D L H [1] Table 6: Input SD H H [1] Output Qn+1 L H Qn+1 H L H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. 9. Limiting values Table 7: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage Conditions VI < 0 V [1] Min −0.5 −0.5 [1] [2] [1] [2] Max +6.5 −50 +6.5 ±50 +6.5 ±50 ±100 ±100 +150 250 Unit V mA V mA V mA mA mA °C mW output clamping current VO > VCC or VO < 0 V output voltage output current quiescent supply current ground current storage temperature total power dissipation Tamb = −40 °C to +125 °C active mode Power-down mode VO = 0 V to VCC −0.5 −0.5 −65 - VCC + 0.5 V The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. 10. Recommended operating conditions Table 8: Symbol VCC VI VO Recommended operating conditions Parameter supply voltage input voltage output voltage active mode Power-down mode; VCC = 0 V Tamb ∆t/∆V ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Conditions Min 1.65 0 0 0 −40 0 0 Typ Max 5.5 5.5 VCC 5.5 +125 20 10 Unit V V V V °C ns/V ns/V 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 5 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 11. Static characteristics Table 9: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIH °C [1] 0.65 × VCC 1.7 2.0 0.7 × VCC VCC − 0.1 1.2 1.9 2.2 2.3 3.8 1.54 2.15 2.50 2.62 4.11 0.07 0.12 0.17 0.33 0.39 ±0.1 ±0.1 0.1 5 4.0 0.7 0.8 0.3 × VCC 0.10 0.45 0.30 0.40 0.55 0.55 ±5 ±10 10 500 V V V V V V V V V V V V V V V V V V V µA µA µA µA pF VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-state input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-state output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-state output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V ILI IOFF ICC ∆ICC Ci input leakage current power-off leakage current VI = 5.5 V or GND; VCC = 5.5 V VI or VO = 5.5 V; VCC = 0 V Conditions Min Typ Max Unit HIGH-state input voltage VCC = 1.65 V to 1.95 V 0.35 × VCC V quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional quiescent supply current (per pin) input capacitance VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 6 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Table 9: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +125 °C VIH HIGH-state input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-state input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-state output voltage VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 5.5 V IO = −4 mA; VCC = 1.65 V IO = −8 mA; VCC = 2.3 V IO = −12 mA; VCC = 2.7 V IO = −24 mA; VCC = 3.0 V IO = −32 mA; VCC = 4.5 V VOL LOW-state output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V ILI IOFF ICC ∆ICC input leakage current power-off leakage current VI = 5.5 V or GND; VCC = 5.5 V VI or VO = 5.5 V; VCC = 0 V 0.10 0.70 0.45 0.60 0.80 0.80 ±20 ±20 40 5000 V V V V V V µA µA µA µA VCC − 0.1 0.95 1.7 1.9 2.0 3.4 V V V V V V 0.65 × VCC 1.7 2.0 0.7 × VCC 0.7 0.8 0.3 × VCC V V V V V V V Conditions Min Typ Max Unit 0.35 × VCC V quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V additional quiescent supply current (per pin) VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V [1] All typical values are measured at Tamb = 25 °C. 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 7 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 12. Dynamic characteristics Table 10: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol tPHL, tPLH Parameter °C [1] see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V SD to Q, Q see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V RD to Q, Q see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW pulse width clock CP HIGH or LOW see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V set SD (LOW) and reset RD (LOW) see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 6.2 2.7 2.7 2.7 2.0 1.6 [2] ns ns ns ns ns 6.2 2.7 2.7 2.7 2.0 1.3 [2] ns ns ns ns ns 1.5 1.0 1.0 1.0 1.0 5.0 3.5 3.5 3.0 [2] 2.5 12.9 7.0 7.0 5.9 4.1 ns ns ns ns ns 1.5 1.0 1.0 1.0 1.0 6.0 3.5 3.5 3.0 [2] 2.5 12.9 7.0 7.0 5.9 4.1 ns ns ns ns ns 1.5 1.0 1.0 1.0 1.0 6.0 3.5 3.5 3.5 [2] 2.5 13.4 7.1 7.1 5.9 4.1 ns ns ns ns ns propagation delay CP to Q, Q Conditions Min Typ Max Unit Tamb = −40 °C to +85 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 8 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Table 10: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol trec Parameter recovery time set SD or reset RD see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tsu setup time D to CP see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V th hold time D to CP see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum input clock frequency see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 80 175 175 175 200 280 [2] MHz MHz MHz MHz MHz 0.0 0.3 0.5 1.2 0.5 0.6 [2] ns ns ns ns ns 2.9 1.7 1.7 1.3 1.1 0.5 [2] ns ns ns ns ns 1.9 1.4 1.3 1.2 1.0 −3.0 [2] ns ns ns ns ns Conditions Min Typ Max Unit 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 9 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Table 10: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol tPHL, tPLH Parameter propagation delay CP to Q, Q see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V SD to Q, Q see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V RD to Q, Q see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW pulse width clock CP HIGH or LOW see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V set SD (LOW) and reset RD (LOW) see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V trec recovery time set SD or reset RD see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 74LVC2G74_1 Conditions Min Typ Max Unit Tamb = −40 °C to +125 °C 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 1.5 1.0 1.0 1.0 1.0 - 13.4 7.1 7.1 5.9 4.1 12.9 7.0 7.0 5.9 4.1 12.9 7.0 7.0 5.9 4.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6.2 2.7 2.7 2.7 2.0 6.2 2.7 2.7 2.7 2.0 - - ns ns ns ns ns ns ns ns ns ns 1.9 1.4 1.3 1.2 1.0 - - ns ns ns ns ns © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 10 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Table 10: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol tsu Parameter setup time D to CP see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V th hold time D to CP see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum input clock frequency see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V [1] [2] All typical values are measured at Tamb = 25 °C. These typical values are measured at VCC = 3.3 V. Conditions Min Typ Max Unit 2.9 1.7 1.7 1.3 1.1 - - ns ns ns ns ns 0.0 0.3 0.5 1.2 0.5 80 175 175 175 200 - - ns ns ns ns ns MHz MHz MHz MHz MHz 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 11 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 13. Waveforms VI CP input GND tW 1/fmax VI D input GND th t su t PHL VOH Q output VOL VOH Q output VOL t PLH t PHL mnb141 VM VM th t su t PLH VM VM Measurement points are given in Table 11. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drop that occur with the output load. Fig 6. The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to D hold times and the maximum clock pulse frequency Table 11: VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Output VM 0.5 × VCC 0.5 × VCC 1.5 V 1.5 V 0.5 × VCC Supply voltage 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 12 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger VI CP input GND t rec VI SD input GND tW VI RD input GND t PLH VOH Q output VOL VOH Q output VOL t PHL t PLH mnb142 VM VM tW VM t PHL VM VM Measurement points are given in Table 11. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and the RD to CP removal time VEXT VCC PULSE GENERATOR VI DUT RT CL RL RL VO mna616 Test data is given in Table 12. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 8. Load circuitry for switching times 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 13 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr = tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns ≤ 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω 500 Ω VEXT tPLH, tPHL open open open open open tPZH, tPHZ GND GND GND GND GND tPZL, tPLZ 2 × VCC 2 × VCC 6V 6V 2 × VCC Table 12: VCC Supply voltage 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 14 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 14. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E A X c y HE vMA Z 8 5 A pin 1 index A2 A1 (A3) Lp L θ 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 Fig 9. Package outline SOT505-2 (TSSOP8) 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 15 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E A X c y HE vMA Z 8 5 Q A pin 1 index A2 A1 (A3) θ Lp L 1 e bp 4 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 θ 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 Fig 10. Package outline SOT765-1 (VSSOP8) 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 16 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09 Fig 11. Package outline SOT833-1 (XSON8) 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 17 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 15. Abbreviations Table 13: Acronym CMOS TTL HBM ESD MM CDM DUT Abbreviations Description Complementary Metal Oxide Semiconductor Transistor Transistor Logic Human Body Model ElectroStatic Discharge Machine Model Charged Device Model Device Under Test 16. Revision history Table 14: Revision history Release date 20051103 Data sheet status Product data sheet Change notice Doc. number Supersedes Document ID 74LVC2G74_1 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 18 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 17. Data sheet status Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 20. Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74LVC2G74_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 3 November 2005 19 of 20 Philips Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 9 10 11 12 13 14 15 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 3 November 2005 Document number: 74LVC2G74_1 Published in The Netherlands