74LVC2T45GN

74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Rev. 4 — 20 August 2010 Product data sheet 1. General description The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA. The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state. Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid logic level. 2. Features and benefits Wide supply voltage range: VCC(A): 1.2 V to 5.5 V VCC(B): 1.2 V to 5.5 V High noise immunity Complies with JEDEC standards: JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 4000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Maximum data rates: 420 Mbps (3.3 V to 5.0 V translation) 210 Mbps (translate to 3.3 V)) 140 Mbps (translate to 2.5 V) 75 Mbps (translate to 1.8 V) 60 Mbps (translate to 1.5 V) NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II ±24 mA output drive (VCC = 3.0 V) Inputs accept voltages up to 5.5 V Low power consumption: 16 μA maximum ICC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range 74LVC2T45DC 74LVCH2T45DC 74LVC2T45GT 74LVCH2T45GT 74LVC2T45GF 74LVCH2T45GF 74LVC2T45GD 74LVCH2T45GD 74LVC2T45GM 74LVCH2T45GM 74LVC2T45GN 74LVCH2T45GN 74LVC2T45GS 74LVCH2T45GS −40 °C to +125 °C XSON8 −40 °C to +125 °C XSON8 −40 °C to +125 °C XQFN8U −40 °C to +125 °C XSON8U −40 °C to +125 °C XSON8 −40 °C to +125 °C XSON8 −40 °C to +125 °C Name VSSOP8 Description Version plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1 × 0.5 mm SOT1089 Type number plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm extremely thin small outline package; no leads; 8 terminals; body 1.2 × 1.0 × 0.35 mm extremely thin small outline package; no leads; 8 terminals; body 1.35 × 1.0 × 0.35 mm SOT902-1 SOT1116 SOT1203 4. Marking Table 2. Marking Marking code[1] V45 X45 V45 X45 V5 X5 V45 X45 V45 X45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Type number 74LVC2T45DC 74LVCH2T45DC 74LVC2T45GT 74LVCH2T45GT 74LVC2T45GF 74LVCH2T45GF 74LVC2T45GD 74LVCH2T45GD 74LVC2T45GM 74LVCH2T45GM 74LVC_LVCH2T45 Product data sheet Rev. 4 — 20 August 2010 2 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Table 2. Marking …continued Marking code[1] V5 X5 V5 X5 Type number 74LVC2T45GN 74LVCH2T45GN 74LVC2T45GS 74LVCH2T45GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram DIR 5 DIR 1A 2 1A 7 1B 1B 2A 3 2A 6 VCC(A) VCC(B) VCC(A) 001aag577 2B 2B VCC(B) 001aag578 Fig 1. Logic symbol Fig 2. Logic diagram 6. Pinning information 6.1 Pinning 74LVC2T45 74LVCH2T45 VCC(A) 1 8 VCC(B) 1A 2 7 1B 74LVC2T45 74LVCH2T45 2A VCC(A) 1A 2A GND 1 2 3 4 001aai904 3 6 2B 8 7 6 5 VCC(B) 1B 2B DIR GND 4 5 DIR 001aai905 Transparent top view Fig 3. Pin configuration SOT765-1 Fig 4. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 3 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 74LVC2T45 74LVCH2T45 terminal 1 index area VCC(B) 1 8 74LVC2T45 74LVCH2T45 VCC(A) 1A 2A GND 1 2 3 4 8 7 6 5 VCC(B) 1B 7 VCC(A) 2B 1B 2B DIR DIR 2 6 1A 3 4 5 2A GND 001aai906 001aaj617 Transparent top view Transparent top view Fig 5. Pin configuration SOT996-2 Fig 6. Pin configuration SOT902-1 6.2 Pin description Table 3. Symbol Pin description Pin SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 VCC(A) 1A 2A GND DIR 2B 1B VCC(B) 1 2 3 4 5 6 7 8 SOT902-1 7 6 5 4 3 2 1 8 supply voltage A (port A and DIR) data input or output data input or output ground (0 V) direction control data input or output data input or output supply voltage B (port B) Description 7. Functional description Table 4. Function table[1] Input DIR L H X Input/output[2] nA nA = nB input Z nB input nB = nA Z Supply voltage VCC(A), VCC(B) 1.2 V to 5.5 V 1.2 V to 5.5 V GND[3] [1] [2] [3] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. The input circuit of the data I/O is always active. When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode. 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 4 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC(A) VCC(B) IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] [3] [4] Parameter supply voltage A supply voltage B input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions Min −0.5 −0.5 Max +6.5 +6.5 +6.5 VCCO + 0.5 +6.5 ±50 100 +150 250 Unit V V mA V mA V V mA mA mA °C mW VI < 0 V [1] −50 −0.5 −50 [1][2][3] [1] [2] VO < 0 V Active mode Suspend or 3-state mode VO = 0 V to VCCO ICC(A) or ICC(B) −0.5 −0.5 −100 −65 Tamb = −40 °C to +125 °C [4] - The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed. VCCO is the supply voltage associated with the output port. VCCO + 0.5 V should not exceed 6.5 V. For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K. For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC(A) VCC(B) VI VO Tamb Δt/ΔV Recommended operating conditions Parameter supply voltage A supply voltage B input voltage output voltage ambient temperature input transition rise and fall rate VCCI = 1.2 V VCCI = 1.4 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3 V to 3.6 V VCCI = 4.5 V to 5.5 V [1] [2] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the input port. [2] Conditions Min 1.2 1.2 0 Max 5.5 5.5 5.5 VCCO 5.5 +125 20 20 20 10 5 Unit V V V V V °C ns/V ns/V ns/V ns/V ns/V Active mode Suspend or 3-state mode [1] 0 0 −40 - 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 5 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 10. Static characteristics Table 7. Typical static characteristics at Tamb = 25 °C At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH VOL II IBHL IBHH IBHLO IBHHO IOZ IOFF HIGH-level output voltage LOW-level output voltage input leakage current bus hold LOW current bus hold HIGH current bus hold LOW overdrive current bus hold HIGH overdrive current OFF-state output current power-off leakage current Conditions VI = VIH or VIL IO = −3 mA; VCCO = 1.2 V VI = VIH or VIL IO = 3 mA; VCCO = 1.2 V DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V A or B port; VI = 0.42 V; VCCI = 1.2 V A or B port; VI = 0.78 V; VCCI = 1.2 V A or B port; VCCI = 1.2 V A or B port; VCCI = 1.2 V A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V CI CI/O input capacitance input/output capacitance DIR input; VI = 0 V or 3.3 V; VCC(A) = VCC(B) = 3.3 V A and B port; suspend mode; VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V [1] [2] [1] Min - Typ 1.09 0.07 19 −19 19 −19 2.2 6.0 Max ±1 ±1 ±1 ±1 - Unit V V μA μA μA μA μA μA μA μA pF pF [2] [2] [2][3] [2][3] [1] [1] [2] [3] VCCO is the supply voltage associated with the output port. VCCI is the supply voltage associated with the data input port. To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH. 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 6 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions data input VCCI = 1.2 V VCCI = 1.4 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VCCI = 4.5 V to 5.5 V DIR input VCCI = 1.2 V VCCI = 1.4 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VCCI = 4.5 V to 5.5 V VIL LOW-level input voltage data input VCCI = 1.2 V VCCI = 1.4 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VCCI = 4.5 V to 5.5 V DIR input VCCI = 1.2 V VCCI = 1.4 V to 1.95 V VCCI = 2.3 V to 2.7 V VCCI = 3.0 V to 3.6 V VCCI = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH IO = −100 μA; VCCO = 1.2 V to 4.5 V IO = −6 mA; VCCO = 1.4 V IO = −8 mA; VCCO = 1.65 V IO = −12 mA; VCCO = 2.3 V IO = −24 mA; VCCO = 3.0 V IO = −32 mA; VCCO = 4.5 V [2] [1] [1] −40 °C to +85 °C Min 0.8VCCI 0.65VCCI 1.7 2.0 0.7VCCI 0.8VCC(A) 0.65VCC(A) 1.7 2.0 0.7VCC(A) VCCO − 0.1 1.0 1.2 1.9 2.4 3.8 Max 0.2VCCI 0.35VCCI 0.7 0.8 0.3VCCI 0.2VCC(A) 0.35VCC(A) 0.7 0.8 0.3VCC(A) - −40 °C to +125 °C Min 0.8VCCI 0.65VCCI 1.7 2.0 0.7VCCI 0.8VCC(A) 0.65VCC(A) 1.7 2.0 0.7VCC(A) VCCO − 0.1 1.0 1.2 1.9 2.4 3.8 Max 0.2VCCI 0.35VCCI 0.7 0.8 0.3VCCI Unit V V V V V V V V V V V V V V V 0.2VCC(A) V 0.35VCC(A) V 0.7 0.8 V V 0.3VCC(A) V V V V V V V 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 7 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL LOW-level output voltage Conditions VI = VIL IO = 100 μA; VCCO = 1.2 V to 4.5 V IO = 6 mA; VCCO = 1.4 V IO = 8 mA; VCCO = 1.65 V IO = 12 mA; VCCO = 2.3 V IO = 24 mA; VCCO = 3.0 V IO = 32 mA; VCCO = 4.5 V II IBHL input leakage current DIR input; VI = 0 V to 5.5 V; VCCI = 1.2 V to 5.5 V [1] [2] −40 °C to +85 °C Min Max 0.1 0.3 0.45 0.3 0.55 0.55 ±2 −40 °C to +125 °C Min Max 0.1 0.3 0.45 0.3 0.55 0.55 ±10 Unit V V V V V V μA bus hold LOW A or B port current VI = 0.49 V; VCCI = 1.4 V VI = 0.58 V; VCCI = 1.65 V VI = 0.70 V; VCCI = 2.3 V VI = 0.80 V; VCCI = 3.0 V VI = 1.35 V; VCCI = 4.5 V 15 25 45 100 100 [1] ±2 10 20 45 80 100 −10 −20 −45 −80 −100 125 200 300 500 900 −125 −200 −300 −500 −900 - ±10 μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA IBHH bus hold HIGH A or B port current VI = 0.91 V; VCCI = 1.4 V VI = 1.07 V; VCCI = 1.65 V VI = 1.60 V; VCCI = 2.3 V VI = 2.00 V; VCCI = 3.0 V VI = 3.15 V; VCCI = 4.5 V −15 −25 −45 −100 −100 [1][3] IBHLO bus hold LOW A or B port overdrive VCCI = 1.6 V current VCCI = 1.95 V VCCI = 2.7 V VCCI = 3.6 V VCCI = 5.5 V 125 200 300 500 900 [1][3] IBHHO bus hold HIGH A or B port overdrive VCCI = 1.6 V current VCCI = 1.95 V VCCI = 2.7 V VCCI = 3.6 V VCCI = 5.5 V −125 −200 −300 −500 −900 [2] IOZ OFF-state output current A or B port; VO = 0 V or VCCO; VCCO = 1.2 V to 5.5 V - 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 8 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter IOFF power-off leakage current Conditions A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V ICC supply current A port; VI = 0 V or VCCI; IO = 0 A VCC(A), VCC(B) = 1.2 V to 5.5 V VCC(A), VCC(B) = 1.65 V to 5.5 V VCC(A) = 5.5 V; VCC(B) = 0 V VCC(A) = 0 V; VCC(B) = 5.5 V B port; VI = 0 V or VCCI; IO = 0 A VCC(A), VCC(B) = 1.2 V to 5.5 V VCC(A), VCC(B) = 1.65 V to 5.5 V VCC(B) = 0 V; VCC(A) = 5.5 V VCC(B) = 5.5 V; VCC(A) = 0 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = 0 V or VCCI VCC(A), VCC(B) = 1.2 V to 5.5 V VCC(A), VCC(B) = 1.65 V to 5.5 V ΔICC additional per input; supply current VCC(A), VCC(B) = 3.0 V to 5.5 V A port; A port at VCC(A) − 0.6 V; DIR at VCC(A); B port = open DIR input; DIR at VCC(A) − 0.6 V; A port at VCC(A) or GND; B port = open B port; B port at VCC(B) − 0.6 V; DIR at GND; A port = open [1] [2] [3] [4] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH. For non bus hold parts only (74LVC2T45). [4] [4] [1] −40 °C to +85 °C Min Max ±2 −40 °C to +125 °C Min Max ±10 Unit μA - ±2 - ±10 μA −2 −2 - 8 3 2 8 3 2 −2 −2 - 8 3 2 8 3 2 μA μA μA μA μA μA μA μA - 16 4 - 16 4 μA μA - 50 50 - 75 75 μA μA - 50 - 75 μA 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 9 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 11. Dynamic characteristics Table 9. Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for waveforms see Figure 7 and Figure 8. Symbol Parameter tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay HIGH to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay OFF-state to HIGH propagation delay OFF-state to LOW propagation delay Conditions 1.2 V A to B B to A A to B B to A DIR to A DIR to B DIR to A DIR to B DIR to A DIR to B DIR to A DIR to B [1] [1] [1] [1] VCC(B) 1.5 V 8.1 9.5 7.1 8.6 9.4 9.4 7.1 7.8 17.3 15.2 18.0 16.5 1.8 V 7.0 9.0 6.0 8.1 9.4 9.0 7.1 7.7 16.7 14.1 17.1 15.4 2.5 V 5.8 8.5 5.3 7.8 9.4 7.8 7.1 6.9 15.4 12.9 15.6 14.7 3.3 V 5.3 8.3 5.2 7.6 9.4 8.4 7.1 7.6 15.9 12.4 16.0 14.6 5.0 V 5.1 8.2 5.4 7.6 9.4 7.9 7.1 7.0 15.2 12.2 15.5 14.8 10.6 10.6 10.1 10.1 9.4 12.0 7.1 9.5 20.1 17.7 22.1 19.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns [1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”. Table 10. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for waveforms see Figure 7 and Figure 8. Symbol Parameter tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay HIGH to LOW propagation delay HIGH to OFF-state propagation delay LOW to OFF-state propagation delay OFF-state to HIGH propagation delay OFF-state to LOW propagation delay Conditions 1.2 V A to B B to A A to B B to A DIR to A DIR to B DIR to A DIR to B DIR to A DIR to B DIR to A DIR to B [1] [1] [1] [1] VCC(A) 1.5 V 9.5 8.1 8.6 7.1 6.5 6.1 4.9 7.3 15.4 14.4 13.2 15.1 1.8 V 9.0 7.0 8.1 6.0 5.7 5.4 4.5 6.6 13.6 13.5 11.4 13.8 2.5 V 8.5 5.8 7.8 5.3 4.1 4.6 3.2 5.9 11.7 11.7 9.9 11.9 3.3 V 8.3 5.3 7.6 5.2 4.1 4.3 3.4 5.7 11.0 11.7 9.5 11.7 5.0 V 8.2 5.1 7.6 5.4 3.0 4.0 2.5 5.6 10.7 10.7 9.4 10.6 10.6 10.6 10.1 10.1 9.4 12.0 7.1 9.5 20.1 17.7 22.1 19.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns [1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”. 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 10 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2] Voltages are referenced to GND (ground = 0 V). Symbol Parameter CPD power dissipation capacitance Conditions 1.8 V A port: (direction A to B); B port: (direction B to A) A port: (direction B to A); B port: (direction A to B) [1] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω. VCC(A) and VCC(B) 2.5 V 3 16 3.3 V 3 16 5.0 V 4 18 2 15 Unit pF pF Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions Min VCC(A) = 1.4 V to 1.6 V tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay HIGH to LOW propagation delay A to B B to A A to B B to A 2.8 2.8 2.6 2.6 3.0 3.5 2.4 2.8 [1] [1] [1] [1] VCC(B) 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Max 21.3 21.3 19.3 19.3 18.7 24.8 11.4 18.3 39.6 32.7 44.1 38.0 19.1 17.6 17.3 15.3 17.1 24.1 10.5 17.6 Min 2.4 2.6 2.2 2.4 3.0 3.5 2.4 3.0 2.2 2.2 2.0 2.0 2.9 3.2 2.4 2.6 Max 17.6 19.1 15.3 17.3 18.7 23.6 11.4 17.2 36.3 29.0 40.9 34.0 17.7 17.7 14.3 14.3 17.1 21.9 10.5 16.0 Min 2.0 2.3 1.8 2.3 3.0 3.0 2.4 2.5 2.2 2.3 1.6 2.1 2.9 2.7 2.4 2.2 Max 13.5 14.9 11.8 13.2 18.7 11.0 11.4 9.4 24.3 24.9 24.2 30.5 9.3 16.0 8.5 12.9 17.1 11.5 10.5 9.2 Min 1.7 2.3 1.7 2.2 3.0 3.3 2.4 3.0 1.7 2.1 1.8 2.0 2.9 3.0 2.4 2.7 Max 11.8 12.4 10.9 11.3 18.7 11.3 11.4 10.1 22.5 23.2 22.6 29.6 7.2 15.5 7.1 12.6 17.1 10.3 10.5 8.4 Min 1.6 2.2 1.7 2.3 3.0 2.8 2.4 2.5 1.4 1.9 1.7 1.8 2.9 2.5 2.4 2.4 Max Unit 10.5 ns 12.0 ns 10.8 ns 11.0 ns 18.7 ns 10.3 ns 11.4 9.4 ns ns HIGH to OFF-state DIR to A propagation delay DIR to B LOW to OFF-state propagation delay DIR to A DIR to B OFF-state to HIGH DIR to A propagation delay DIR to B OFF-state to LOW propagation delay DIR to A DIR to B A to B B to A A to B B to A 2.6 2.4 2.4 2.2 2.9 3.2 2.4 2.5 21.4 ns 21.9 ns 21.3 ns 29.5 ns 6.8 7.0 ns ns VCC(A) = 1.65 V to 1.95 V tPLH tPHL tPHZ tPLZ LOW to HIGH propagation delay HIGH to LOW propagation delay 15.1 ns 12.2 ns 17.1 ns 8.2 7.1 ns ns 10.5 ns HIGH to OFF-state DIR to A propagation delay DIR to B LOW to OFF-state propagation delay DIR to A DIR to B 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 11 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions Min tPZH tPZL OFF-state to HIGH DIR to A propagation delay DIR to B OFF-state to LOW propagation delay DIR to A DIR to B A to B B to A A to B B to A [1] [1] [1] [1] VCC(B) 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Max 35.2 29.6 39.4 34.4 17.9 13.5 15.8 11.8 8.1 22.5 5.8 14.6 28.1 23.7 34.3 23.9 17.1 11.8 15.6 10.9 7.3 18.0 5.6 13.6 25.4 22.7 28.9 22.9 16.6 10.5 15.3 10.8 5.4 17.3 Min 2.3 2.2 2.1 1.9 2.1 3.0 1.7 2.5 2.1 1.7 2.0 1.8 2.3 2.9 2.0 2.4 1.9 1.4 1.8 1.7 1.7 2.9 Max 33.7 28.2 36.2 31.4 16.0 9.3 12.9 8.5 8.1 21.4 5.8 13.2 22.5 21.8 29.9 21.0 15.5 7.2 12.6 7.1 7.3 16.5 5.6 12.5 19.7 21.1 23.6 19.9 15.1 6.8 12.2 7.0 5.4 16.1 Min 1.5 1.5 1.4 1.4 2.1 2.5 1.7 2.0 1.4 1.3 1.3 1.3 2.3 2.3 2.0 1.9 1.0 1.0 1.0 0.9 1.7 2.3 Max 25.2 19.8 24.4 25.6 8.5 8.5 7.5 7.5 8.1 11.0 5.8 9.0 17.5 14.3 18.5 15.6 8.0 6.2 7.0 5.4 7.3 10.1 5.6 7.8 14.0 13.6 15.5 14.3 7.5 4.8 6.2 4.6 5.4 9.7 Min 1.3 1.4 1.3 1.3 2.1 2.8 1.7 2.5 0.8 0.7 0.8 0.8 2.3 2.7 2.0 2.3 0.7 0.7 0.7 0.7 1.7 2.7 Max 23.9 17.7 22.9 24.2 6.2 8.0 5.4 7.0 8.1 9.3 5.8 8.4 16.4 12.0 16.3 13.5 5.6 5.6 5.0 5.0 7.3 8.6 5.6 7.1 12.7 11.2 13.6 12.3 5.4 4.4 4.5 4.0 5.4 8.0 Min 1.1 1.0 0.9 0.9 2.1 2.3 1.7 1.8 0.7 0.6 0.7 0.7 2.7 2.2 2.0 1.7 0.5 0.5 0.5 0.5 1.7 2.5 Max 2.3 2.0 2.3 1.8 2.1 3.0 1.7 2.3 Unit 22.2 ns 17.3 ns 20.4 ns 24.1 ns 4.8 7.5 4.6 6.2 8.1 6.9 5.8 5.8 ns ns ns ns ns ns ns ns VCC(A) = 2.3 V to 2.7 V tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay HIGH to LOW propagation delay HIGH to OFF-state DIR to A propagation delay DIR to B LOW to OFF-state propagation delay DIR to A DIR to B [1] [1] [1] [1] OFF-state to HIGH DIR to A propagation delay DIR to B OFF-state to LOW propagation delay DIR to A DIR to B A to B B to A A to B B to A 2.3 1.7 2.2 1.7 2.3 2.9 2.0 2.3 13.3 ns 10.6 ns 13.1 ns 12.7 ns 4.4 5.4 4.0 4.5 7.3 6.3 5.6 4.9 ns ns ns ns ns ns ns ns VCC(A) = 3.0 V to 3.6 V tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay HIGH to LOW propagation delay HIGH to OFF-state DIR to A propagation delay DIR to B LOW to OFF-state propagation delay DIR to A DIR to B [1] [1] [1] [1] OFF-state to HIGH DIR to A propagation delay DIR to B OFF-state to LOW propagation delay DIR to A DIR to B A to B B to A A to B B to A 2.2 1.6 2.3 1.7 1.7 2.9 10.3 ns 10.0 ns 10.8 ns 11.3 3.9 3.9 3.5 3.5 5.4 5.7 ns ns ns ns ns ns ns VCC(A) = 4.5 V to 5.5 V tPLH tPHL tPHZ LOW to HIGH propagation delay HIGH to LOW propagation delay HIGH to OFF-state DIR to A propagation delay DIR to B 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 12 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions Min tPLZ tPZH tPZL LOW to OFF-state propagation delay DIR to A DIR to B [1] [1] [1] [1] VCC(B) 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Max 3.7 13.1 23.6 20.3 28.1 20.7 Min 1.4 2.4 Max 3.7 12.1 18.9 18.8 23.1 17.6 Min 1.3 1.9 Max 3.7 7.4 12.2 11.2 14.3 11.6 Min 1.0 2.3 Max 3.7 7.0 11.4 9.1 12.0 9.9 Min 0.9 1.8 Max 3.7 4.5 8.4 7.6 9.2 8.9 1.4 2.3 - Unit ns ns ns ns ns ns OFF-state to HIGH DIR to A propagation delay DIR to B OFF-state to LOW propagation delay DIR to A DIR to B [1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”. Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions Min VCC(A) = 1.4 V to 1.6 V tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay HIGH to LOW propagation delay A to B B to A A to B B to A 2.5 2.5 2.3 2.3 2.7 3.1 2.1 2.5 [1] [1] [1] [1] VCC(B) 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Max 23.5 23.5 21.3 21.3 20.6 27.3 12.6 20.2 43.7 36.1 48.6 41.9 21.1 19.4 19.1 16.9 18.9 26.6 11.6 19.4 38.8 32.7 Min 2.1 2.3 1.9 2.1 2.7 3.1 2.1 2.7 1.9 1.9 1.8 1.8 2.6 2.8 2.1 2.3 Max 19.4 21.1 16.9 19.1 20.6 26.0 12.6 19.0 40.1 32.0 45.1 37.5 19.5 19.5 15.8 15.8 18.9 24.1 11.6 17.6 37.1 31.1 Min 1.8 2.0 1.6 2.0 2.7 2.7 2.1 2.2 1.9 2.0 1.4 1.8 2.6 2.4 2.1 1.9 Max 14.9 16.4 13.0 14.6 20.6 12.1 12.6 10.4 26.8 27.5 26.7 33.6 10.3 17.6 9.4 14.2 18.9 12.7 11.6 10.2 27.8 21.9 Min 1.5 2.0 1.5 1.9 2.7 2.9 2.1 2.7 1.5 1.8 1.6 1.8 2.6 2.7 2.1 2.4 Max 13.0 13.7 12.0 12.5 20.6 12.5 12.6 11.2 24.9 25.6 25.0 32.6 8.0 17.1 7.9 13.9 18.9 11.4 11.6 9.3 26.4 19.6 Min 1.4 1.9 1.5 2.0 2.7 2.5 2.1 2.2 1.2 1.7 1.5 1.6 2.6 2.2 2.1 2.1 Max 11.6 11.9 Unit ns ns 13.2 ns 12.1 ns 20.6 ns 11.4 ns 12.6 ns 10.4 ns 23.6 ns 24.2 ns 23.5 ns 32.5 ns 7.5 7.7 ns ns HIGH to OFF-state DIR to A propagation delay DIR to B LOW to OFF-state propagation delay DIR to A DIR to B OFF-state to HIGH DIR to A propagation delay DIR to B OFF-state to LOW propagation delay DIR to A DIR to B A to B B to A A to B B to A 2.3 2.1 2.1 1.9 2.6 2.8 2.1 2.2 VCC(A) = 1.65 V to 1.95 V tPLH tPHL tPHZ tPLZ tPZH LOW to HIGH propagation delay HIGH to LOW propagation delay 16.7 ns 13.5 ns 18.9 ns 9.1 11.6 7.9 ns ns ns HIGH to OFF-state DIR to A propagation delay DIR to B LOW to OFF-state propagation delay DIR to A DIR to B [1] [1] OFF-state to HIGH DIR to A propagation delay DIR to B - 24.6 ns 19.1 ns 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 13 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions Min tPZL OFF-state to LOW propagation delay DIR to A DIR to B A to B B to A A to B B to A [1] [1] VCC(B) 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Max 43.5 38.0 19.7 14.9 17.4 13.0 9.0 24.8 6.4 16.1 31.0 26.1 37.8 26.4 18.9 13.0 17.2 12.0 8.1 19.8 6.2 15.0 28.0 25.1 31.8 25.3 18.3 11.6 16.9 11.9 6.0 19.1 4.1 14.5 Min 2.0 1.9 1.8 1.7 1.8 2.7 1.5 2.2 1.8 1.5 1.8 1.6 2.0 2.6 1.8 2.1 1.7 1.2 1.6 1.5 1.5 2.6 1.2 2.1 Max 39.9 34.7 17.6 10.3 14.2 9.4 9.0 23.6 6.4 14.6 24.9 24.0 33.0 23.2 17.1 8.0 13.9 7.9 8.1 18.2 6.2 13.8 21.8 23.3 26.1 22.0 16.7 7.5 13.5 7.7 6.0 17.8 4.1 13.4 Min 1.3 1.3 1.2 1.2 1.8 2.2 1.5 1.8 1.2 1.1 1.1 1.1 2.0 2.0 1.8 1.7 0.9 0.9 0.9 0.8 1.5 2.0 1.1 1.7 Max 26.9 28.3 9.4 9.4 8.3 8.3 9.0 12.1 6.4 9.9 19.3 15.8 20.4 17.3 8.8 6.9 7.7 6.0 8.1 11.2 6.2 8.6 15.5 15.0 17.2 15.8 8.3 5.3 6.9 5.1 6.0 10.7 4.1 8.2 Min 1.1 1.2 1.1 1.1 1.8 2.5 1.5 2.2 0.7 0.6 0.7 0.7 2.0 2.4 1.8 2.0 0.6 0.6 0.6 0.6 1.5 2.4 0.9 2.0 Max 25.3 26.8 6.9 8.8 6.0 7.7 9.0 10.3 6.4 9.3 18.1 13.3 18.0 15.0 6.2 6.2 5.5 5.5 8.1 9.5 6.2 7.9 14.1 12.4 15.0 13.6 6.0 4.9 5.0 4.4 6.0 8.8 4.1 7.7 Min 0.9 0.9 0.8 0.8 1.8 2.0 1.5 1.6 0.6 0.5 0.6 0.6 2.4 1.9 1.8 1.5 0.4 0.4 0.4 0.4 1.5 2.2 0.8 1.6 Max 2.0 1.8 2.0 1.6 1.8 2.7 1.5 2.0 Unit 22.6 ns 26.6 ns 5.3 8.3 5.1 6.9 9.0 7.6 6.4 6.4 11.7 ns ns ns ns ns ns ns ns ns VCC(A) = 2.3 V to 2.7 V tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay HIGH to LOW propagation delay HIGH to OFF-state DIR to A propagation delay DIR to B LOW to OFF-state propagation delay DIR to A DIR to B [1] [1] [1] [1] OFF-state to HIGH DIR to A propagation delay DIR to B OFF-state to LOW propagation delay DIR to A DIR to B A to B B to A A to B B to A 2.0 1.5 1.9 1.5 2.0 2.6 1.8 2.0 14.7 ns 14.5 ns 14.1 ns 4.9 6.0 4.4 5.0 8.1 7.0 6.2 5.4 11.4 11.1 ns ns ns ns ns ns ns ns ns ns VCC(A) = 3.0 V to 3.6 V tPLH tPHL tPHZ tPLZ tPZH tPZL LOW to HIGH propagation delay HIGH to LOW propagation delay HIGH to OFF-state DIR to A propagation delay DIR to B LOW to OFF-state propagation delay DIR to A DIR to B [1] [1] [1] [1] OFF-state to HIGH DIR to A propagation delay DIR to B OFF-state to LOW propagation delay DIR to A DIR to B A to B B to A A to B B to A 1.9 1.4 2.0 1.5 1.5 2.6 1.2 2.0 12.0 ns 12.5 ns 4.3 4.3 3.9 3.9 6.0 6.3 4.1 5.0 ns ns ns ns ns ns ns ns VCC(A) = 4.5 V to 5.5 V tPLH tPHL tPHZ tPLZ LOW to HIGH propagation delay HIGH to LOW propagation delay HIGH to OFF-state DIR to A propagation delay DIR to B LOW to OFF-state propagation delay DIR to A DIR to B 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 14 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8. Symbol Parameter Conditions Min tPZH tPZL OFF-state to HIGH DIR to A propagation delay DIR to B OFF-state to LOW propagation delay DIR to A DIR to B [1] [1] [1] [1] VCC(B) 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V Max 26.1 22.4 31.0 22.9 Min Max 20.9 20.8 25.5 19.5 Min Max 13.5 12.4 15.8 12.9 Min Max 12.6 10.1 13.2 11.0 Min Max 9.3 8.4 9.9 - Unit ns ns ns 10.2 ns [1] tPZH and tPZL are calculated values using the formula shown in Section 14.4 “Enable times”. 12. Waveforms VI nA, nB input GND tPHL VOH nB, nA output VOL VM 001aaj644 VM tPLH Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The data input (A, B) to output (B, A) propagation delay times VI DIR input GND t PLZ output LOW-to-OFF OFF-to-LOW VCCO VM VOL t PHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled 001aae968 VM t PZL VX t PZH VY VM Measurement points are given in Table 14. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Enable and disable times 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 15 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state Table 14. Measurement points Input[1] VM 0.5VCCI 0.5VCCI 0.5VCCI Output[2] VM 0.5VCCO 0.5VCCO 0.5VCCO VX VOL + 0.1 V VOL + 0.15 V VOL + 0.3 V VY VOH − 0.1 V VOH − 0.15 V VOH − 0.3 V Supply voltage VCC(A), VCC(B) 1.2 V to 1.6 V 1.65 V to 2.7 V 3.0 V to 5.5 V [1] [2] VCCI is the supply voltage associated with the data input port. VCCO is the supply voltage associated with the output port. VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VEXT VCC VI VO RL VM VI positive pulse 0V VM G RT DUT CL RL 001aae331 Test data is given in Table 15. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 9. Table 15. Test circuit for measuring switching times Test data Input VI[1] VCCI Δt/ΔV[2] ≤ 1.0 ns/V Load CL 15 pF RL 2 kΩ VEXT tPLH, tPHL open tPZH, tPHZ GND tPZL, tPLZ[3] 2VCCO Supply voltage VCC(A), VCC(B) 1.2 V to 5.5 V [1] [2] [3] VCCI is the supply voltage associated with the data input port. dV/dt ≥ 1.0 V/ns. VCCO is the supply voltage associated with the output port. 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 16 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 13. Typical propagation delay characteristics 001aai907 001aai908 14 tPHL (ns) 12 10 8 6 4 2 0 0 5 10 15 20 25 14 tPLH (ns) 12 10 (1) (1) (2) (2) (3) (4) (5) (6) 8 6 4 2 0 (3) (4) (5) (6) 30 35 CL (pF) 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 14 tPHL (ns) 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) 001aai909 b. LOW to HIGH propagation delay (A to B) 14 tPLH (ns) 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) 001aai910 (1) (2) (3) (4) (5) (6) (1) (2) (3) (4) (5) (6) c. HIGH to LOW propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. d. LOW to HIGH propagation delay (B to A) Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.2 V 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 17 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 14 tPHL (ns) 12 10 8 001aai911 14 tPLH (ns) 12 10 8 001aai912 (1) (1) (2) (3) (2) 6 4 (3) (4) 6 4 (4) (5) (6) (5) 2 0 0 5 10 15 20 25 (6) 2 0 30 35 CL (pF) 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 14 tPHL (ns) 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) (1) (2) (3) (4) (5) (6) 001aai913 b. LOW to HIGH propagation delay (A to B) 14 tPLH (ns) 12 10 (1) 001aai914 8 6 4 2 0 0 5 10 15 20 25 (2) (3) (4) (5) (6) 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. d. LOW to HIGH propagation delay (B to A) Fig 11. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.5 V 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 18 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 14 tPHL (ns) 12 10 001aai915 14 tPLH (ns) 12 10 001aai916 (1) (1) 8 (2) 8 (2) 6 (3) 6 (4) (5) (6) (3) (4) (5) (6) 4 2 0 0 5 10 15 20 25 4 2 0 30 35 CL (pF) 0 5 10 15 20 25 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 14 tPHL (ns) 12 10 8 (1) 001aai917 b. LOW to HIGH propagation delay (A to B) 14 tPLH (ns) 12 10 8 6 4 2 0 001aai918 (1) (2) (3) (4) (5) (6) 6 4 2 0 0 5 10 15 20 25 (2) (3) (4) (5) (6) 30 35 CL (pF) 0 5 10 15 20 25 30 35 CL (pF) c. HIGH to LOW propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. d. LOW to HIGH propagation delay (B to A) Fig 12. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 1.8 V 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 19 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 14 tPHL (ns) 12 10 001aai919 14 tPLH (ns) 12 10 001aai920 (1) (1) 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) (2) (3) (4) (5) (6) 8 (2) 6 (3) 4 2 0 0 5 10 15 20 25 (4) (5) (6) 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 14 tPHL (ns) 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) 001aai921 b. LOW to HIGH propagation delay (A to B) 14 tPLH (ns) 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) (1) (2) (3) (4) (5) (6) 001aai922 (1) (2) (3) (4) (5) (6) c. HIGH to LOW propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. d. LOW to HIGH propagation delay (B to A) Fig 13. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 2.5 V 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 20 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 14 tPHL (ns) 12 10 001aai923 14 tPLH (ns) 12 10 001aai924 (1) (1) 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) (2) (3) (4) (5) (6) 8 (2) 6 (3) 4 2 0 0 5 10 15 20 25 (4) (5) (6) 30 35 CL (pF) a. HIGH to LOW propagation delay (A to B) 14 tPHL (ns) 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) 001aai925 b. LOW to HIGH propagation delay (A to B) 14 tPLH (ns) 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) 001aai926 (1) (2) (3) (4) (5) (6) (1) (2) (3) (4) (5) (6) c. HIGH to LOW propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. d. LOW to HIGH propagation delay (B to A) Fig 14. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 3.3 V 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 21 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 14 tPHL (ns) 12 10 001aai927 14 tPLH (ns) 12 10 001aai928 (1) (1) 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) (2) (3) (4) (5) (6) 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) (2) (3) (4) (5) (6) a. HIGH to LOW propagation delay (A to B) 14 tPHL (ns) 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) 001aai929 b. LOW to HIGH propagation delay (A to B) 14 tPLH (ns) 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 CL (pF) 001aai930 (1) (2) (3) (4) (5) (6) (1) (2) (3) (4) (5) (6) c. HIGH to LOW propagation delay (B to A) (1) VCC(B) = 1.2 V. (2) VCC(B) = 1.5 V. (3) VCC(B) = 1.8 V. (4) VCC(B) = 2.5 V. (5) VCC(B) = 3.3 V. (6) VCC(B) = 5.0 V. d. LOW to HIGH propagation delay (B to A) Fig 15. Typical propagation delay versus load capacitance; Tamb = 25 °C; VCC(A) = 5 V 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 22 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state 14. Application information 14.1 Unidirectional logic level-shifting application The circuit given in Figure 16 is an example of the 74LVC2T45; 74LVCH2T45 being used in an unidirectional logic level-shifting application. VCC1 VCC1 VCC(A) 1A 1 2 8 7 VCC(B) 1B VCC2 VCC2 74LVC2T45 2A 2B 3 74LVCH2T45 6 VCC1 GND 4 5 DIR VCC2 system-1 system-2 001aai931 Fig 16. Unidirectional logic level-shifting application Table 16. Pin 1 2 3 4 5 6 7 8 Description of unidirectional logic level-shifting application Name VCC(A) 1A 2A GND DIR 2B 1B VCC(B) Function VCC1 OUT OUT GND DIR IN IN VCC2 Description supply voltage of system-1 (1.2 V to 5.5 V) output level depends on VCC1 voltage output level depends on VCC1 voltage device GND the GND (LOW level) determines B port to A port direction input threshold value depends on VCC2 voltage input threshold value depends on VCC2 voltage supply voltage of system-2 (1.2 V to 5.5 V) 14.2 Bidirectional logic level-shifting application Figure 17 shows the 74LVC2T45; 74LVCH2T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. 74LVC_LVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 20 August 2010 23 of 36 NXP Semiconductors 74LVC2T45; 74LVCH2T45 Dual supply translating transceiver; 3-state VCC1 I/O-1 PULL-UP/DOWN VCC1 VCC(A) 1A 2A GND 1 2 8 7 VCC(B) 1B VCC2 PULL-UP/DOWN VCC2 I/O-2 74LVC2T45 2B 3 74LVCH2T45 6 4 5 DIR DIR CTRL DIR CTRL system-1 system-2 001aai932 Pull-up or pull-down only needed for 74LVC2T45. Fig 17. Bidirectional logic level-shifting application Table 17 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 17. State 1 2 3 4 [1] Description of bidirectional logic level-shifting application[1] DIR CTRL H H L L I/O-1 output Z Z input I/O-2 input Z Z output Description system-1 data to system-2 system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on bus hold DIR bit is set LOW. I/O-1 and I/O-2 still are disabled. The bus-line state depends on bus hold system-2 data to system-1 H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 14.3 Power-up considerations The device is designed such that no special power-up sequence is required other than GND being applied first. Table 18. VCC(A) 0V 1.8 V 2.5 V 3.3 V 5.0 V Typical total supply current (ICC(A) + ICC(B)) VCC(B) 0V 0