74LVC38ABQ

INTEGRATED CIRCUITS DATA SHEET 74LVC38A Quad 2-input NAND gate (open drain) Product specification Supersedes data of 2004 Mar 10 2004 Mar 22 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) FEATURES • 5 V tolerant inputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption • Direct interface with TTL levels • Open-drain outputs • Inputs accept voltages up to 5.5 V • Complies with JEDEC standard no. 8-1A • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION 74LVC38A The 74LVC38A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment. The 74LVC38A provides the 2-input NAND function. The outputs of the 74LVC38A devices are open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPZL tPLZ CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74LVC38AD 74LVC38ADB 74LVC38APW 74LVC38ABQ −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C PINS 14 14 14 14 PACKAGE SO14 SSOP14 TSSOP14 DHVQFN14 MATERIAL plastic plastic plastic plastic CODE SOT108-1 SOT337-1 SOT402-1 SOT762-1 PARAMETER propagation delay nA, nB to nY propagation delay nA, nB to nY input capacitance power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 CONDITIONS CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V TYPICAL 1.7 2.3 4.0 5.5 UNIT ns ns pF pF 2004 Mar 22 2 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) FUNCTION TABLE See note 1. INPUTS nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level: Z = high-impedance OFF-state. PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC SYMBOL data input data input data output data input data input data output ground (0 V) data output data input data input data output data input data input supply voltage DESCRIPTION nB L H L H 74LVC38A OUTPUTS nY Z Z Z L 2004 Mar 22 3 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) 74LVC38A handbook, halfpage handbook, halfpage 1A 1 VCC 14 13 12 4B 4A 4Y 3B 3A 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 MNA696 14 VCC 13 4B 12 4A 1B 1Y 2A 2B 2Y 2 3 4 5 6 7 Top view GND 8 3Y 38 11 4Y 10 3B 9 3A GND(1) 11 10 9 8 3Y MNA977 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO14 and (T)SSOP14. Fig.2 Pin configuration (DHVQFN14). handbook, halfpage handbook, halfpage 1 2 & 3 1 2 4 5 9 10 12 13 1A 1B 2A 2B 3A 3B 4A 4B 1Y 3 4 & 6 2Y 6 5 9 10 3Y 8 & 8 4Y 11 12 13 & 11 MNA697 MNA698 Fig.3 Logic symbol. Fig.4 Logic symbol (IEEE/IEC). 2004 Mar 22 4 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) 74LVC38A handbook, halfpage Y A B GND MNA699 Fig.5 Logic diagram (one gate). RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times VCC = 1.2 to 2.7 V VCC = 2.7 to 3.6 V CONDITIONS for maximum speed performance for low-voltage applications MIN. 2.7 1.2 0 0 −40 0 0 MAX. 3.6 3.6 5.5 5.5 +125 20 10 V V V V °C ns/V ns/V UNIT LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO14 packages: above 70 °C derate linearly with 8 mW/K. For (T)SSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. 2004 Mar 22 5 PARAMETER supply voltage input diode current input voltage output diode current output voltage output sink current VCC or GND current storage temperature power dissipation Tamb = −40 to +125 °C; note 2 VI < 0 note 1 VO < 0 note 1 VO = 0 to VCC CONDITIONS − −0.5 − −0.5 − − −65 − MIN. −0.5 MAX. +6.5 −50 +6.5 −50 +6.5 50 ±100 +150 500 V mA V mA V mA mA °C mW UNIT Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = −40 to +85 °C; note 1 VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 12 mA IO = 24 mA ILI IOZ ICC ∆ICC input leakage current 3-state output OFF-state current quiescent supply current VI = 5.5 V or GND VI = VIH or VIL; VO = 5.5 V or GND VI = VCC or GND; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 3.6 2.7 to 3.6 − − − − − − − GND − − ±0.1 0.1 0.1 5 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 − − − − − − VCC (V) MIN. TYP. 74LVC38A MAX. UNIT − − GND 0.8 0.20 0.40 0.55 ±5 ±10 10 500 V V V V V V V µA µA µA µA additional quiescent supply VI = VCC − 0.6 V; IO = 0 current per input pin Tamb = −40 to +125 °C VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL IO = 100 µA IO = 12 mA IO = 24 mA ILI IOZ ICC ∆ICC Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. input leakage current 3-state output OFF-state current quiescent supply current VI = 5.5 V or GND VI = VIH or VIL; VO = 5.5 V or GND VI = VCC or GND; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 3.6 2.7 to 3.6 − − − − − − − − − − − − − − 0.3 0.6 0.8 ±20 ±20 40 5000 V V V µA µA µA µA 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 − − − − − − − − GND 0.8 V V V V additional quiescent supply VI = VCC − 0.6 V; IO = 0 current per input pin 2004 Mar 22 6 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = −40 to +85 °C; note 1 tPZL propagation delay nA, nB to nY see Figs 6 and 7 1.2 2.7 3.0 to 3.6 tPLZ propagation delay nA, nB to nY see Figs 6 and 7 1.2 2.7 3.0 to 3.6 tsk(0) skew note 3 Tamb = −40 to +125 °C tPZL propagation delay nA, nB to nY see Figs 6 and 7 1.2 2.7 3.0 to 3.6 tPLZ propagation delay nA, nB to nY see Figs 6 and 7 1.2 2.7 3.0 to 3.6 tsk(0) Notes 1. All typical values are measured at Tamb = 25 °C. 2. These typical values are measured at VCC = 3.3 V. skew note 3 − 0.5 0.5 − 1.0 1.0 − − − − − − − − − 0.5 0.5 − 1.0 1.0 − 5.7 1.7 1.7(2) 4.8 2.6 2.3(2) − VCC (V) MIN. TYP 74LVC38A MAX. UNIT − 2.9 3.0 − 3.8 3.6 1.0 − 4.0 4.0 − 5.0 4.5 1.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2004 Mar 22 7 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) AC WAVEFORMS 74LVC38A handbook, full pagewidth VI nA, nB input GND t PLZ VCC nY output VOL(2) VX (3) MNA700 VM (1) t PZL VM (1) (1) VM = 1.5 V at VCC ≥ 2.7 V. VM = 0.5VCC at VCC < 2.7 V. (2) VOL and VOH are typical output voltage drop that occur with the output load. (3) VX = VOL + 0.3 V at VCC ≥ 2.7 V. VX = VOL + 0.15 V at VCC < 2.7 V. Fig.6 The input nA, nB to output nY propagation delays. handbook, full pagewidth VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL MNA616 VCC 1.2 2.7 3.3 to 3.6 Note 6V 6V VEXT 2 × VCC VI VCC 2.7 V 2.7 V CL 30 pF 50 pF 50 pF RL 500 Ω(1) 500 Ω 500 Ω 1. The circuit performs better when RL = 1000 Ω. Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. tr = tf ≤ 2.5 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor. Fig.7 Load circuitry for switching times. 2004 Mar 22 8 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm 74LVC38A SOT108-1 D E A X c y HE vMA Z 14 8 Q A2 A1 pin 1 index θ Lp 1 e bp 7 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 θ 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 0.028 0.004 0.012 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2004 Mar 22 9 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) 74LVC38A SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E A X c y HE vM A Z 14 8 Q A2 A1 pin 1 index Lp L 1 bp 7 wM detail X (A 3) θ A e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2004 Mar 22 10 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) 74LVC38A TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE vMA Z 14 8 Q A2 pin 1 index A1 θ Lp L (A 3) A 1 e bp 7 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 2004 Mar 22 11 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) 74LVC38A DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 vMCAB wM C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 2004 Mar 22 12 Philips Semiconductors Product specification Quad 2-input NAND gate (open drain) DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION 74LVC38A This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2004 Mar 22 13 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2004 SCA76 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R20/03/pp14 Date of release: 2004 Mar 22 Document order number: 9397 750 13029