74LVT16500ADL

74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Rev. 03 — 29 May 2006 Product data sheet 1. General description The 74LVT16500A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW). Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2. Features I I I I I I I I I I I I I 18-bit bidirectional bus interface 3-state buffers Output capability: +64 mA and −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion/extraction permitted Power-up reset Power-up 3-state No bus current loading when output is tied to 5 V bus Negative edge-triggered clock inputs Latch-up protection: N JESD78: exceeds 500 mA ESD protection: N MIL STD 883 Method 3015: exceeds 2000 V N CDM JESD22-C101-C exceeds 1000 V Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVT16500ADGG 74LVT16500ADL −40 °C to +85 °C −40 °C to +85 °C TSSOP56 SSOP56 Description plastic thin shrink small outline package; 56 leads; body width 6.1 mm plastic shrink small outline package; 56 leads; body width 7.5 mm Version SOT364-1 SOT371-1 Type number 4. Functional diagram 1 OEAB 55 CPAB 2 LEAB 27 OEBA 30 CPBA 28 LEBA 30 28 27 55 2 CPBA LEBA OEBA LEAB CPAB 1 OEAB A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 EN1 2C3 C3 G2 EN4 5C6 C6 G5 3D 4 1 1 1 6D 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 001aaf038 001aaf039 Fig 1. Logic symbol Fig 2. IEC logic symbol 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 2 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state OEAB CPAB LEAB LEBA CPBA OEBA A0 1 55 2 28 30 27 3 1D C1 CLK 1D C1 CLK 54 B0 to 17 other channels 001aaf035 Fig 3. Logic diagram 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 3 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 5. Pinning information 5.1 Pinning 74LVT16500A OEAB LEAB A0 GND A1 A2 VCC A3 A4 1 2 3 4 5 6 7 8 9 56 GND 55 CPAB 54 B0 53 GND 52 B1 51 B2 50 VCC 49 B3 48 B4 47 B5 46 GND 45 B6 44 B7 43 B8 42 B9 41 B10 40 B11 39 GND 38 B12 37 B13 36 B14 35 VCC 34 B15 33 B16 32 GND 31 B17 30 CPBA 29 GND 001aaf040 A5 10 GND 11 A6 12 A7 13 A8 14 A9 15 A10 16 A11 17 GND 18 A12 19 A13 20 A14 21 VCC 22 A15 23 A16 24 GND 25 A17 26 OEBA 27 LEBA 28 Fig 4. Pin configuration 5.2 Pin description Table 2. Symbol OEAB LEAB A0 GND A1 A2 VCC 74LVT16500A_3 Pin description Pin 1 2 3 4 5 6 7 Description A-to-B output enable input A-to-B latch enable input data input/output A0 ground (0 V) data input/output A1 data input/output A2 supply voltage © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 4 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Pin description …continued Pin 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Description data input/output A3 data input/output A4 data input/output A5 ground (0 V) data input/output A6 data input/output A7 data input/output A8 data input/output A9 data input/output A10 data input/output A11 ground (0 V) data input/output A12 data input/output A13 data input/output A14 supply voltage data input/output A15 data input/output A16 ground (0 V) data input/output A17 B-to-A output enable input (active LOW) B-to-A latch enable input ground (0 V) B-to-A clock input (active falling edge) data input/output B17 ground (0 V) data input/output B16 data input/output B15 supply voltage data input/output B14 data input/output B13 data input/output B12 ground (0 V) data input/output B11 data input/output B10 data input/output B9 data input/output B8 data input/output B7 data input/output B6 ground (0 V) data input/output B5 data input/output B4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Table 2. Symbol A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 OEBA LEBA GND CPBA B17 GND B16 B15 VCC B14 B13 B12 GND B11 B10 B9 B8 B7 B6 GND B5 B4 74LVT16500A_3 Product data sheet Rev. 03 — 29 May 2006 5 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Pin description …continued Pin 49 50 51 52 53 54 55 56 Description data input/output B3 supply voltage data input/output B2 data input/output B1 ground (0 V) data input/output B0 A-to-B clock input (active falling edge) ground (0 V) Table 2. Symbol B3 VCC B2 B1 GND B0 CPAB GND 6. Functional description Table 3. Function table[1] Control OEAB OEBA disabled disabled, latch data disabled, latch data disabled, hold data disabled, clock data disabled, clock data transparent transparent latch data and display latch data and display clock data and display clock data and display hold data and display hold data and display [1] Operating mode Input LEAB LEBA H ↓ ↓ L L L H H ↓ ↓ L L L L CPAB CPBA X X X H or L ↓ ↓ X X X X ↓ ↓ H or L H or L An Bn X h l X h l H L h l h l X X Internal register Output Bn An Z Z Z Z Z Z H L H L H L H L L L L L L L H H H H H H H H X H L NC H L H L H L H L H L H = HIGH voltage level; h = HIGH voltage level one setup time prior to the enable or clock transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the enable or clock transition; NC = no change; X = don’t care; Z = high-impedance OFF-state; ↓ = HIGH-to-LOW enable or clock transition. 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 6 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO IIK IOK IO Tstg Tj [1] [2] Conditions [1] Min −0.5 −0.5 −0.5 −65 [2] Max +4.6 +7.0 +7.0 −50 −50 128 −64 +150 150 Unit V V V mA mA mA mA °C °C supply voltage input voltage output voltage input clamping current output current storage temperature junction temperature output in OFF-state or HIGH-state VI < 0 V output in LOW-state output in HIGH-state [1] output clamping current VO < 0 V - The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 8. Recommended operating conditions Table 5. VCC VI VIH VIL IOH IOL Recommended operating conditions Conditions Min 2.7 0 2.0 −40 current duty cycle ≤ 50 %; fi ≥ 1 kHz ∆t/∆V Tamb input transition rise and fall rate ambient temperature outputs enabled in free air Typ Max Unit 3.6 5.5 0.8 −32 32 64 10 +85 V V V V mA mA mA ns/V °C supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current none Symbol Parameter 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 7 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to 85 VIK VOH °C[1] VCC = 2.7 V; IIK = −18 mA VCC = 2.7 V to 3.6 V; IOH = −100 µA VCC = 2.7 V; IOH = −8 mA VCC = 3.0 V; IOH = −32 mA VOL LOW-level output voltage VCC = 2.7 V IOL = 100 µA IOL = 24 mA VCC = 3.0 V IOL = 16 mA IOL = 32 mA IOL = 64 mA VRST ILI power-up output low voltage VCC = 3.6 V; IO = 1 mA; VI = VCC or GND input leakage current control pins I/O data pins VCC = 3.6 V; VI = VCC or GND VCC = 0 V or 3.6 V; VI = 5.5 V VCC = 3.6 V VI = 5.5 V VI = VCC VI = 0 V IOFF IHOLD power-off leakage current bus hold current data input VCC = 0 V; VI or VO = 0 V to 4.5 V VCC = 3 V VI = 0.8 V VI = 2.0 V VI = 0 V to 3.6 V; VCC = 3.6 V IEX IO(pu/pd) ICC external current into output power-up/power-down output current quiescent supply current output in the HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OEAB or OEBA don’t care VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH-state outputs LOW-state outputs disabled [6] [5] [4] [3] [2] Conditions Min 2.4 2.0 75 −75 ±500 - Typ −0.85 2.55 2.3 0.07 0.3 0.25 0.3 0.36 0.1 0.1 0.1 1.0 0.1 +0.1 1.0 130 −130 50 40 Max −1.2 0.2 0.5 0.4 0.5 0.55 0.55 ±1 10 20 10 −5 ±100 125 ±100 Unit V V V V V V V V V V µA µA µA µA µA µA µA µA µA µA µA input clamping voltage HIGH-level output voltage VCC − 0.2 VCC - 0.07 4 0.07 0.12 6 0.12 mA mA mA 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 8 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ∆ICC Ci Cio [1] [2] [3] [4] [5] [6] [7] Conditions per input pin; VCC = 3 V to 3.6 V; one input at VCC − 0.6 V; other inputs at VCC or GND control pins; VI = 0 V or 3.0 V I/O pins; VI/O = 0 V or 3.0 V [7] Min - Typ 0.1 3 9 Max 0.2 - Unit mA pF pF additional quiescent supply current input capacitance input/output capacitance Typical values are at VCC = 3.3 V and Tamb = 25 °C. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. Unused pins at VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.0 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only. ICC is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol tPLH Parameter propagation delay An to Bn or Bn to An CPAB to Bn or CPBA to An LEAB to Bn or LEBA to An tPHL propagation delay An to Bn or Bn to An CPAB to Bn or CPBA to An LEAB to Bn or LEBA to An tPZH tPZL tPHZ tPLZ tsu(H) output enable time to HIGH-level output enable time to LOW-level output disable time from LOW-level setup time HIGH An to CPAB or Bn to CPBA An to LEAB with CPAB LOW or Bn to LEBA with CPBA LOW An to LEAB with CPAB HIGH or Bn to LEBA with CPBA HIGH see Figure 10 see Figure 10 see Figure 10 2.5 2.2 2.7 ns ns ns see Figure 5 see Figure 6 see Figure 7 see Figure 8 see Figure 9 see Figure 9 5.4 6.4 6.4 5.5 5.2 6.3 5.6 ns ns ns ns ns ns ns see Figure 5 see Figure 6 see Figure 7 5.4 6.4 6.4 ns ns ns Conditions Min Typ Max Unit VCC = 2.7 V; Tamb = −40 °C to 85 °C output disable time from HIGH-level see Figure 8 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 9 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol tsu(L) Parameter setup time LOW An to CPAB or Bn to CPBA An to LEAB with CPAB LOW or Bn to LEBA with CPBA LOW An to LEAB with CPAB HIGH or Bn to LEBA with CPBA HIGH th(H) hold time HIGH An to CPAB or Bn to CPBA An to LEAB or Bn to LEBA th(L) hold time LOW An to CPAB or Bn to CPBA An to LEAB or Bn to LEBA tWH pulse width HIGH CPAB or CPBA LEAB or LEBA tWL pulse width LOW CPAB or CPBA VCC = 3.0 V ± 0.3 V; Tamb = −40 °C to 85 tPLH propagation delay An to Bn or Bn to An CPAB to Bn or CPBA to An LEAB to Bn or LEBA to An tPHL propagation delay An to Bn or Bn to An CPAB to Bn or CPBA to An LEAB to Bn or LEBA to An tPZH tPZL tPHZ tPLZ tsu(H) output enable time to HIGH-level output enable time to LOW-level output disable time from LOW-level setup time HIGH An to CPAB or Bn to CPBA An to LEAB with CPAB LOW or Bn to LEBA with CPBA LOW An to LEAB with CPAB HIGH or Bn to LEBA with CPBA HIGH tsu(L) setup time LOW An to CPAB or Bn to CPBA An to LEAB with CPAB LOW or Bn to LEBA with CPBA LOW An to LEAB with CPAB HIGH or Bn to LEBA with CPBA HIGH 74LVT16500A_3 Conditions see Figure 10 see Figure 10 see Figure 10 Min 2.5 2.2 2.7 Typ - Max - Unit ns ns ns see Figure 10 see Figure 10 see Figure 10 see Figure 10 see Figure 6 see Figure 7 see Figure 6 0 0 0 0 1.5 1.5 1.5 - - ns ns ns ns ns ns ns °C[1] see Figure 5 see Figure 6 see Figure 7 see Figure 5 see Figure 6 see Figure 7 see Figure 8 see Figure 9 see Figure 9 see Figure 10 see Figure 10 see Figure 10 0.5 1.0 1.0 0.5 1.0 1.0 1.0 1.0 1.0 1.0 2.4 2.3 2.4 1.9 3.2 2.4 1.9 3.2 2.9 2.4 2.2 2.8 3.2 1.0 0.9 0.9 4.2 5.4 5.4 4.2 5.4 5.4 4.8 4.8 5.8 5.2 ns ns ns ns ns ns ns ns ns ns ns ns ns output disable time from HIGH-level see Figure 8 see Figure 10 see Figure 10 see Figure 10 2.4 2.3 2.4 0.7 0.9 0.8 - ns ns ns © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 10 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol th(H) Parameter hold time HIGH An to CPAB or Bn to CPBA An to LEAB or Bn to LEBA th(L) hold time LOW An to CPAB or Bn to CPBA An to LEAB or Bn to LEBA tWH pulse width HIGH CPAB or CPBA LEAB or LEBA tWL fmax [1] Conditions see Figure 10 see Figure 10 see Figure 10 see Figure 10 see Figure 6 see Figure 7 see Figure 6 see Figure 6 Min 0 0 0 0 1.2 1.2 1.2 150 Typ 0 0 0 0 0.8 0.8 0.8 350 Max - Unit ns ns ns ns ns ns ns MHz pulse width LOW CPAB or CPBA maximum input clock frequency All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 11. Waveforms VI input An or Bn 0V t PLH VOH output Bn or An VOL 001aad308 VM VM t PHL VM VM Measurements points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load. Fig 5. Propagation delay input (An, Bn) to output (Bn, An) in transparent mode 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 11 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 1/fmax VI input CPBA or CPAB 0V t WL t PHL VOH output An or Bn VOL VM VM 001aaf037 VM VM t WH t PLH Measurements points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load. Fig 6. Propagation delay clock (CPAB, CPBA) to output (An, Bn), clock (CPAB, CPBA) pulse width and maximum clock frequency (CPAB, CPBA) VI input LEAB or LEBA 0V t WH t PHL VOH output An or Bn VOL 001aad310 VM VM VM t PLH VM VM Measurements points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load. Fig 7. Propagation delay latch enable (LEAB, LEBA) to output (An, Bn) and latch enable (LEAB, LEBA) pulse width OEBA input OEAB VI VM 0V t PZH VOH t PHZ VY VM output An or Bn 0V VM 001aad344 Measurements points are given in Table 8. VOH is typical voltage output drop that occur with the output load. Fig 8. 3-state output enable time to HIGH-level and output disable time from HIGH-level 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 12 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state OEBA input OEAB VI VM 0V t PZL 3.0 V or VCC t PLZ VM output An or Bn VOL VM VX 001aad346 Measurements points are given in Table 8. VOL is typical voltage output drop that occur with the output load. Fig 9. 3-state output enable time to LOW-level and output disable time from LOW-level CPAB or CPBA input LEAB or LEBA t su(H) t h(H) t su(L) t h(L) VM VM 3.0 V or VCC whichever is less 0V input An, Bn VM VM VM VM 3.0 V or VCC whichever is less 0V 001aaf036 Measurements points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 10. Data setup and hold times Table 8. Measurement points Input VM 2.7 V 3.3 V 1.5 V 1.5 V Output VM 1.5 V 1.5 V VX VOL + 0.3 V VOL + 0.3 V VY VOH − 0.3 V VOH − 0.3 V Supply voltage 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 13 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state VI negative pulse 0V tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM VI positive pulse 0V VEXT VCC PULSE GENERATOR VI DUT RT CL RL RL VO 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 11. Load circuitry for switching times Table 9. Input VI 2.7 V fi tW tr, tf ≤ 2.5 ns ≤ 10 MHz 500 ns Test data Load CL 50 pF RL 500 Ω VEXT tPHZ, tPZH tPLZ, tPZL tPLH, tPHL GND 6V open 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 14 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 12. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 D E A X c y HE vMA Z 56 29 Q A2 A1 pin 1 index Lp L (A 3) A θ 1 e bp wM 28 detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 14.1 13.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.5 0.1 θ 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT364-1 (TSSOP56) 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 15 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y HE vM A Z 56 29 Q A2 A1 (A 3) θ Lp 1 bp 28 wM L detail X A pin 1 index e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 18.55 18.30 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 13. Package outline SOT371-1 (SSOP56) 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 16 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 13. Abbreviations Table 10. Acronym BiCMOS DUT ESD TTL Abbreviations Description Bipolar Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Transistor-Transistor Logic 14. Revision history Table 11. Revision history Release date 20060529 Data sheet status Product data sheet Change notice Supersedes 74LVT16500A_2 Document ID 74LVT16500A_3 Modifications: • • • • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors Section 2 “Features”: replaced JEDEC JC40.2 Std 17 with JESD78 Figure 3 “Logic diagram”: corrected clock names and pin names Table 7 “Dynamic characteristics”: splitting up tsu(H) and tsu(L) parameter ‘An to LEAB or Bn to LEBA’ in 2 parameters with clock conditions and new values Product specification Product specification Product specification 74LVT16500A_1 74LVT16500A - 74LVT16500A_2 (9397 750 03556) 74LVT16500A_1 74LVT16500A 19980219 19970612 19950320 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 17 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 74LVT16500A_3 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 03 — 29 May 2006 18 of 19 Philips Semiconductors 74LVT16500A 3.3 V 18-bit universal bus transceiver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Date of release: 29 May 2006 Document identifier: 74LVT16500A_3