80C652

INTEGRATED CIRCUITS 80C652/83C652 CMOS single-chip 8-bit microcontrollers Product specification Supersedes data of 1996 Aug 15 IC20 Data Handbook 1997 Dec 05 Philips Semiconductors Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 DESCRIPTION The P80C652/83C652 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 80C652/83C652 has the same instruction set as the 80C51. Three versions of the derivative exist: 83C652 — 8k bytes mask programmable ROM 80C652 — ROMless version 87C652 — EPROM version (described in a separate chapter) This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The 8XC652 contains a non-volatile 8k × 8 read-only program memory, a volatile 256 × 8 read/write data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a multi-source, two-priority-level, nested interrupt structure, an I2C interface, UART and on-chip oscillator and timing circuits. For systems that require extra capability, the 8XC652 can be expanded using standard TTL compatible memories and logic. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. With a 16(24)MHz crystal, 58% of the instructions are executed in 0.75(0.5)µs and 40% in 1.5(1)µs. Multiply and divide instructions require 3(2)µs. PIN CONFIGURATIONS P1.0 1 P1.1 2 P1.2 3 P1.3 4 P1.4 5 40 V DD 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 PLASTIC DUAL IN-LINE PACKAGE 32 P0.7/AD7 31 EA 30 ALE 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8 FEATURES P1.5 6 SCL/P1.6 7 SDA/P1.7 8 RST 9 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 • 80C51 central processing unit • 8k × 8 ROM expandable externally to 64k bytes • 256 × 8 RAM, expandable externally to 64k bytes • Two standard 16-bit timer/counters • Four 8-bit I/O ports • I2C-bus serial I/O port with byte oriented master and slave functions • Full-duplex UART facilities • Power control modes – Idle mode – Power-down mode • ROM code protection • Extended frequency range: 3.5 to 24 MHz • Three operating ambient temperature ranges: 0 to +70°C –40 to +85°C –40 to +125°C 6 1 40 7 PLASTIC LEADED CHIP CARRIER 39 LOGIC SYMBOL VDDVSS ADDRESS AND DATA BUS RST XTAL1 XTAL2 EA PSEN ALE 44 ALTERNATE FUNCTIONS PORT 3 PORT 1 PORT 0 17 29 18 28 34 1 SCL SDA PLASTIC QUAD FLAT PACK 11 33 RxD TxD INT0 INT1 T0 T1 WR RD ADDRESS BUS PORT 2 23 12 22 1997 Dec 05 2 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS 6 1 40 PLASTIC QUAD FLAT PACK PIN FUNCTIONS 44 34 7 PLASTIC LEADED CHIP CARRIER 17 39 1 PLASTIC QUAD FLAT PACK 33 29 11 23 18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function NC* P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 28 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC* EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 12 Function P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD VSS4 P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS1 NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 22 Function P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE VSS2 EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD VSS3 P1.0 P1.1 P1.2 P1.3 P1.4 *DO NOT CONNECT *DO NOT CONNECT NOTES TO QFP ONLY: 1. Due to EMC improvements, all VSS pins (6, 16, 28, 39) must be connected to VSS on the 80C652/83C652. 1997 Dec 05 3 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 ORDER INFORMATION PHILIPS PART ORDER NUMBER PART MARKING ROMless P80C652EBP P80C652EBA P80C652EBB P80C652EFP P80C652EFA P80C652EFB P80C652EHP P80C652EHA P80C652EHB P80C652IBP P80C652IBA P80C652IBB P80C652IFP P80C652IFA P80C652IFB ROM3 P83C652EBP/xxx P83C652EBA/xxx P83C652EBB/xxx P83C652EFP/xxx P83C652EFA/xxx P83C652EFB/xxx P83C652EHP/xxx P83C652EHA/xxx P83C652EHB/xxx P83C652IBP/xxx P83C652IBA/xxx P83C652IBB/xxx P83C652IFP/xxx P83C652IFA/xxx P83C652IFB/xxx Drawing Number SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 PHILIPS NORTH AMERICA PART ORDER NUMBER ROMless P80C652EBPN P80C652EBAA P80C652EBBB P80C652EFPN P80C652EFAA P80C652EFBB ROM P83C652EBPN P83C652EBAA P83C652EBBB P83C652EFPN P83C652EFAA P83C652EFBB EPROM2 S87C652-4N40 S87C652-4A44 S87C652-4B44 S87C652-5N40 S87C652-5A44 S87C652-5B44 TEMPERATURE RANGE (°C) ) AND PACKAGE FREQ MHz MH 1,2 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack –40 to +85, Plastic Dual In-line Package –40 to +85, Plastic Leaded Chip Carrier –40 to +85, Plastic Quad Flat Pack –40 to +125, Plastic Dual In-line Package –40 to +125, Plastic Leaded Chip Carrier –40 to +125, Plastic Quad Flat Pack 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack –40 to +85, Plastic Dual In-line Package –40 to +85, Plastic Leaded Chip Carrier –40 to +85, Plastic Quad Flat Pack 16 16 16 16 16 16 16 16 16 24 24 24 24 24 24 P80C652EHPN P83C652EHPN P80C652EHAA P80C652EHBB P80C652IBPN P80C652IBAA P80C652IBBB P80C652IFPN P80C652IFAA P80C652IFBB P83C652EHAA P83C652EHBB P83C652IBPN P83C652IBAA P83C652IBBB P83C652IFPN P83C652IFAA P83C652IFBB NOTES: 1. 80C652 and 83C652 frequency range is 3.5MHz–16MHz or 3.5MHz–24MHz. 2. For specification of the EPROM version, see the 87C652 data sheet. 3. xxx denotes the ROM code number. 1997 Dec 05 4 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 BLOCK DIAGRAM FREQUENCY REFERENCE XTAL2 XTAL1 COUNTERS T0 T1 OSCILLATOR AND TIMING PROGRAM MEMORY (8K x 8 ROM) DATA MEMORY (256 x 8 RAM) TWO 16-BIT TIMER/EVENT COUNTERS SDA CPU I2C SERIAL I/O SCL SHARED WITH PORT 1 INTERNAL INTERRUPTS 64K BYTE BUS EXPANSION CONTRTOL PROG SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT PROGRAMMABLE I/O INT0 INT1 CONTROL PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS SERIAL IN SERIAL OUT EXTERNAL INTERRUPTS SHARED WITH PORT 3 1997 Dec 05 5 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 PIN DESCRIPTIONS PIN NUMBER MNEMONIC VSS VDD P0.0–0.7 DIP 20 40 39–32 PLCC 22 44 43–36 QFP 6, 16, 28, 39 38 37–30 TYPE I I I/O NAME AND FUNCTION Ground: 0V reference. With the QFP package all VSS pins (VSS1 to VSS4) must be connected. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Alternate functions include: SCL: I2C-bus serial port clock line. SDA: I2C-bus serial port data line. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency. Note that one ALE pulse is skipped during each access to external data memory. Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It is activated twice each machine cycle during fetches from the external program memory. When executing out of external program memory two activations of PSEN are skipped during each access to external data memory. PSEN is not activated (remains HIGH) during no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs and can drive CMOS inputs without external pull–ups. External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the internal program memory ROM provided the Program Counter is less than 8192. If during a RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is not allowed to float. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. P1.0–P1.7 1–8 2–9 40–44, 1–3 I/O P1.6 P1.7 P2.0–P2.7 7 8 21–28 8 9 24–31 2 3 18–25 I/O I/O I/O P3.0–P3.7 10–17 11, 13–19 5, 7–13 I/O 10 11 12 13 14 15 16 17 RST 9 11 13 14 15 16 17 18 19 10 5 7 8 9 10 11 12 13 4 I O I I I I O O I ALE 30 33 27 I/O PSEN 29 32 26 O EA 31 35 29 I XTAL1 19 21 15 I XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS – 0.5V, respectively. 1997 Dec 05 6 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 Table 1. SYMBOL ACC* B* DPTR: DPH DPL 8XC652/654 Special Function Registers DESCRIPTION Accumulator B register Data pointer (2 bytes) Data pointer high Data pointer low DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION ADDRESS MSB LSB E0H F0H E7 F7 E6 F6 E5 F5 E4 F4 E3 F3 E2 F2 E1 F1 E0 F0 RESET VALUE 00H 00H 83H 82H AF AE AD ES1 BE BD PS1 86 AD6 96 SCL A6 A14 B6 WR – 9E SM1 A5 A13 B5 T1 – 9D SM2 A4 A12 B4 T0 – 9C REN A3 A11 B3 INT1 GF1 9B TB8 A2 A10 B2 INT0 GF0 9A RB8 A1 A9 B1 TXD PD 99 TI A0 A8 B0 RXD IDL 98 RI 85 AD5 95 AC ES0 BC PS0 84 AD4 94 AB ET1 BB PT1 83 AD3 93 AA EX1 BA PX1 82 AD2 92 A9 ET0 B9 PT0 81 AD1 91 A8 EX0 B8 PX0 80 AD0 90 00H 00H IE*# Interrupt enable A8H EA BF 0x000000B IP*# Interrupt priority B8H – 87 xx000000B P0* Port 0 80H AD7 97 FFH P1*# Port 1 90H SDA A7 FFH P2* Port 2 A0H A15 B7 FFH P3* PCON Port 3 Power control B0H 87H RD SMOD 9F FFH 0xxx0000B S0CON*# S0BUF# Serial 0 port control Serial 0 data buffer 98H 99H SM0 00H xxxxxxxxB D7 PSW* S1DAT# SP S1ADR# Program status word Serial 1 data Stack pointer Serial 1 address D0H DAH 81H DBH CY D6 AC D5 F0 D4 RS1 D3 RS0 D2 OV D1 F1 D0 P 00H 00H 07H  SLAVE ADDRESS  SC4 DF SC3 DE ENS1 8E TR1 SC2 DD STA 8D TF0 SC1 DC STO 8C TR0 SC0 DB SI 8B IE1 0 DA AA 8A IT1 0 D9 CR1 89 IE0 GC 00H S1STA# Serial 1 status D9H 0 D8 CR0 88 IT0 F8H S1CON*# Serial 1 control D8H CR2 8F 00000000B TCON* TH1 TH0 TL1 TL0 Timer control Timer high 1 Timer high 0 Timer low 1 Timer low 0 88H 8DH 8CH 8BH 8AH TF1 00H 00H 00H 00H 00H TMOD Timer mode 89H GATE * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. C/T M1 M0 GATE C/T M1 M0 00H 1997 Dec 05 7 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 ROM CODE PROTECTION (83C652) The 8XC652 has an additional security feature. ROM code protection may be selected by setting a mask–programmable security bit (i.e., user dependent). This feature may be requested during ROM code submission. When selected, the ROM code is protected and cannot be read out at any time by any test mode or by any instruction in the external program memory space. The MOVC instructions are the only instructions that have access to program code in the internal or external program memory. The EA input is latched during RESET and is “don’t care” after RESET (also if the security bit is not set). This implementation prevents reading internal program code by switching from external program memory to internal program memory during a MOVC instruction or any other instruction that uses immediate data. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. Power-Down Mode In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register PCON. Table 2 shows the state of the I/O ports during low current operating modes. Reset A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up. I2C Serial Communication—SIO1 The I2C serial port is identical to the I2C serial port on the 8XC552. The operation of this subsystem is described in detail in the 8XC552 section of this manual. Note that in both the 8XC652/4 and the 8XC552 the I2C pins are alternate functions to port pins P1.6 and P1.7. Because of this, P1.6 and P1.7 on these parts do not have a pull-up structure as found on the 80C51. Therefore P1.6 and P1.7 have open drain outputs on the 8XC652/4. Idle Mode In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the Logic Symbol, page 2. Table 2. MODE Idle Idle External Pin Status During Idle and Power-Down Mode PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data Power-down Power-down Serial Control Register (S1CON) – See Table 3 S1CON (D8H) CR2 ENS1 STA STO SI AA CR1 CR0 Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation. Table 3. CR2 0 0 0 0 1 1 1 1 Serial Clock Rates BIT FREQUENCY (kHz) AT fOSC CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 6MHz 23 27 31.25 37 6.25 50 100 0.24 < 62.5 0 to 255 12MHz 47 54 62.5 75 12.5 100 2001 0.49 < 62.5 0 to 254 16MHz 62.5 71 83.3 100 17 1331 2671 0.65 < 55.6 0 to 253 24MHz 94 1071 1251 1501 25 2001 4001 0.98 < 50.0 0 to 251 fOSC DIVIDED BY 256 224 192 160 960 120 60 96 × (256 – (reload value Timer 1)) reload value range Timer 1 (in mode 2) NOTES: 1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application. 1997 Dec 05 8 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Storage temperature range Voltage on any other pin to VSS Input, output current on any single pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING –65 to +150 –0.5 to + 6.0 ±5 1 UNIT °C V mA W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. DEVICE SPECIFICATIONS TYPE SUPPLY VOLTAGE (V) MIN. P8XC652EBx P8XC652EFx P8XC652EHx P8XC652IBx P83X652IFx 4.5 4.5 4.5 4.5 4.5 MAX. 5.5 5.5 5.5 5.5 5.5 FREQUENCY (MHz) MIN. 3.5 3.5 3.5 3.5 3.5 MAX. 16 16 16 24 24 TEMPERATURE RANGE (°C) 0 to +70 –40 to +85 –40 to +125 0 to +70 –40 to +85 1997 Dec 05 9 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 DC ELECTRICAL CHARACTERISTICS VSS = 0V; VDD = 5V ± 10% TEST SYMBOL VIL PARAMETER Input low voltage, except EA, P1.6/SCL, P1.7/SDA PART TYPE 0 to +70°C –40 to +85°C –40 to +125°C 0 to +70°C –40 to +85°C –40 to +125°C CONDITIONS MIN. –0.5 –0.5 –0.5 –0.5 –0.5 –0.5 –0.5 0 to +70°C –40 to +85°C –40 to +125°C 0 to +70°C –40 to +85°C –40 to +125°C IOL = 1.6mA8, 9 IOL = 3.2mA8, 9 IOL = 3.0mA IOH = –60µA IOH = –25µA IOH = –10µA IOH = –800µA IOH = –300µA IOH = –80µA 0 to +70°C –40 to +85°C –40 to +125°C 0 to +70°C –40 to +85°C –40 to +125°C VIN = 0.45V 2.4 0.75VDD 0.9VDD 2.4 0.75VDD 0.9VDD –50 –75 –75 –650 –750 –750 ±10 ±10 LIMITS MAX. 0.2VDD–0.1 0.2VDD–0.15 0.2VDD–0.25 0.2VDD–0.3 0.2VDD–0.35 0.2VDD–0.45 0.3VDD VDD+0.5 VDD+0.5 VDD+0.5 VDD+0.5 VDD+0.5 VDD+0.5 6.0 0.45 0.45 0.4 UNIT V V V V V V V V V V V V V V V V V V V V V V V µA µA µA µA µA µA µA µA µA mA mA mA mA µA µA kΩ pF VIL1 Input low voltage to EA VIL2 VIH Input low voltage to P1.6/SCL, P1.7/SDA6 Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA 0.2VDD+0.9 0.2VDD+1.0 0.2VDD+1.0 0.7VDD 0.7VDD+0.1 0.7VDD+0.1 0.7VDD VIH1 Input high voltage, XTAL1, RST VIH2 VOL VOL1 VOL2 VOH Input high voltage, P1.6/SCL, P1.7/SDA6 Output low voltage, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA Output low voltage, port 0, ALE, PSEN Output low voltage, P1.6/SCL, P1.7/SDA Output high voltage, ports 1, 2, 3, ALE, PSEN10 VOH1 Output high voltage; port 0 in external bus mode IIL Logical 0 input current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA ITL Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA See note 7 IL1 IL2 IDD Input leakage current, port 0, EA Input leakage current, P1.6/SCL, P1.7/SDA Power supply current: Active mode @ 16MHz2, 11 Active mode @ 24MHz2, 11 Idle mode @ 16MHz3, 11 Idle mode @ 24MHz3, 11 Power down mode4, 5 Power down mode4, 5 Internal reset pull-down resistor Pin capacitance 0.45V < VI < VDD 0V < VI < 6.0V 0V < VDD < 6.0V See note 1 VDD=5.5V VDD=5.5V –40 to +125°C 50 Freq.=1MHz 26.5 33.8 6 7 50 100 150 10 RRST CIO NOTES ON NEXT PAGE. 1997 Dec 05 10 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 NOTES FOR DC ELECTRICAL CHARACTERISTICS: 1. See Figures 9 through 11 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5V; VIH = VDD –0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD. See Figure 9. 3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5V; VIH = VDD –0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 10. 4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 11. 5. 2V ≤ VPD ≤ VDDmax. 6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 0.3VDD will be recognized as a logic 0 while an input voltage above 0.7VDD will be recognized as a logic 1. 7. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 8. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 9. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL = 10mA per port pin; Maximum IOL = 26mA total for Port 0; Maximum IOL = 15mA total for Ports 1, 2, and 3; Maximum IOL = 71mA total for all output pins. If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 10. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 11. IDDMAX for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. IDDMAX is given in mA. 40 IDD (mA) IDD (mA) 50 40 30 30 (1) 20 (1) 20 10 10 (2) (2) 0 0 4 8 12 fXTAL1 (MHz) 16 0 0 4 8 12 16 24 fXTAL1 (MHz) (1) MAXIMUM OPERATING MODE: VDD = VDDmax (2) MAXIMUM IDLE MODE: VDD = VDDmax These values are valid within the specified frequency range. (1) MAXIMUM OPERATING MODE: VDD = VDDmax (2) MAXIMUM IDLE MODE: VDD = VDDmax These values are valid within the specified frequency range. Figure 1. IDD vs. Frequency 1997 Dec 05 11 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 AC ELECTRICAL CHARACTERISTICS1, 2 (16 MHz type) 16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tDW tWHQX tRLAZ tWHLH Shift Register tXLXL tQVXH tXHQX tXHDX tXHDV External Clock tCHCX tCLCX tCLCH tCHCL 6 6 6 6 High time3 Low time3 time3 Rise time3 Fall 20 20 20 20 20 20 tCLCL – tCLCX tCLCL – tCHCX 20 20 ns ns ns ns 5 5 5 5 5 Serial port clock cycle time3 Output data setup to clock rising edge3 Output data hold after clock rising edge3 Input data hold after clock rising edge3 Clock rising edge to input data valid3 0.75 492 80 0 492 12tCLCL 10tCLCL–133 2tCLCL–117 0 10tCLCL–133 µs ns ns ns ns 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data setup time before WR Data hold after WR RD low to address float RD or WR high to ALE high 23 138 120 3 288 13 0 103 tCLCL–40 0 55 350 398 238 3tCLCL–50 4tCLCL–130 tCLCL–60 7tCLCL–150 tCLCL–50 0 tCLCL+40 275 275 148 0 2tCLCL–70 8tCLCL–150 9tCLCL–165 3tCLCL+50 6tCLCL–100 6tCLCL–100 5tCLCL–165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 2 2 2 2 2 2 2 2 2 2 2 2 PARAMETER Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 38 208 10 23 143 83 0 tCLCL–25 5tCLCL–105 10 85 8 28 150 tCLCL–40 3tCLCL–45 3tCLCL–105 MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL–40 tCLCL–55 tCLCL–35 4tCLCL–100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. These values are characterized but not 100% production tested. 1997 Dec 05 12 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 AC ELECTRICAL CHARACTERISTICS1, 2 (24 MHz type) 24MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tDW tWHQX tRLAZ tWHLH Shift Register tXLXL tQVXH tXHQX tXHDX tXHDV External Clock tCHCX tCLCX tCLCH tCHCL 6 6 6 6 High time3 Low time3 time3 Rise time3 Fall 17 17 5 5 17 17 tCLCL – tCLCX tCLCL – tCHCX 5 5 ns ns ns ns 5 5 5 5 5 Serial port clock cycle time3 Output data setup to clock rising edge3 Output data hold after clock rising edge3 Input data hold after clock rising edge3 Clock rising edge to input data valid3 0.5 283 23 0 283 12tCLCL 10tCLCL–133 2tCLCL–60 0 10tCLCL–133 µs ns ns ns ns 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data setup time before WR Data hold after WR RD low to address float RD or WR high to ALE high 17 75 92 12 162 17 0 67 tCLCL–25 0 55 180 210 175 3tCLCL–50 4tCLCL–75 tCLCL–30 7tCLCL–130 tCLCL–25 0 tCLCL+25 150 150 118 0 2tCLCL–28 8tCLCL–150 9tCLCL–165 3tCLCL+50 6tCLCL–100 6tCLCL–100 5tCLCL–90 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 2 2 2 2 2 2 2 2 2 2 2 2 PARAMETER Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 17 128 10 17 80 65 0 tCLCL–25 5tCLCL–80 10 43 17 17 102 tCLCL–25 3tCLCL–45 3tCLCL–60 MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL–40 tCLCL–25 tCLCL–25 4tCLCL–65 MAX 24 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. These values are characterized but not 100% production tested. 1997 Dec 05 13 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 AC ELECTRICAL CHARACTERISTICS – I2C INTERFACE SYMBOL PARAMETER INPUT OUTPUT SCL TIMING CHARACTERISTICS tHD;STA tLOW tHIGH tRC tFC tSU;DAT1 tSU;DAT2 tSU;DAT3 tHD;DAT tSU;STA tSU;STO tBUF tRD START condition hold time SCL LOW time SCL HIGH time SCL rise time SCL fall time Data set-up time SDA set-up time (before rep. START cond.) SDA set-up time (before STOP cond.) Data hold time Repeated START set-up time STOP condition set-up time Bus free time SDA rise time ≥ ≥ ≥ ≤ ≥ ≥ ≥ 14 tCLCL 16 tCLCL 14 tCLCL ≤ > 4.0µs1 > 4.7µs1 > 4.0µs1 –2 < 0.3µs3 > 20 tCLCL – tRD > 1µs1 > 8 tCLCL > 8 tCLCL – tFC > 4.7µs1 > 4.0µs1 > 4.7µs1 –2 1µs 0.3µs 250ns 250ns 250ns ≥ SDA TIMING CHARACTERISTICS ≥ ≥ ≥ 0ns 14 tCLCL 14 tCLCL 14 tCLCL ≤ 1µs tFD SDA fall time ≤ 0.3µs < 0.3µs3 NOTES: 1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs. 3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400pF. 4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 63ns (42ns) < tCLCL < 285ns (16MHz (24MHz) > fOSC > 3.5MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s. TIMING SIO1 (I2C) INTERFACE repeated START condition START or repeated START condition tRD STOP condition 0.7 VDD 0.3 VDD tBUF tFD tRC tFC tSU; STO 0.7 VDD 0.3 VDD tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tHD;DAT tSU;DAT2 tSU;STA START condition SDA (INPUT/OUTPUT) SCL (INPUT/OUTPUT) 1997 Dec 05 14 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. tLHLL ALE tAVLL tLLPL tPLPH PSEN tLLIV tPLIV tLLAX tPLAZ tPXIX tPXIZ PORT 0 A0–A7 INSTR IN A0–A7 tAVIV PORT 2 A8–A15 A8–A15 Figure 2. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL RD tRLRH tAVLL PORT 0 tLLAX tRLAZ A0–A7 FROM RI OR DPL tRLDV tRHDX DATA IN tRHDZ A0–A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH Figure 3. External Data Memory Read Cycle 1997 Dec 05 15 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 ALE tWHLH PSEN tLLWL WR tWLWH tAVLL PORT 0 tLLAX tQVWX tDW tWHQX A0–A7 FROM RI OR DPL DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH Figure 4. External Data Memory Write Cycle INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 tXLXL CLOCK tQVXH OUTPUT DATA WRITE TO SBUF tXHQX tXHDV INPUT DATA VALID CLEAR RI VALID tXHDX SET TI VALID VALID VALID VALID VALID VALID SET RI Figure 5. Shift Register Mode Timing 1997 Dec 05 16 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 VIH1 0.8V tCHCL tCLCX tCLCL tCHCX tCLCH Figure 6. External Clock Drive at XTAL1 VDD–0.5 0.2VDD+0.9 VLOAD 0.2VDD–0.1 VLOAD+0.1V VLOAD–0.1V TIMING REFERENCE POINTS VOH–0.1V VOL+0.1V 0.45V NOTE: AC INPUTS DURING TESTING ARE DRIVEN AT VDD–0.5 FOR A LOGIC ‘1’ AND 0.45V FOR A LOGIC ‘0’. TIMING MEASUREMENTS ARE MADE AT VIH MIN FOR A LOGIC ‘1’ AND VIL MAX FOR A LOGIC ‘0’. NOTE: FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A 100mV CHANGE FROM THE LOADED VOH/VOL LEVEL OCCURS. IOH/IOL > + 20mA. Figure 7. AC Testing Input/Output Figure 8. Float Waveform 1997 Dec 05 17 Phlips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 VDD IDD VDD VDD P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS P1.6 P1.7 VDD RST EA P0 VDD VDD IDD VDD RST * * (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS P1.6 P1.7 * * Figure 9. IDD Test Condition, Active Mode All other pins are disconnected Figure 10. IDD Test Condition, Idle Mode All other pins are disconnected VDD IDD VDD RST EA P0 VDD (NC) XTAL2 XTAL1 VSS P1.6 P1.7 * * Figure 11. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2V to 5.5V NOTE: * Ports 1.6 and 1.7 should be connected to VCC through resistors of sufficiently high value such that the sink current into these pins does not exceed the IOL1 specification. Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Dec 05 18 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 1997 Dec 05 19 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 1997 Dec 05 20 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 1997 Dec 05 21 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 80C652/83C652 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 06-98 Document order number: 9397 750 04047 Philips Semiconductors 1997 Dec 05 22