83C851

INTEGRATED CIRCUITS 80C851/83C851 CMOS single-chip 8-bit microcontroller with on-chip EEPROM Product specification Supersedes data of 1992 Nov 25 IC20 Data Handbook 1998 Jul 03 Philips Semiconductors Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 DESCRIPTION The Philips 80C851/83C851 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The 80C851/83C851 has the same instruction set as the 80C51. The Philips CMOS technology combines the high speed and density characteristics of HMOS with the low power attributes of CMOS. The Philips epitaxial substrate minimizes latch-up sensitivity. The 80C851/83C851 contains a 4k × 8 ROM with mask-programmable ROM code protection, a 128 × 8 RAM, 256 × 8 EEPROM, 32 I/O lines, two 16-bit counter/timers, a seven-source, five vector, two-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the 80C851/83C851 has two software selectable modes of power reduction — idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM and EEPROM contents but freezes the oscillator, causing all other chip functions to be inoperative. FEATURES • 80C51 based architecture – 4k × 8 ROM – 128 × 8 RAM – Two 16-bit counter/timers – Full duplex serial channel – Boolean processor • Non-volatile 256 × 8-bit EEPROM (electrically erasable programmable read only memory) – On-chip voltage multiplier for erase/write – 10,000 erase/write cycles per byte – 10 years non-volatile data retention – Infinite number of read cycles – User selectable security mode – Block erase capability • Mask-programmable ROM code protection • Memory addressing capability – 64k ROM and 64k RAM • Power control modes: – Idle mode – Power-down mode • CMOS and TTL compatible • 1.2 to 16MHz or 3.5 to 24MHz • Three package styles • Three temperature ranges • ROM code protection ORDERING INFORMATION PHILIPS PART ORDER NUMBER PART MARKING ROMless Version P80C851 FBP P80C851 IBP P80C851 FBA P80C851 IBA P80C851 FBB P80C851 IBB P80C851 FFP P80C851 FFA P80C851 FFB P80C851 FHP P80C851 FHA P80C851 FHB ROM Version P83C851 FBP P83C851 IBP P83C851 FBA P83C851 IBA P83C851 FBB P83C851 IBB P83C851 FFP P83C851 FFA P83C851 FFB P83C851 FHP P83C851 FHA P83C851 FHB S80C851-5N40 S80C851-5A44 S80C851-5B44 S80C851-6N40 S80C851-6A44 S80C851-6B44 S83C851-5N40 S83C851-5A44 S83C851-5B44 S83C851-6N40 S83C851-6A44 S83C851-6B44 S80C851-4B44 S83C851-4B44 S80C851-4A44 S83C851-4A44 NORTH AMERICA PHILIPS PART ORDER NUMBER ROMless Version S80C851-4N40 ROM Version S83C851-4N40 TEMPERATURE RANGE °C AND PACKAGE 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack 0 to +70, Plastic Quad Flat Pack –40 to +85, Plastic Dual In-line Package –40 to +85, Plastic Leaded Chip Carrier –40 to +85, Plastic Quad Flat Pack –40 to +125, Plastic Dual In-line Package –40 to +125, Plastic Leaded Chip Carrier –40 to +125, Plastic Quad Flat Pack FREQ. (MHz) 1.2 to 16 3.5 to 24 1.2 to 16 3.5 to 24 1.2 to 16 3.5 to 24 1.2 to 16 1.2 to 16 1.2 to 16 1.2 to 16 1.2 to 16 1.2 to 16 DRAWING NUMBER SOT129-1 SOT129-1 SOT187-1 SOT187-1 SOT307-2 SOT307-2 SOT129-1 SOT187-1 SOT307-2 SOT129-1 SOT187-1 SOT307-2 1998 Jul 03 2 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 BLOCK DIAGRAM FREQUENCY REFERENCE XTAL2 XTAL1 COUNTERS T0 T1 OSCILLATOR AND TIMING PROGRAM MEMORY (4K x 8 ROM) DATA MEMORY (128 x 8 RAM) TWO 16-BIT TIMER/EVENT COUNTERS EEPROM (256 x 8) CPU INTERNAL INTERRUPTS 64K BYTE BUS EXPANSION CONTRTOL PROGRAMMABLE I/O PROG SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT INT0 INT1 CONTROL PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS SERIAL IN SERIAL OUT EXTERNAL INTERRUPTS SHARED WITH PORT 3 LOGIC SYMBOL VDD XTAL1 PORT 0 ADDRESS AND DATA BUS VSS XTAL2 SECONDARY FUNCTIONS RST EA PSEN ALE RxD TxD INT0 INT1 T0 T1 WR RD PORT 3 PORT 2 PORT 1 ADDRESS BUS 1998 Jul 03 3 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 PIN CONFIGURATIONS PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS 6 1 40 PLASTIC QUAD FLAT PACK PIN FUNCTIONS 44 34 P1.0 1 P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1.6 7 P1.7 8 RST 9 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 DUAL IN-LINE PACKAGE 40 VDD 39 P0.0/AD0 7 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA 30 ALE 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 39 PLASTIC LEADED CHIP CARRIER 22 17 39 1 33 PLCC PQFP 29 11 23 18 28 12 Function NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC* EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function P1.5 P1.6 P1.7 RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7RD XTAL2 XTAL1 VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 22 Function P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC* EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD VSS P1.0 P1.1 P1.2 P1.3 P1.4 Function NC* P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 6 1 40 7 * NO INTERNAL CONNECTION * NO INTERNAL CONNECTION 17 29 18 28 44 34 1 PLASTIC QUAD FLAT PACK 11 33 23 12 22 1998 Jul 03 4 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 PIN DESCRIPTION PIN NO. MNEMONIC VSS VDD P0.0–0.7 DIP 20 40 39–32 LCC 22 44 43–36 QFP 16, 39 38 37–30 TYPE I I I/O Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the SC80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out of the internal program memory ROM provided the Program Counter is less than 4096. If during a RESET, EA is held a TTL LOW level, the CPU executes out of external program memory. EA is not allowed to float. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. NAME AND FUNCTION P1.0–P1.7 1–8 2–9 40–44, 1–3 I/O P2.0–P2.7 21–28 24–31 18–25 I/O P3.0–P3.7 10–17 11, 13–19 5, 7–13 I/O 10 11 12 13 14 15 16 17 RST 9 11 13 14 15 16 17 18 19 10 5 7 8 9 10 11 12 13 4 I O I I I I O O I ALE 30 33 27 I/O PSEN 29 32 26 O EA 31 35 29 I XTAL1 XTAL2 19 18 21 20 15 14 I O 1998 Jul 03 5 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 Table 1. SYMBOL ACC* B* 8XC851 Special Function Registers DESCRIPTION Accumulator B register DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION ADDRESS MSB LSB E0H F0H E7 F7 EF E6 F6 EE E5 F5 ED E4 F4 EC E3 F3 EB E2 F2 EA E1 F1 E9 E0 F0 E8 RESET VALUE 00H 00H DPTR: DPH DPL EADRH# EADRL# ECNTRL# EDAT# ETIM# Data pointer (2 bytes): High byte Low byte EEPROM addr reg-high EEPROM addr reg-low EEPROM control reg EEPROM data register EEPROM timer register 83H 82H F3H F2H F6H F4H F5H BF BE – BD – BC PS BB PT1 BA PX1 B9 PT0 B8 PX0 IFE EEINT EWP – ECNTR L3 ECNTR L2 ECNTR L1 00H 00H 80H 00H ECNTR 00H L0 xxH 08H IP* Interrupt priority B8H – xxx00000B AF IE* P0* P1* P2* P3* PCON Interrupt enable Port 0 Port 1 Port 2 Port 3 Power control A8H 80H 90H A0H B0H 87H EA 87 97 A7 B7 SMOD AE – 86 96 A6 B6 – AD – 85 95 A5 B5 – AC ES 84 94 A4 B4 – AB ET1 83 93 A3 B3 GF1 AA EX1 82 92 A2 B2 GF0 A9 ET0 81 91 A1 B1 PD A8 EX0 80 90 A0 B0 IDL 0xx00000B FFH FFH FFH FFH 0xxx0000B D7 PSW* SBUF Program status word Serial data buffer D0H 99H 9F SCON* SP Serial port control Stack pointer 98H 81H 8F TCON* Timer/counter control 88H TF1 SM0 CY D6 AC D5 F0 D4 RS1 D3 RS0 D2 OV D1 – D0 P 00H xxxxxxxxB 9E SM1 9D SM2 9C REN 9B TB8 9A RB8 99 TI 98 RI 00H 07H 8E TR1 8D TF0 8C TR0 8B IE1 8A IT1 89 IE0 88 IT0 00H 00H TMOD TH0 TH1 TL0 Timer/counter mode Timer 0 high byte Timer 1 high byte Timer 0 low byte 89H 8CH 8DH 8AH GATE C/T M1 M0 GATE C/T M1 M0 00H 00H 00H 00H 00H TL1 Timer 1 low byte 8BH * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1998 Jul 03 6 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 EEPROM Communications between the CPU and the EEPROM is accomplished via 5 special function registers; 2 address registers (high and low byte), 1 data register for read and write operations, 1 control register, and 1 timer register to adapt the erase/write time to the clock frequency. All registers can be read and written. Figure 1 shows a block diagram of the CPU, the EEPROM and the interface. EADRH register address is F3H. The EADRL register address is F2H. Data Register (EDAT) This register is required for read and write operations and also for row/block erase. In write mode, its contents are written to the addressed byte (for “row erase” and “block erase” the contents are don’t care). The write pulse starts all operations, except read. In read mode, EDAT contains the data of the addressed byte. The EDAT register address is F4H. Timer Register (ETIM) The timer register is required to adapt the erase/write time to the oscillator frequency. The user has to ensure that the erase or write (program) time is neither too short or too long. The ETIM register address is F5H. Table 2 contains the values which must be written to the ETIM register by software for various oscillator frequencies (the default value is 08H after RESET). The general formula is: 2ms Write time: f [kHz] Value (decimal, + XTAL1 *2 to be rounded up) 512 10ms Write time: Value (decimal) + f XTAL1 [kHz] *2 96 Register and Functional Description Address Register (EADRH, EADRL) The lower byte contains the address of one of the 256 bytes. The higher byte (EADRH) is for future extensions and for addressing the security bits (see Security Facilities). The Control Register (ECNTRL) See Figure 2 for a description of this register. The ECNTRL register address is F6H. Table 2. fXTAL1 Values for the Timer Register (ETIM) VALUES FOR ETIM 2ms WRITE TIME HEX DEC – 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 – 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E 10ms WRITE TIME HEX 08 13 1D 28 32 3C 47 51 5C 66 71 7B DEC 8 19 29 40 50 60 71 81 92 102 113 123 1.0MHz 2.0MHz 3.0MHz 4.0MHz 5.0MHz 6.0MHz 7.0MHz 8.0MHz 9.0MHz 10.0MHz 11.0MHz 12.0MHz 13.0MHz 14.0MHz 15.0MHz 16.0MHz . . 24.0MHz 2C INTERRUPT 4745 CONTROL LOGIC SEQUENCER 8 MATRIX EEPROM POWER-DOWN IDLE RESET ECNTRL CLOCK GENERATOR ETIM COLUMN DECODER 3 5 ROW DECODER CLK CPU 8 EDATA 3 EADRH 8 EADRL INTERNAL BUS Figure 1. EEPROM Interface Block Diagram 1998 Jul 03 7 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 7 IFE Bit ECNTRL.7 6 EEINT Symbol IFE 5 EWP 4 –– 3 2 1 0 ECNTRL3 ECNTRL2 ECNTRL1 ECNTRL0 ECNTRL.6 ECNTRL.5 ECNTRL.4 ECCTRL.3– ECNTRL.0 EEINT EWP Function Active high EEPROM interrupt flag: set by the sequencer or by software; reset by software. When set and enabled, this flag forces an interrupt to the same vector as the serial port interrupt (see Interrupt section). EEPROM interrupt enable: set and reset by software (active high). Erase/write in progress flag: set and reset by the sequencer (active high). When EWP is set, access to the EEPROM is not possible. EWP cannot be set or reset by software. Reserved. See table below. ECNTRL.3 0 1 – – 1 ECNTRL.2 0 1 – – 0 ECNTRL.1 0 0 – – 1 ECNTRL.0 0 0 – – 0 Operation Byte mode Row erase Page write* Page erase/write* block erase *Future products. Byte mode: Read mode: Write mode: Normal EEPROM mode, default mode after reset. In this mode, data can be read and written to one byte at a time. This is the default mode when byte mode is selected. This means that the contents of the addressed byte are available in the data register. This mode is activated by writing to the data register. The address register must be loaded first. Since the old contents are read first (by default), this allows the sequencer to decide whether an erase/write or write cycle only (data = 00H) is required. In this mode, the addressed row is cleared. The three LSBs of EADRL are not significant, i.e. the 8 bytes addressed by EADRL are cleared in the same time normally needed to clear one byte (tROWERASE = tE = tW). For the following write modes, only the write and not the erase/write cycle is required. For example, using the row erase mode, programming 8 bytes takes tTOTOAL = tE + 8 × tW compared to tTOTAL = 8 × tE + 8 × tW (tE = tERASE ⋅ tW = tWRITE). For future products. For future products. In this mode all 256 bytes are cleared. The byte containing the security bits is also cleared. tBLOCKERASE = tE. The contents of EADRH, EADRL and EDAT are insignificant. Row erase: Page write: Page erase/write: Block erase: Program Sequences and Register Contents after Reset The contents of the EEPROM registers after a Reset are the default values: EADRH = 1xxxxxxxB (security bit address) EADRL = 00H (security bit address) ETIM = 08H (minimum erase time with the lowest permissible oscillator frequency) ECNTRL = 00H (Byte mode, read) EDAT = xxH (security bit) Initialize: Read: Write: Erase row: MOV ETIM, .. MOV EADRH, .. MOV EADRL, .. MOV .., EDAT MOV EADRL, .. MOV EDAT, .. MOV EADRL, .. Row address. 3LSBs don’t care MOV ECNTRL, #0CH Erase row mode MOV EDAT, .. (EDAT) don’t care Erase block: MOV ECNTRL, 0AH Erase block mode MOV EDAT, .. (EDAT) don’t care If the security bit is to be altered, the program generally starts as follows: MOV EADRH, #80H MOV EADRL, #00H Figure 2. Control Register (ECNTRL) 8 1998 Jul 03 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 Security Facilities EEPROM Protection The EEPROM is protected using four security bits which are contained in an extra EEPROM byte at address 8000H (EADRH/EADRL). They can be set or cleared by software. To activate the EEPROM protection, the program sequence in byte mode must be as follows: MOV MOV MOV EADRH, #80H EADRL, #00H EDAT, #FFH the EA pin low or by passing the 4K boundary). For SB = 1 and “external access” only, the “block erase” mode is enabled. The program sequence has to be as follows: MOV MOV MOV MOV EADRH, #80H (security byte address) EADRL, #00H (security byte address) ECNTRL, #0AH (block erase mode) EDAT, #xxH (start block erase) mode to internal access within the MOVC cycle. Additionally, a mask-programmable ROM code protection facility is available. When the program memory passes the 4K boundary using both the internal and external ROMs, it is not possible to access the internal ROM from the external program memory if the mask-programmable ROM security bit is set. An access to the lower 4K bytes of program memory using the MOVC instruction is only possible while executing internal program memory. Also the verification mode (test-mode which writes the ROM contents to a port for comparison with a reference code) is not implemented for security reasons. A different test-mode is implemented for test purposes. This mode allows every bit to be tested. However, the internal code cannot be accessed via a port. If two or more of these bits are reset, SB = 0, the security mode is disabled and the EEPROM is not protected. If three or four bits are set, SB = 1 and the EA mode differs from the internal access mode. In this case, access to the EEPROM is only possible in one mode regardless of how the external access mode is reached (by pulling All 256 data bytes, the security bits, and SB will be cleared after completing this mode (EWP = 0). SB will also be affected in byte mode when writing to the security byte (not for SB = 1 and “external access”). Figure 3 illustrates the access to SB. ROM Code Protection Since the external access mode can only be selected by pulling the EA pin low during reset, it is not possible to read the internal program memory using the MOVC instruction while executing external program memory. Furthermore, it is not possible to change this RESET EADRH EADRL 8 RESET EA REGISTERS EADRH AND EADRL CONTAIN THE ADDRESS OF THE SECURITY BYTE EEPROM RESET EDATA n RESET SECURITY BYTE ADDRESS AND BLOCK ERASE FINISHED SECURITY BYTE ADDRESS AND BYTE MODE FINISHED L EAQ SB SB = 1 NO YES EXTERNAL ACCESS YES NO INHIBIT ‘READ DATA REGISTER’ INHIBIT ‘WRITE DATA REGISTER’ EXCEPT (ECNTRL) = BLOCK ERASE Figure 3. EEPROM Protection (Functional and Flowchart) 1998 Jul 03 9 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol, page 3. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. (i.e., the EWP bit has to be reset before activating the idle or power-down modes; otherwise EEPROM accesses will be aborted). INTERRUPT SYSTEM External events and the real-time-driven on-chip peripherals require service by the CPU asynchronous to the execution of any particular section of code. To tie the asynchronous activities of these functions to normal program execution, a multiple-source, two-priority-level, nested interrupt system is provided. Interrupt response latency is from 3µs to 7µs when using a 12MHz crystal. The S83C851 acknowledges interrupt requests from 7 sources as follows: – INT0 and INT1: externally via pins 12 and 13, respectively, – Timer 0 and timer 1: from the two internal counters, – Serial port: from the internal serial I/O port or EEPROM (1 vector). Each interrupt vectors to a separate location in program memory for its service program. Each source can be individually enabled (the EEPROM interrupt can only be enabled when the serial port interrupt is enabled) or disabled and can be programmed to a high or low priority level. All enabled sources can also be globally disabled or enabled. Both external interrupts can be programmed to be level-activated and are active low to allow “wire-ORing” of several interrupt sources to one input pin. Note: The serial port and EEPROM interrupt flags must be cleared by software; all other flags are cleared by hardware. IDLE MODE In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. RESET A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-up, the voltage on VDD and RST must come up at the same time for a proper start-up. Note: Before entering the idle or power-down modes, the user has to ensure that there is no EEPROM erase/write cycle in progress POWER-DOWN MODE In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM and EEPROM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register PCON. Table 3 shows the state of the I/O ports during low current operating modes. Table 3. Idle Idle Power-down Power-down External Pin Status During Idle and Power-Down Modes MODE PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Storage temperature range Voltage on any other pin to VSS Input or output DC current on any single I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING –65 to +150 –0.5 to +6.5 UNIT °C V mA W ±5 1.0 NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 1998 Jul 03 10 Philips Semiconductors Product specification CMOS single-chip 8-bit microcontroller with on-chip EEPROM 80C851/83C851 DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C (VDD = 5V ±10%), –40°C to +85°C (VDD = 5V ±10%), or –40°C to +125°C (VDD = 5V ±10%), VSS = 0V PART SYMBOL VIL PARAMETER Input low voltage, except EA TYPE 0 to +70°C –40 to +85°C –40 to +125°C 0 to +70°C –40 to +85°C –40 to +125°C 0 to +70°C –40 to +85°C –40 to +125°C 0 to +70°C –40 to +85°C –40 to +125°C IOL = 1.6mA4 IOL = 3.2mA4 IOH = –60µA, IOH = –25µA, IOH = –10µA IOH = –800µA, IOH = –300µA, IOH = –80µA 0 to +70°C –40 to +85°C –40 to +125°C 0 to +70°C –40 to +85°C –40 to +125°C VIN = 0.45V 2.4 0.75VDD 0.9VDD 2.4 0.75VDD 0.9VDD –50 –75 –75 –650 –750 –750 TEST CONDITIONS MIN –0.5 –0.5 –0.5 –0.5 –0.5 –0.5 0.2VDD+0.9 0.2VDD+1.0 0.2VDD+1.0 0.7VDD 0.7VDD+0.1 0.7VD+0.1 LIMITS MAX 0.2VDD–0.1 0.2VDD–0.15 0.2VDD–0.25 0.2VDD–0.3 0.2VDD–0.35 0.2VDD–0.45 VDD+0.5 VDD+0.5 VDD+0.5 VDD+0.5 VDD+0.5 VDD+0.5 0.45 0.45 V V V V V V V V µA µA µA µA µA µA µA mA mA mA mA µA kΩ UNIT V V V V V V V V V VIL1 Input low voltage to EA VIH Input high voltage, except XTAL1, RST VIH1 Input high voltage, XTAL1, RST VOL VOL1 VOH Output low voltage, ports 1, 2, 3 6 Output low voltage, port 0, ALE, PSEN 6 Output high voltage, ports 1, 2, 3, ALE, PSEN VOH1 Output high voltage, port 0 in external bus mode5 Logical 0 input current, ports 1, 2, 3 IIL ITL Logical 1-to-0 transition current, ports 1, 2, 3 VIN = 2.0V IL1 IDD Input leakage current, port 0, EA Power supply current: Active mode @ 16MHz 1 Active mode @ 24MHz 1 Idle mode @ 16MHz 2 Idle mode @ 24MHz 2 Power down mode 3 Internal reset pull-down resistor 0.45V