87C576

INTEGRATED CIRCUITS 83C576/87C576 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer Product specification Supersedes data of 1998 Jan 06 IC20 Data Handbook 1998 Jun 04 Philips Semiconductors Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 FEATURES • 80C51 based architecture – 8k × 8 ROM (83C576) – 256 × 8 RAM – 10-bit, 6 channel A/D – Three 16-bit counter/timers – 2 PWM outputs – Programmable Counter Array – Universal Peripheral Interface – Enhanced UART – Oscillator fail detect – Low active reset – 4 analog comparators – Watchdog timer – Low VCC detect – Power-on detect – 8k × 8 EPROM (87C576) • OTP available • That can be programmed in circuit • Software Reset • 15 source, 2 level interrupt structure • Lower EMI noise • Programmable I/O pins • Serial on-board programming • Schmitt trigger inputs on Port 1 DESCRIPTION The Philips 83C576/87C576 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The Philips CMOS technology combines the high speed and density characteristics of HMOS with the low power attributes of CMOS. Philips epitaxial substrate minimizes latch-up sensitivity. The 8XC576 contains an 8k × 8 ROM (83C576) EPROM (87C576), a 256 × 8 RAM, 32 I/O lines, three 16-bit counter/timers, a Programmable Counter Array (PCA), a 10-bit, 6 channel A/D, 2 PWM outputs, an 8-bit UPI interface, a fifteen-source, two-priority level nested interrupt structure, an enhanced UART, four analog comparators, power-fail detect and oscillator fail detect circuits, and on-chip oscillator and clock circuits. In addition, the 8XC576 has a low active reset, and a software reset. There is also a fully configurable watchdog timer, and internal power on clear circuit. The part includes idle mode and power-down mode states for reduced power consumption. • Memory addressing capability – 64k ROM and 64k RAM • Power control modes: – Idle mode – Power-down mode • CMOS and TTL compatible • 6 to 16MHz • Extended temperature ranges ORDERING INFORMATION ROM P83C576EBP N P83C576EBA A P83C576EBB B P83C576EFP N P83C576EFA A P83C576EFB B P83C576EHPN P83C576EHAA P83C576EHBB EPROM1 P87C576EBPN P87C576EBAA P87C576EBBB P87C576EBPN P87C576EFA A P87C576EFBB P87C576EHPN P87C576EHAA P87C576EHBB OTP OTP OTP OTP OTP OTP OTP OTP OTP TEMPERATURE RANGE °C AND PACKAGE 0 to +70, 40-Pin Plastic Dual In-line Package 0 to +70, 44-Pin Plastic Leaded Chip Carrier 0 to +70, 44-Pin Plastic Quad Flat Pack –40 to +85, 40-Pin Plastic Dual In-line Package –40 to +85, 44-Pin Plastic Leaded Chip Carrier –40 to +85, 44-Pin Plastic Quad Flat Pack –40 to +125, 40-Pin Plastic Dual In-line Package –40 to +125, 44-Pin Plastic Leaded Chip Carrier –40 to +125, 44-Pin Plastic Quad Flat Pack FREQ (MHz) 16 16 16 16 16 16 16 16 16 DRAWING NUMBER SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 NOTE: 1. OTP - One Time Programmable EPROM. 1998 Jun 04 2 853-2067 19495 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 BLOCK DIAGRAM P0.0-P0.7 P2.0-P2.7 UPI CONTROL PORT 0 DRIVERS PORT 2 DRIVERS VCC LOW VOLTAGE DETECT VSS POWER ON DETECT A RAM ADDR REGISTER B RAM PORT 0 LATCH PORT 2 LATCH ROM/ EPROM B REGISTER ACC STACK POINTER PROGRAM ADDRESS REGISTER TMP2 TMP1 BUFFER ALU WATCHDOG TIMER B A PSEN ALE EA RST PD TIMING AND CONTROL INSTRUCTION REGISTER PSW SFRs TIMERS PCA PC INCREMENTER PROGRAM COUNTER DPTR CLK AND OSC FAILURE DETECT PORT 1 LATCH 10-BIT ANALOG TO DIGITAL CONVERTER PORT 1 DRIVERS PORT 3 LATCH PWM OSCILLATOR PORT 3 DRIVERS COMPARATOR BLOCK XTAL1 XTAL2 +AVCC P3.0-P3.7 P1.0-P1.5 –AVSS SU00255B 1998 Jun 04 3 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 LOGIC SYMBOL VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 XTAL2 SECONDARY FUNCTIONS RST EA/VPP PSEN SECONDARY FUNCTIONS ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD CMP3+ CMP2+ CMP1+ CMPR– CMP0+ CMP0– ADDRESS BUS ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 ADIN5 PWM1/ECI CEX4/PWM0 T2/CS# T2EX/A0 CEX3/CMP3 CEX2/CMP2 CEX1/CMP1 CEX0/CMP0 PORT 3 PORT 2 PORT 1 SU00254A PIN CONFIGURATIONS 44-pin Plastic Quad Flat Pack 44 34 7 1 33 LCC PQFP 17 Plastic Leaded Chip Carrier 6 1 40 39 11 23 29 18 12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function ADIN3/P1.3 ADIN4/P1.4 ADIN5/P1.5 RST RxD/P3.0 NC* TXD/P3.1 INT0/P3.2/CMP3+ INT1/P3.3/CMP2+ T0/P3.4/CMP1+ T1/P3.5/CMPR– WR/P3.6/CMP0+ RD/P3.7CMP0– XTAL2 XTAL1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 22 Function VSS NC* P2.0/A8/CEX0/CMP0 P2.1/A9/CEX1/CMP1 P2.2/A10/CEX2/CMP2 P2.3/A11/CEX3/CMP3 P2.4/A12/T2EX/A0 P2.5/A13/T2/CS P2.6/A14/CEX4/PWM0 P2.7/A15/PWM1/ECI PSEN ALE/PROG NC* EA/VPP P0.7/AD7/DB7 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6/DB6 P0.5/AD5/DB5 P0.4/AD4/DB4 P0.3/AD3/DB3 P0.2/AD2/DB2 P0.1/AD1/DB1 P0.0/AD0/DB0 VCC NC* +VREF/AVCC –VREF/AVSS ADIN0/P1.0 ADIN1/P1.1 ADIN2/P1.2 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NC* +VREF/AVCC –VREF/AVSS ADIN0/P1.0 ADIN1/P1.1 ADIN2/P1.2 ADIN3/P1.3 ADIN4/P1.4 ADIN5/P1.5 RST RxD/P3.0 NC* TxD/P3.1 INT0/P3.2/CMP3+ INT1/P3.3/CMP2+ Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function T0/P3.4/CMP1+ T1/P3.5/CMPR– WR/P3.6/CMP0+ RD/P3.7/CMP0– XTAL2 XTAL1 VSS 28 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15/PWM1/ECI PSEN ALE/PROG NC* EA/VPP P0.7/AD7/DB7 P0.6/AD6/DB6 P0.5/AD5/DB5 P0.4/AD4/DB4 P0.3/AD3/DB3 P0.2/AD2/DB2 P0.1/AD1/DB1 P0.0/AD0/DB0 VCC NC* P2.0/A8/CEX0/CMP0 P2.1/A9/CEX1/CMP1 P2.2/A10/CEX2/CMP2 P2.3/A11/CEX3/CMP3 P2.4/A12/T2EX/A0 P2.5/A13/T2/CS P2.6/A14/CEX4/PWM0 * NO INTERNAL CONNECTION * NO INTERNAL CONNECTION SU00252A SU00253B 1998 Jun 04 4 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 PIN DESCRIPTIONS PIN NUMBER MNEMONIC DIP 20 40 39-32 LCC 22 44 43-36 QFP 16 38 37-30 TYPE I I I/O NAME AND FUNCTION Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is a bidirectional I/O port. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory (see Note 5). In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code bytes during parallel EPROM programming and outputs code bytes during verification. External pull-ups are required during program verification. During reset, the port register is loaded with 1’s. Port 0 has 4 output modes selected on a per bit basis by writing to the P0M1 and P0M2 Special Function Registers as follows: P0M1.x P0M2.x Mode Description 0 0 Open drain (default). See Note 1. 0 1 Weak pullup. See Note 2. 1 0 High impedance. See Note 3. 1 1 Push-pull. See Note 4. Port 0 is also the data I/O port for the Universal Peripheral Interface (UPI). When the UPI is enabled, port 0 must be configured as High-Z by the user. Input/Output through P0 is controlled by pin CS, WR, RD, and A0. Output is push-pull when enabled. Port 1: Port 1 is a 6-bit bidirectional I/O port with Schmitt trigger inputs. Port 1 receives the control signals during program memory verification and parallel EPROM programming. During reset, port 1 is configured as a high impedance analog input port. Digital push-pull outputs are enabled by writing 1’s to the P1M1 register. The programmer must take care to prevent digital outputs from switching while an A/D conversion is in progress. Port 1 has 3 output modes selected on a per bit basis by writing to the P1M1 and P1M2 special function registers as follows: P1M1.X P1M2.X Mode Description 0 0 A/D only. (High impedance) 0 1 Digital input only. High impedance (default). 1 X Push-pull. Port 1 pins also serve alternate functions as follows: P1.0/ADIN0 P1.1/ADIN1 P1.2/ADIN2 P1.3/ADIN3 P1.4/ADIN4 P1.5/ADIN5 Port 2: Port 2 is an 8-bit bidirectional I/O port. Port 2 emits the high-order address byte during accesses to external program and data memory that use 16-bit addresses (MOVX @DPTR) (see Note 5). In this application, it uses strong internal pull-ups when emitting 1s. Port 2 receives the high-order address byte during program verification and parallel EPROM programming. During reset, the port 2 pullups are turned on synchronously, and the port register is loaded with 1’s. Port 2 has the following output modes which can be selected on a per bit basis by writing to P2M1 and P2M0: P2M1.X P2M2.X Mode Description 0 0 Open drain. See Note 1. 0 1 Weak pullup (default). See Note 2. 1 0 High impedance. See Note 3. 1 1 Push-pull. See Note 4. Port 2 pins serve alternate functions as follows: P2.0 CEX0 PCA module 0 external I/O CMP0 comparator 0 output P2.1 CEX1 PCA module 1 external I/O CMP1 comparator 1 output P2.2 CEX2 PCA module 2 external I/O CMP2 comparator 2 output P2.3 CEX3 PCA module 3 external I/O CMP3 comparator 3 output P2.4 T2EX timer 2 capture input A0 UPI address input P2.5 T2 timer 2 external I/O — clock-out (programmable) CS UPI chip select input P2.6 CEX4 PCA module 4 external I/O PWM0 Pulse width modulator 0 output P2.7 ECI PCA count input PWM1 Pulse width modulator 1 output VSS VCC P0.0-0.7 P1.0-P1.5 3-8 5-9 42-44 1-3 I/O 3 4 5 6 7 8 P2.0-P2.7 21-28 4 5 6 7 8 9 24-31 42 43 44 1 2 3 18-25 I/O I/O I/O I/O I/O I/O I/O 21 22 23 24 25 26 27 28 24 25 26 27 28 29 30 31 18 19 20 21 22 23 24 25 1998 Jun 04 5 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 PIN DESCRIPTIONS (Continued) PIN NUMBER MNEMONIC +VREF/AVCC –VREF/AVSS P3.0-P3.7 DIP 1 2 10-17 LCC 2 3 11, 13-19 QFP 40 41 5, 7-13 TYPE I I I/O NAME AND FUNCTION A/D positive power supply A/D 0V reference Port 3: Port 3 is an 8-bit bidirectional I/O port. Port 3 pins that have 1s written to them can be used as inputs but will source current when externally pulled low (see DC Electrical Characteristics: IIL). During reset all pins will be synchronously driven high and will remain high until written to by software. Port 3 has the following output modes which can be selected on a per bit basis by writing to P3M1 and P3M2: P3M1.X 0 0 1 1 10 11 12 13 14 15 16 17 RST 9 11 13 14 15 16 17 18 19 10 5 7 8 9 10 11 12 13 4 I O I I I I O O I P3M2.X 0 1 0 1 Mode Description Open drain. See Note 1. Weak pullup (default). See Note 2. High impedance. See Note 3. Push-pull. See Note 4. ALE/PROG 30 33 27 I/O PSEN 29 32 26 O EA/VPP 31 35 29 I XTAL1 19 21 15 I XTAL2 18 20 14 O NOTES: 1. When Open Drain mode is selected, ports 0 and 2 have weak pulldowns to guarantee positive leakage current (see DC electrical characteristic IIH). 2. When Weak Pullup mode is selected, ports bits that have 1’s written to them can be used as inputs but will source current when externally pulled low (see DC electrical characteristic IIL). 3. When High Impedance mode is selected, all pullups and pulldowns are turned off. The only current sourced or sunk by the pin is the parasitic leakage current (see DC electrical characteristic IL2 or ILC, as applicable. 4. When Push-Pull mode is selected, strong pullups are on continuously when emitting 1’s (see DC electrical characteristic VOH). 5. When Open-Drain, Weak Pull-up, or Push-pull mode is selected. Port 3 pins serve alternate functions as follows: P3.0 RxD Serial receive port P3.1 TxD Serial transmit port (enabled only when transmitting serial data) P3.2 INT0 External interrupt 0 CMP3+ Comparator 3 positive input P3.3 INT1 External interrupt 1 CMP2+ Comparator 2 positive input P3.4 T0 Timer/counter 0 input CMP1+ Comparator 1 positive input P3.5 T1 Timer/counter 1 input CMPR– Common reference to comparators 1, 2, 3 P3.6 WR External data memory write strobe CMP0+ Comparator 0 positive input P3.7 RD External data memory read strobe CMP0– Comparator 0 negative input Reset: A low on this pin synchronously resets all port pins to a high state. The pin must be held low with the oscillator running for 24 oscillator cycles to initialize the internal registers. An internal diffused resistor to VCC permits a power on reset using only an external capacitor to VSS. RST has a Schmitt trigger input stage to provide additional noise immunity with a slow rising input voltage. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE is switched off if the bit 0 in the AUXR register (8EH) is set. This pin is also the program pulse input (PROG) during parallel EPROM programming. (See also Internal Reset on page 24.) Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 1FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 1FFFH. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If this pin is at VPP voltage during reset the device enters the in-circuit programming mode. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. 1998 Jun 04 6 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 Table 1. SYMBOL ACC* ADC0H# ADC1H# ADC2H# ADC3H# ADC4H# ADC5H# ADC0L# ADC1L# ADC2L# ADC3L# ADC4L# ADC5L# ADCON# ADCS# AUXR# B* CCAP0H# CCAP1H# CCAP2H# CCAP3H# CCAP4H# CCAP0L# CCAP1L# CCAP2L# CCAP3L# CCAP4L# CCAPM0# CCAPM1# CCAPM2# CCAPM3# CCAPM4# 87C576 Special Function Registers DESCRIPTION Accumulator A/D Channel 0 MSB A/D Channel 1 MSB A/D Channel 2 MSB A/D Channel 3 MSB A/D Channel 4 MSB A/D Channel 5 MSB A/D Channel 0 2-LSBits A/D Channel 1 2-LSBits A/D Channel 2 2-LSBits A/D Channel 3 2-LSBits A/D Channel 4 2-LSBits A/D Channel 5 2-LSBits A/D Control A/D Channel Select Auxiliary B register Module 0 Capture High Module 1 Capture High Module 2 Capture High Module 3 Capture High Module 4 Capture High Module 0 Capture Low Module 1 Capture Low Module 2 Capture Low Module 3 Capture Low Module 4 Capture Low Module 0 Mode Module 1 Mode Module 2 Mode Module 3 Mode Module 4 Mode DIRECT ADDRESS E0H AAH ABH ACH ADH AEH AFH 9AH 9BH 9CH 9DH 9EH 9FH B1H B2H 8EH F0H FAH FBH FCH FDH FEH EAH EBH ECH EDH EEH DAH DBH DCH DDH DEH – – – – – DF ECOM ECOM ECOM ECOM ECOM DE CR CAPP CAPP CAPP CAPP CAPP DD – CAPN CAPN CAPN CAPN CAPN DC CCF4 MAT MAT MAT MAT MAT DB CCF3 TOG TOG TOG TOG TOG DA CCF2 PWM PWM PWM PWM PWM D9 CCF1 ECCF ECCF ECCF ECCF ECCF D8 CCF0 00x00000B 00H 00H 00xxx000B – F7 – F6 – F5 – F4 SRST F3 TXI F2 LO F1 AO F0 ADF ADCE AD8M AMOD1 BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E7 E6 E5 E4 E3 E2 E1 E0 RESET VALUE 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H AMOD0 ASCA2 ASCA1 ASCA0 00H 00H xxxx0000B 00H xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB xxxxxxxxB x0000000B x0000000B x0000000B x0000000B x0000000B CCON*# CH# CL# CMOD# PCA Counter Control PCA Counter High PCA Counter Low PCA Counter Mode D8H F9H E9H D9H CF CIDL C7 WDTE C6 EC2DP EC2TDC – C5 EC1DP EC1TDC – C4 EC0DP EC0TDC – C3 C3RO EC3O CPS1 C2 C2RO EC2O CPS0 C1 C1RO EC1O ECF C0 C0RO EC0O CMP*# CMPE# DPTR: DPH DPL IE0*# Comparator Comparator Enable Data Pointer (2 bytes) Data Pointer High Data Pointer Low Interrupt Enable 0 C0H 92H 83H 82H EC3DP EC3TDC 00H 00H 00H 00H AF A8H EA IE1*# Interrupt Enable 1 E8H EOB * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. AE EC EIB AD ET2 EAD AC ES EC4 AB ET1 EC3 AA EX1 EC2 A9 ET0 EC1 A8 EX0 EC0 00H 00H 1998 Jun 04 7 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 Table 1. SYMBOL 87C576 Special Function Registers (Continued) DESCRIPTION DIRECT ADDRESS B8H F8H 80H 90H A0H B0H 84H 85H 94H 95H A4H A5H B4H B5H 87H D0H BCH BDH BEH BFH CBH CAH A9H B9H 99H 9F 9E SM1 8E TR1 CE EXF2 – 9D SM2 8D TF0 CD RCLK – 9C REN 8C TR0 CC TCLK – 9B TB8 8B IE1 CB EXEN2 – 9A RB8 8A IT1 CA TR2 – 99 TI 89 IE0 C9 C/T2 T2OE2 98 RI 88 IT0 C8 CP/RL2 DCEN 00H xxxxxxx0B 00H 00H 07H 8F TF1 CF TF2 98H 81H 88H C8H SM0/FE SMOD1 BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB BF BE PPC PIB 86 AD6 96 – A6 CEX4 B6 WR BD PT2 PAD 85 AD5 95 ADIN5 A5 T2 B5 T1 BC PS PC4 84 AD4 94 ADIN4 A4 T2EX B4 T0 BB PT1 PC3 83 AD3 93 ADIN3 A3 CEX3 B3 INT1 BA PX1 PC2 82 AD2 92 ADIN2 A2 CEX2 B2 INT0 B9 PT0 PC1 81 AD1 91 ADIN1 A1 CEX1 B1 TxD B8 PX0 PC0 80 AD0 90 ADIN0 A0 CEX0 B0 RxD – POB 87 AD7 97 – A7 ECI B7 RD RESET VALUE x0000000B 00H FFH FFH FFH FFH 00H 00H 00H 3FH 00H FFH 00H FFH IP0* IP1*# P0* P1* P2* P3* P0M1# P0M2# P1M1# P1M2# P2M1# P2M2# P3M1# P3M2# PCON PSW* PWCON# PWMP# PWM0# PWM1# RACAP2H# RACAP2L# Interrupt Priority 0 Interrupt Priority 1 Port 0 Port 1 Port 2 Port 3 Port 0 Output Mode 1 Port 0 Output Mode 2 Port 1 Output Mode 1 Port 1 Output Mode 2 Port 2 Output Mode 1 Port 2 Output Mode 2 Port 3 Output Mode 1 Port 3 Output Mode 2 Power Control Program Status Word PWM Control PWM Prescaler PWM Register 0 PWM Register 1 Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control Timer 2 Control SMOD0 OSF1 D5 F0 – POF1 D4 RS1 – LVF1 D3 RS0 PWMF WDT0F1 PD D1 – PWE1 IDL D0 P PWE0 00xxxx00B 00H 00H 00H 00H 00H 00H 00H 00H 00H xxxxxxxxB D7 CY – D6 AC – D2 OV EN/CLR SADDR# SADEN# SBUF SCON* SP TCON* T2CON* T2MOD# Timer 2 Mode Control C9H – * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1. Reset value depends on reset source. 2. Programmable clock-out 1998 Jun 04 8 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 Table 1. SYMBOL TH0 TH1 TH2# TL0 TL1 TL2# TMOD UCS# WDCON# 87C576 Special Function Registers (Continued) DESCRIPTION Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 Timer Mode UPI Control/Status Watchdog Timer Control DIRECT ADDRESS 8CH 8DH CDH 8AH 8BH CCH 89H 86H C4H GATE ST7 PRE2 C/T ST6 PRE1 M1 ST5 PRE0 M0 ST4 LVRE GATE UE OFRE C/T AF DPD M1 IBF WDRUN BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB RESET VALUE 00H 00H 00H 00H 00H 00H M0 OBE/OBF 00H 00H 11111111B 00H xxH xxH WDMOD WDL# Watchdog Timer Reload C1H WFEED1# Watchdog Feed 1 C2H WFEED2# Watchdog Feed 2 C3H * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1. Reset value depends on reset source. The 8XC576 has a number of failure detect circuits to prevent abnormal operating conditions. these failure detect circuits generate resets as shown in Figure 1. LOW ACTIVE RESET One of the most notable features on this part is the low active reset. The low active reset operates exactly the same as high active reset with the exception that the part is put into the reset mode by applying a low level to the reset pin. For power-on reset it is also necessary to invert the power-on reset circuit; connecting the 8.2K resistor from the reset pin to VCC and the 10µf capacitor from the reset pin to ground. Figure 1 shows the reset related circuitry. When reset the port pins on the 8XC576 are driven high synchronously. The 8XC576 also has Low voltage detection circuitry that will, if enabled, force the part to reset when VCC (on the part) fails below a set level. Low Voltage Reset is enabled by a normal reset. Low Voltage Reset can be disabled by clearing LVRE (bit 4 in the WDCON SFR) then executing a watchdog feed sequence (A5H to WFEED1 followed immediately by 5AH to WFEED2). In addition there is a flag (LVF) that is set if a low voltage condition is detected. The LVF flag is set even if the Low Voltage detection circuitry is disabled. Notice that the Low voltage detection circuitry does not drive the RST# pin so the LVF flag is the only way that the microcontroller can determine if it has been reset due to a low voltage condition. The 8XC576 has an on-chip power-on detection circuit that sets the POF (PCON.4) flag on power up or if the VCC level momentarily drops to 0V. This flag can be used to determine if the part is being started from a power-on (cold start) or if a reset has occurred due to another condition (warm start). The 8XC576 can be reset in software by setting the RST bit of the AUXR register (AUXR.3). See Figure 1 for reset diagram. POWER ON CLEAR / POWER ON FLAG An on-chip Power On Detect Circuit resets the 8XC576 and sets the Power Off Flag (PCON.4) on power up or if VCC drops to zero momentarily. The POF can only be cleared by software. The RST pin is not driven by the power on detect circuit. The POF can be read by software to determine that a power failure has occurred and can also be set by software. LOW VOLTAGE DETECT An on-chip Low Voltage Detect circuit sets the Low Voltage Flag (PCON.3) if VCC drops below VLOW (see DC Electrical Characteristics) and resets the 8XC576 if the Low Voltage Reset Enable bit (WDCON.4) is set. If the LVRE is cleared, the reset is disabled but LVF will still be set if VCC is low. The RST pin is not driven by the low voltage detect circuit. The LVF can be read by software to determine that VCC was low. The LVF can be set or cleared by software. OSCILLATOR FAIL DETECT An on-chip Oscillator Fail Detect circuit sets the Oscillator Fail Flag (PCON.5) if the oscillator frequency drops below OSCF for one or more cycles (see AC Electrical Characteristics: OSCF) and resets the 8XC576 if the Oscillator Fail Reset Enable bit (WDCON.3) is set. If OFRE is cleared, the reset is disabled but OSF will still be set if the oscillator fails. The RST pin is not driven by the oscillator fail detect circuit. The OSF can be read by software to determine that an oscillator failure has occurred. The OSF can be set or cleared by software. 1998 Jun 04 9 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 – – – – SRST TXI LO AO AUXR (8EH) VCC SMOD1 SMOD0 OSF POF LVF WDTOF PD IDL PCON (87H) POWER-ON DETECT VLOW (LOW VCC REFERENCE) + – OSC FREQ BELOW OSCF (MIN FREQUENCY) 8xC576 INTERNAL RESET RST WDTE PCA WATCHDOG WATCHDOG TIMER SHADOW REGISTER FOR WDCON SHADOW REGISTER WATCHDOG FEED PRE2 PRE1 PRE0 LVRE OFRE DPD WDRUN WDMOD WDCON (C4H) CIDL WDTE – – – CPS1 CPS0 ECF CMOD (D9H) SU00515B Figure 1. Reset Circuitry The PCA timer is a common time base for all five modules and can be programmed to run at: 1/12 the oscillator frequency, 1/4 the oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P2.7). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR as follows (see Figure 3): CPS1 CPS0 PCA Timer Count Source 0 0 1/12 oscillator frequency 0 1 1/4 oscillator frequency 1 0 Timer 0 overflow 1 1 External Input at ECI pin (P2.7) In the CMOD SFR are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during idle mode, WDTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. These functions are shown in Figure 3. The watchdog timer function is implemented in module 4 as implemented in other parts that have a PCA that are available on the market. However, if a watchdog timer is required in the target application, it is recommended to use the hardware watchdog timer that is implemented on the 87C576 separately from the PCA (see Figure 15). The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (refer to Figure 6). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set, The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags 10 TIMERS The 8XC576 has four on-chip timers. Timers 0 and 1 are identical in every way to Timers 0 and 1 on the 80C51. Timer 2 on the 8XC576 is identical to the 80C52 Timer 2 (described in detail in the 80C52 overview) with the exception that it is an up or down counter. To configure the Timer to count down the DCEN bit in the T2MOD special function register must be set and a low level must be present on the T2EX pin (P1.1). The Pulse Width Modulator (PWM) system can be used as a timer by disabling its outputs and monitoring its counter overflow flag, the PWMF bit in the PWCON register (see the PWM section for details). The Watchdog timer operation and implementation is similar to the 8XC550 (for additional information see the 8XC550 datasheet) with the exception that the reset values of the WDCON and WDL special function registers have been changed. The changes in these registers cause the watchdog timer to be enabled with a timeout of 16384 × TOSC when the part is reset. The watchdog can be disabled by executing a valid feed sequence and then clearing WDRUN (bit 2 in the WDCON SFR). In timer mode, the timer is controlled by toggling the WDRUN bit. The timeout flag, WDTOF, is set when the timer overflows and must be cleared in software. PROGRAMMABLE COUNTER ARRAY (PCA) The Programmable Counter Array is a special Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it in port 2. Module 0 is connected to P2.0(CEX0), module 1 to P2.1(CEX1), etc. The basic PCA configuration is shown in Figure 2. 1998 Jun 04 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 also can only be cleared by software. The PCA interrupt system shown in Figure 4. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Figure 7). The registers contain the bits that control the mode that each module will operate in. The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Figure 8 shows the CCAPMn settings for the various PCA functions. There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output. PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 2) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. Refer to Figure 9. 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 10). High Speed Output Mode In this mode the CEX output (on port 2) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set (see Figure 11). Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 12 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module’s capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module’s CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode. PCA Interrupt System The PCA on most 80C51 family devices provides a single interrupt source, EC (IE.6). The 8xC576 expands the flexibility of the PCA by providing additional interrupt sources for each of the five PCA modules, EC0 (IE1.0) through EC4 (IE1.4), in addition to the original interrupt source EC (IE.6). Any of these sources can be enabled at any time. It is possible for both a module source (EC0 through EC4) to be enabled at the same time that the single source, EC, is enabled. In this case, a module event will generate an interrupt for both the module source and the single source, EC. 16 BITS MODULE 0 P2.0/CEX0 MODULE 1 16 BITS PCA TIMER/COUNTER TIME BASE FOR PCA MODULES MODULE 3 MODULE FUNCTIONS: 16-BIT CAPTURE 16-BIT TIMER 16-BIT HIGH SPEED OUTPUT 8-BIT PWM WATCHDOG TIMER (MODULE 4 ONLY) MODULE 2 P2.1/CEX1 P2.2/CEX2 P2.3/CEX3 MODULE 4 P2.6/CEX4 SU00578 Figure 2. Programmable Counter Array (PCA) 1998 Jun 04 11 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 OSC/12 TO PCA MODULES OSC/4 CH TIMER 0 OVERFLOW EXTERNAL INPUT (P2.7/ECI) 00 01 10 11 CL OVERFLOW INTERRUPT 16–BIT UP COUNTER DECODE IDLE CIDL WDTE –– –– –– CPS1 CPS0 ECF CMOD (D9H) CF CR –– CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) SU00516 Figure 3. PCA Timer/Counter CF PCA TIMER/COUNTER CR –– CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) MODULE 0 IE1.0 EC0 IE0.7 EA TO INTERRUPT PRIORITY DECODER MODULE 1 IE1.1 EC1 IE0.7 EA MODULE 2 MODULE 3 IE0.6 EC MODULE 4 TO INTERRUPT PRIORITY DECODER IE0.7 EA TO INTERRUPT PRIORITY DECODER ECF CCAPMn.0 ECCFn IE1.2 EC2 IE0.7 EA TO INTERRUPT PRIORITY DECODER IE1.3 EC3 IE0.7 EA TO INTERRUPT PRIORITY DECODER IE1.4 EC4 IE0.7 EA TO INTERRUPT PRIORITY DECODER CMOD.0 SU00579 Figure 4. PCA Interrupt System 1998 Jun 04 12 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 CMOD Address = OD9H Reset Value = 00XX X000B – 5 – 4 – 3 CPS1 2 CPS0 1 ECF 0 CIDL Bit: Symbol CIDL WDTE – CPS1 CPS0 Function 7 WDTE 6 Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. Not implemented, reserved for future use.* PCA Count Pulse Select bit 1. PCA Count Pulse Select bit 0. CPS1 CPS0 Selected PCA Input** 0 0 1 1 0 1 0 1 0 1 2 3 Internal clock, fOSC ÷ 12 Internal clock, fOSC ÷ 4 Timer 0 overflow External clock at ECI/P2.7 pin (max. rate = fOSC ÷ 8) ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. ** –fOSC = oscillator frequency SU00686A Figure 5. CMOD: PCA Counter Mode Register CCON Address = OD8H Bit Addressable CF Bit: Symbol CF CR – CCF4 CCF3 CCF2 CCF1 CCF0 Function 7 CR 6 – 5 CCF4 4 CCF3 3 CCF2 2 CCF1 1 CCF0 0 Reset Value = 00X0 0000B PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. Not implemented, reserved for future use*. PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00036 Figure 6. CCON: PCA Counter Control Register 1998 Jun 04 13 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 CCAPMn Address CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 0DAH 0DBH 0DCH 0DDH 0DEH Reset Value = X000 0000B Not Bit Addressable – Bit: Symbol – ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Function Not implemented, reserved for future use*. Enable Comparator. ECOMn = 1 enables the comparator function. Capture Positive, CAPPn = 1 enables positive edge capture. Capture Negative, CAPNn = 1 enables negative edge capture. Match. When MATn = 1, a match of the PCA counter with this module’s compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. Toggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn pin to toggle. Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. 7 ECOMn 6 CAPPn 5 CAPNn 4 MATn 3 TOGn 2 PWMn 1 ECCFn 0 NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00037 Figure 7. CCAPMn: PCA Modules Compare/Capture Registers – X X X X X X X X ECOMn 0 X X X 1 1 1 1 CAPPn 0 1 0 1 0 0 0 0 CAPNn 0 0 1 1 0 0 0 0 MATn 0 0 0 0 1 1 0 1 TOGn 0 0 0 0 0 1 0 X PWMn 0 0 0 0 0 0 1 0 ECCFn 0 X X X X X 0 X No operation MODULE FUNCTION 16-bit capture by a positive-edge trigger on CEXn 16-bit capture by a negative trigger on CEXn 16-bit capture by a transition on CEXn 16-bit Software Timer 16-bit High Speed Output 8-bit PWM Watchdog Timer Figure 8. PCA Module Modes (CCAPMn Register) 1998 Jun 04 14 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 CF CR –– CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) PCA INTERRUPT (TO CCFn) PCA TIMER/COUNTER CH CL CEXn CAPTURE CCAPnH CCAPnL –– ECOMn 0 CAPPn CAPNn MATn 0 TOGn 0 PWMn 0 ECCFn CCAPMn, n= 0 to 4 (DAH – DEH) SU00749 Figure 9. PCA Capture Mode CF WRITE TO CCAPnH RESET CR –– CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) WRITE TO CCAPnL 0 1 ENABLE CCAPnH CCAPnL PCA INTERRUPT (TO CCFn) 16–BIT COMPARATOR MATCH CH CL PCA TIMER/COUNTER –– ECOMn CAPPn 0 CAPNn 0 MATn TOGn 0 PWMn 0 ECCFn CCAPMn, n= 0 to 4 (DAH – DEH) SU00750 Figure 10. PCA Compare Mode 1998 Jun 04 15 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 CF WRITE TO CCAPnH RESET CCAPnH CR –– CCF4 CCF3 CCF2 CCF1 CCF0 CCON (D8H) WRITE TO CCAPnL 0 1 ENABLE CCAPnL PCA INTERRUPT (TO CCFn) MATCH 16–BIT COMPARATOR TOGGLE CH CL CEXn PCA TIMER/COUNTER –– ECOMn CAPPn 0 CAPNn 0 MATn TOGn 1 PWMn 0 ECCFn CCAPMn, n: 0..4 (DAH – DEH) SU00751 Figure 11. PCA High Speed Output Mode CCAPnH CCAPnL 0 CL < CCAPnL ENABLE 8–BIT COMPARATOR CL >= CCAPnL 1 OVERFLOW CL PCA TIMER/COUNTER CEXn –– ECOMn CAPPn 0 CAPNn 0 MATn 0 TOGn 0 PWMn ECCFn 0 CCAPMn, n: 0..4 (DAH – DEH) SU00752 Figure 12. PCA PWM Mode 1998 Jun 04 16 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 WATCHDOG TIMER The watchdog timer is not directly loadable by the user. Instead, the value to be loaded into the main timer is held in an autoload register or is part of the mask ROM programming. In order to cause the main timer to be loaded with the appropriate value, a special sequence of software action must take place. This operation is referred to as feeding the watchdog timer. To feed the watchdog, two instructions must be sequentially executed successfully. No intervening instruction fetches are allowed, so interrupts should be disabled before feeding the watchdog. The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register. If WFEED1 is correctly loaded and WFEED2 is not correctly loaded, then an immediate underflow will occur. The watchdog timer subsystem has two modes of operation. Its principal function is a watchdog timer. In this mode it protects the system from incorrect code execution by causing a system reset when the watchdog timer underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. If the user does not employ the watchdog function, the watchdog subsystem can be used as a timer. In this mode, reaching the terminal count sets a flag. In most other respects, the timer mode possesses the characteristics of the watchdog mode. This is done to protect the integrity of the watchdog function. The watchdog timer subsystem consists of a prescaler and a main counter. The prescaler has 8 selectable taps off the final stages and the output of a selected tap provides the clock to the main counter. The main counter is the section that is loaded as a result of the software feeding the watchdog and it is the section that causes the system reset (watchdog mode) or time-out flag to be set (timer mode) if allowed to reach its terminal count. • Watchdog mode bit set to watchdog mode. • Watchdog is running. • Autoload register set to 00 (min. count). • Watchdog time-out flag is unchanged. • Prescaler is cleared. • Prescaler tap set to the highest divide. • Autoload takes place. The watchdog can be fed even though it is in the timer mode. Note that the operational concept is for the watchdog mode of operation, when coming out of a hardware reset, the software should load the autoload registers, set the mode to watchdog, clear the watchdog timeout flag, and then feed the watchdog (cause an autoload). The watchdog will now be starting at a known point. If the watchdog is in the watchdog mode and running and happens to underflow at the time the external RESET is applied, the watchdog time-out flag will be set. When the watchdog is in the watchdog mode and the watchdog underflows, the following action takes place (see Figure 17): • Autoload takes place. • Watchdog time-out flag is set • Mode bit unchanged. • Watchdog run bit unchanged. • Autoload register unchanged. • Prescaler tap unchanged. • All other device action same as external reset. Programming the Watchdog Timer Both the EPROM and ROM devices have a set of SFRs for holding the watchdog autoload values and the control bits. The watchdog time-out flag is present in the PCON register and operates the same in all versions. In the EPROM device, the watchdog parameters (autoload value and control) are always taken from the SFRs. In the ROM device, the watchdog parameters can be mask programmed or taken from the SFRs. The selection to take the watchdog parameters from the SFRs or from the mask programmed values is controlled by EA (external access). When EA is high (internal ROM access), the watchdog parameters are taken from the mask programmed values. If the watchdog is mask programmed to the timer mode, then the autoload values and the pre-scaler taps are taken from the SFRs. When EA is low (external access), the watchdog parameters are taken from the SFRs. The user should be able to leave code in his program which initializes the watchdog SFRs even though he has migrated to the mask ROM part. This allows no code changes from EPROM prototyping to ROM coded production parts. The run control bit only functions in timer mode and does not require a feed sequence to modify. Note that if the watchdog underflows, the program counter will start from 00H as in the case of an external reset. The watchdog time-out flag can be examined to determine if the watchdog has caused the reset condition. The watchdog time-out flag bit must be cleared by software. When the watchdog is in the timer mode and the timer software underflows, the following action takes place: • Autoload takes place. • Watchdog time-out flag is set • Mode bit unchanged. • Watchdog run bit unchanged. • Autoload register unchanged. • Prescaler tap unchanged. Watchdog Detailed Operation EPROM Device (and ROMless Operation: EA = 0) In the ROMless operation (ROM part, EA = 0) and in the EPROM device, the watchdog operates in the following manner (see Figure 15). Whether the watchdog is in the watchdog or timer mode, when external RESET is applied, the following takes place: Mask ROM Device (EA = 1) In the mask ROM device, the watchdog mode bit (WDMOD) is mask programmed and the bit in the watchdog command register is read only and reflects the mask programmed selection. If the mask programmed mode bit selects the timer mode, then the watchdog run bit (WDRUN) operates as described under EPROM Device. If the mask programmed bit selects the watchdog mode, then the watchdog run bit has no effect on the timer operation (see Figure 16). Watchdog Function The watchdog consists of a programmable prescaler and the main timer. The prescaler derives its clock from the on-chip oscillator. The prescaler consists of a divide by 2 followed by a 13 stage upcounter with taps from stage 6 through stage 13. This is shown in Figure 18. 1998 Jun 04 17 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 The tap selection is programmable. The watchdog main counter is a down counter clocked (decremented) each time the programmable prescaler overflows. The watchdog generates an underflow signal (and is autoloaded) when the watchdog is at count 0 and the prescaler clock decrements the watchdog. The watchdog is 8 bits long and the autoload value can range from 0 to FFH. (The autoload value of 0 is permissible since the prescaler is cleared upon autoload). This leads to the following user design equations. Definitions :tOSC is the oscillator period, N is the selected prescaler tap value, W is the main counter autoload value, tMIN is the minimum watchdog time-out value (when the autoload value is 0), tMAX is the maximum time-out value (when the autoload value is FFH), tD is the design time-out value. tMIN = tOSC × 2 × 64 tMAX = tMIN × 128 × 256 tD = tMIN × 2PRESCALER × (W + 1) (where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7) Note that the design procedure is anticipated to be as follows. A tMAX will be chosen either from equipment or operation considerations and will most likely be the next convenient value higher than tD. (If the watchdog were inadvertently to start from 00H, an underflow would be guaranteed, barring other anomalies, to occur within tMAX). The software must be written so that a feed operation takes place every tD seconds from the last feed operation. Some tradeoffs may need to be made. It is not advisable to include feed operations in minor loops or in subroutines unless the feed operation is a specific subroutine. Watchdog Control Register (WDCON) Address C4H The following bits of this register are read only in the ROM part when EA is high: WDMOD, DPD, OFRE, LVRE, PRE0, PRE1, and PRE2. That is, the register will reflect the mask programmed values. In the ROM part with EA high, these bits are taken from mask coded bits and are not readable by the program. WDRUN is read only in the ROM part when EA is high and WDMOD is in the watchdog mode. When WDMOD is in the timer mode, WDRUN functions normally. The parameters written into WDMOD, DPD, OFRE, LVRE, PRE0, PRE1, and PRE2 by the program are not applied directly to the watchdog timer subsystem. The watchdog timer subsystem is directly controlled by a second register which stores these bits. The transfer of these bits from the user register to the second control register takes place when the watchdog is fed. This prevents random code execution from directly foiling the watchdog function. This does not affect the operation where these bits are taken from mask coded values. The reset values of the WDCON and WDL registers will be such that the timer resets to the watchdog mode with a timeout period of 2 × 64 × 128 × tOSC. The watchdog timer does not generate an interrupt. Additional bits in WDCON are used to disable reset generation by the oscillator fail and low voltage detect circuits. WDCON can be written by software only by executing a valid watchdog feed sequence. WDCON Register Bit Definitions WDCON.7 PRE2 Prescaler Select 2, reset to 1 WDCON.6 PRE1 Prescaler Select 1, reset to 1 WDCON.5 PRE0 Prescaler Select 0, reset to 1 WDCON.4 LVRE Low Voltage Reset Enable, reset to 1 (enabled) WDCON.3 OFRE Oscillator Fail Reset Enable, reset to 1 (enabled) WDCON.2 DPD Disable Power Down WDCON.1 WDRUN Watchdog Run, reset to 1 (enabled) WDCON.0 WDMOD Watchdog Mode, reset to 1 (watchdog mode) Enhanced UART The UART operates in all of the usual modes that are described in the first section of this book for the 80C51. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The 8XC576 UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 20). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 19. The serial port transmitter data can be inverted by setting the TXI (AUXR.2) bit. For normal operation, the TXI bit should be cleared. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 21. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. 1998 Jun 04 18 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 TXD TXI INT. BUS D Q P3.1 LATCH PROGRAMMABLE OUTPUT BUFFER P3.1 PIN WRITE TO LATCH SU00711 Figure 13. TXI (AUXR.2) Bit Inverts the TxD Pin (P3.1) When Set CIDL WRITE TO CCAP4H WDTE –– –– –– CPS1 CPS0 ECF CMOD (D9H) RESET WRITE TO CCAP4L 0 1 ENABLE CCAP4H CCAP4L MATCH 16–BIT COMPARATOR RESET CH CL PCA TIMER/COUNTER –– ECOMn CAPPn 0 CAPNn 0 MATn 1 TOGn X PWMn 0 ECCFn X CCAPM4 (DEH) SU00042 Figure 14. PCA Watchdog Timer WDL WATCHDOG FEED SEQUENCE MOV WFEED1,#0A5H MOV WFEED2,#5AH (C1H) WDTOF (PCON.2) OSC/2 PRESCALER 8–BIT DOWN COUNTER RESET SHADOW REGISTER FOR WDCON PRE2 PRE1 PRE0 LVRE OFRE DPD WDRUN WDMOD WDCON (C4H) SU00657C Figure 15. Watchdog Timer in 87C576 and 80C576 / 83C576 (EA = 0) 1998 Jun 04 19 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 ROM–CODE CONTENT WDL WDCON ADDRESS 2031H 2030H WATCHDOG FEED SEQUENCE MOV WFEED1,#0A5H MOV WFEED2,#5AH OSC/2 PRESCALER 8–BIT DOWN COUNTER RESET WDTOF (PCON.2) 1 1 WDCON (C4H) PRE2 PRE1 PRE0 LVRE OFRE DPD WDRUN WDMOD SU00658C Figure 16. Watchdog Timer of 83C576 in Watchdog Mode (EA = 1, WDMOD = 1) ROM–CODE WDL WATCHDOG FEED SEQUENCE MOV WFEED1,#0A5H MOV WFEED2,#5AH (C1H) CONTENT WDCON ADDRESS 2030H OSC/2 PRESCALER 8–BIT DOWN COUNTER WDTOF (PCON.2) 0 WDCON (C4H) PRE2 PRE1 PRE0 LVRE OFRE DPD WDRUN WDMOD SU00659C Figure 17. Watchdog Timer of 83C576 in Timer Mode (EA = 1, WDMOD = 0) 1998 Jun 04 20 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 OSC/2 ÷64 ÷64 ÷128 ÷2 ÷256 ÷2 ÷512 ÷2 ÷1024 ÷2 ÷2 ÷2048 ÷4096 ÷2 ÷8192 ÷2 PRE2 PRE1 PRE0 000 001 010 011 DECODE 100 101 110 111 TO WATCHDOG DOWN COUNTER SU00660 Figure 18. Watchdog Prescaler SCON Address = 98H Bit Addressable SM0/FE Bit: 7 (SMOD0/1)* SM1 6 SM2 5 REN 4 TB8 3 RB8 2 Tl 1 Rl 0 Reset Value = 0000 0000B Symbol FE SM0 SM1 Function Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate** fOSC/12 variable fOSC/64 or fOSC/32 variable SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. REN TB8 RB8 Tl Rl NOTE: *SMOD0/1 is located at PCON.6, PCON.7 **fOSC = oscillator frequency SU00766 Figure 19. SCON: Serial Port Control Register 1998 Jun 04 21 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 D0 D1 D2 D3 D4 D5 D6 D7 D8 START BIT DATA BYTE ONLY IN MODE 2, 3 STOP BIT SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL SM0 / FE SM1 SM2 REN TB8 RB8 TI RI SCON (98H) SMOD1 SMOD0 – POF LVF GF0 GF1 IDL PCON (87H) 0 : SCON.7 = SM0 1 : SCON.7 = FE SU00044 Figure 20. UART Framing Error Detection Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0 1100 0000 1111 1110 1100 000X Slave 1 SADDR = SADEN = Given = SADDR = SADEN = Given = 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX Slave 2 In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. this effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. Slave 1 In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 Analog Comparators Four analog comparators are provided on chip. Three comparators have a common negative reference CMPR- and independent positive inputs CMP1+, CMP2+, CMP3+ on port 3. The fourth comparator has independent positive and negative inputs CMP0+ and CMP0- on port 2. The CMP register contains an output and enable bit for each comparator. Figure 22 shows the connection of the comparators. When the comparator is enabled, the port should be configured by the user as high impedance. 1998 Jun 04 22 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 D0 D1 D2 D3 D4 D5 D6 D7 D8 SM0 1 1 SM1 1 0 SM2 1 REN 1 TB8 X RB8 TI RI SCON (98H) RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS” – WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. SU00045 Figure 21. UART Multiprocessor Communication, Automatic Address Recognition CMP Register Bit Definitions CMP.7 enable comparator 3 CMP.6 enable comparator 2 CMP.5 enable comparator 1, CMP.4 enable comparator 0 CMP.3 comparator 3 output (read only) CMP.2 comparator 2 output (read only) CMP.1 comparator 1 output (read only) CMP.0 comparator 0 output (read only) All comparators are disabled automatically in power down mode. In idle mode unused comparators should be disabled by software to save power. A comparator can generate an interrupt that will terminate idle mode when used to drive a PCA capture input. The CMPE register contains bits to enable each comparator to drive external output pins or internal PCA capture inputs. When the comparator is configured for external output, the user must also configure the output port in one of its output modes. The comparator output is wire-ORed with the corresponding port SFR bit, so the SFR bit must also be set by software to enable the output. CMPE Register Bit Definitions CMPE.7 enables comparator 3 to drive CEX3 CMPE.6 enables comparator 2 to drive CEX2 CMPE.5 enables comparator 1 to drive CEX1 CMPE.4 enables comparator 0 to drive CEX0 CMPE.3 enables comparator 3 output on P2.3 CMPE.2 enables comparator 2 output on P2.2 CMPE.1 enables comparator 1 output on P2.1 CMPE.0 enables comparator 0 output on P2.0 When 1s are written to CMPE bits 7-4, the comparator outputs will drive the corresponding capture input. When 1s are written to CMPE bits 3-0 the comparator output will also drive the corresponding port 2 pin. If the comparator’s enabled to drive the capture input but not the port pin, then the port pin can be used for general purpose I/O. When a comparator output is enabled, the user will need to configure the port for one of its output modes. There are two special function registers associated with the comparators. They are CMP which contains the comparator enables and a bit that can be read by software to determine the state of each comparator’s output, and CMPE which controls whether the output from each comparator drives the associated output pin or a capture input associated with one of the PCA modules. The CMP registers bits 0–3 can be read by software to determine the state of the output of each comparator. To do this the associated comparator must be enabled but the output in port 2 can be disabled. This allows easy polling of the comparator output value without the need to use up a port pin. The CMPE register allows the comparator to drive the associated PCA module capture input, so that on compare a capture can be generated in the PCA. Bits 0–3 of this register enable the comparator output to drive the associated port 2 output circuitry. Used as a comparator output, the output mode for this port must be configured for output by the user and the port output SFR bit latch must be set. If the comparator is not enabled to drive the port 2 circuitry, the associated port 2 pin can be used for other I/O. This includes when a comparator is enabled to drive the capture input to a PCA module. Reduced EMI Mode There are two bits in the AUXR register that can be set to reduce the internal clock drive and disable the ALE output. AO (AUXR.0) when set turns off the ALE output. LO (AUXR.1) when set reduces the drive of the internal clock circuitry. Both bits are cleared on Reset. With LO set the 8XC576 will still operate at 12MHz, and will have reduced EMI in the range above 100MHz. 8XC576 Reduced EMI Mode AUXR (0X8E) –– –– –– –– RST TXI LO AO AO: LO: Turns off ALE output. Reduces drive of internal clock circuitry. 8XC576 spec’d to 12MHz when LO set. TXI: Inverts TxD when set. RST: Software reset. 1998 Jun 04 23 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 EC3TDC EC2TDC EC1TDC EC0TDC EC3OD * EC2OD * EC1OD * EC0OD * CMPE (92H) P3.6 / CMP0+ P3.7 / CMP0– + P2.0 / CMP0 – ENABLE TO CEX0 INPUT OF PCA MODULE 0 P2.1 / CMP1 – ENABLE TO CEX1 INPUT OF PCA MODULE 1 P2.2 / CMP2 – ENABLE TO CEX2 INPUT OF PCA MODULE 2 P2.3 / CMP3 P3.4 / CMP1+ + P3.3 / CMP2+ + P3.2 / CMP3+ P3.5 / CMPR– + – ENABLE TO CEX3 INPUT OF PCA MODULE 3 * : WILL DISABLE PULLUPS ON RELEVANT PINS EC3DP * EC2DP * EC1DP * EC0DP * C3RO C2RO C1RO C0RO CMP (C0H) SU00517C Figure 22. Analog Comparators INTERNAL RESET Internal resets (see Figure 1) generated by the power on, low voltage, software (SRST), watchdog and oscillator fail detect circuits are self timed to guarantee proper initialization of the 8XC576. Reset will be held approximately 24 oscillator periods after normal conditions are detected by all enabled detect circuits. Internal resets do not drive RST but will cause missing pulses on ALE. AMOD1 AMOD0 ASCA2 ASCA1 ASCA0 ADCON.4 – A/D mode select bit 1 ADCON.3 – A/D mode select bit 0 ADCON.2 – A/D channel address bit 2 ADCON.1 – A/D channel address bit 1 ADCON.0 – A/D channel address bit 0 Analog to Digital Converter The 8XC576 has a 6 channel10 bit successive approximation A/D converter with separate result registers for each channel. Operating modes are provided for single or multiple channel conversions and multiple conversions of a single channel without software intervention. The ADC can also be operated in 8 bit mode with faster conversion times. Registers ADC0H–ADC5H contain the MSBs and ADC0L–ADC5L bits 6 and 7 contain the 2 LSBs of the conversion result for each channel. The ADCS register determines which channels are converted in multiple channel modes. If the ADCS bit corresponding to a channel is set, that channel is converted, else if the bit is clear the channel is skipped. A/D Channel Select (ADCS) Register (Reset Value = 00H) ADCS5 ADCS.5 – A/D channel 5 select bit ADCS4 ADCS.4 – A/D channel 4 select bit ADCS3 ADCS.3 – A/D channel 3 select bit ADCS2 ADCS.2 – A/D channel 2 select bit ADCS1 ADCS.1 – A/D channel 1 select bit ADCS0 ADCS.0 – A/D channel 0 select bit A/D Control (ADCON) Register (Reset Value = 00H) ADF ADCON.7 – A/D conversion complete flag ADCE ADCON.6 – A/D conversion enable AD8M ADCON.5 – A/D 8-bit mode AMOD1 AMOD0 0 0 Single Conversion Mode – channel selected by bits ASCA2..0 in ADCON is converted, the result placed in the associated result registers; ADF is set on completion. 0 1 Mulitple Channel Scan Mode – all channels selected in the ADCS register are converted starting with the channel addressed by bits ASCA2..0 in ADON, conversion results are placed in the corresponding result registers for each channel. ADF is set when the last conversion is completed. Single Channel Multiple Conversion – channel selected by bits ASCA2..0 in ADCON is converted 6 times and all 6 results are saved in ADC0H–ADC5H and ADC0L–ADC5L, ADF is set when all conversions are complete. Multiple Channel Continuous – same as Multiple Channel Scan mode but repeats as long as ADCE=1, ADF is set when all channels have been converted once. Hardware will prevent the ADC from wiriting to the result registers while they are being read. 1 0 1 1 Flag ADF is set upon completion of a conversion, if the ADC interrupt enable bit EAD is set, the program will vector to the ADC interrupt location when ADF is set. 1998 Jun 04 24 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 PWMs The pulse width modulator system of the 8XC576 contains two PWM output channels. These channels generate pulses of programmable length and interval. The prescaler and counter are common to both PWM channels. The prescaler is loaded with the complement of the PWMP register during counter overflow, internal reset, and when EN/CLR# = 0. The repetition frequency is defined by the 8-bit prescaler which clocks the counter. The prescaler division factor = PWMP+1. Reading the PWMP gives the current reload value. The actual count of the prescaler cannot be read. The 8-bit counter counts from 0–254 inclusive. The value of the counter is compared to the contents of the compare registers PWM0 and PWM1. When the counter compares to the compare register, that register’s output goes LOW. When the counter reaches zero the output is set HIGH unless PWMn = 00H. The duty cycle of each channel is defined by the contents of its compare register and is in the range of 0 to 1, programmed in increments of 1/255. The outputs can be set continuously low by loading PWMn with 00H and continuously high by loading with FFH. The PWM counter is enabled with bit EN/CLR# of the PWCON register. Output to the port pin is separately enabled by setting the PWEn bits in the PWCON register. The counter remains active if EN/CLR# is set even if both PWEn bits are reset. The PWM function is reset by a chip reset. In idle mode, the PWM will function as configured by PWCON. In power-down the state of the PWM will freeze when the internal clock stops. If the chip is awakened with an external interrupt, the PWM will continue to function from its state when power-down was entered. The EN/CLR# bit of PWCON will clear the counter and load the contents of the PWMP into the prescaler when set LOW. If PWEn is set at this time the output will go HIGH unless PWMn is 00H. The repetition frequency is given by: f PWM + (510 f OSC (1 ) PWMP)) Pulse Width Modulator Control Register Bit Definitions (PWCON = BCH) PWMF PWCON.3 Counter overflow flag, must be cleared by software EN/CLR PWCON.2 Counter enable and counter/prescaler reset when Low PWE1 PWCON.1 PWM1 output to P2.7 pin enable PWE0 PWCON.0 PWM0 output to P2.6 pin enable Auxiliary Register Bit Definitions (AUXR =8EH) RST AUXR.3 Software reset bit TXI AUXR.2 SIO TxD invert LO AUXR.1 Low Speed, reduces internal clock drive AO AUXR.0 ALE Off, when set turns off ALE Interrupt Enable 0 (IE0) Register EA IE0.7 Enable all interrupts EC IE0.6 Enable PCA interrupt ET2 IE0.5 Enable Timer 2 interrupt ES IE0.4 Enable Serial I/O interrupt ET1 IE0.3 Enable Timer 1 interrupt EX1 IE0.2 Enable External interrupt 1 ET0 IE0.1 Enable Timer 0 interrupt EX0 IE0.0 Enable External interrupt 0 Interrupt Enable 1 (IE1) Register EOB IE1.7 Enable OBE interrupt EIB IE1.6 Enable IBF interrupt EAD IE1.5 Enable ADC interrupt EC4 IE1.4 Enable PCA module 4 interrupt EC3 IE1.3 Enable PCA module 3 interrupt EC2 IE1.2 Enable PCA module 2 interrupt EC1 IE1.1 Enable PCA module 1 interrupt EC0 IE1.0 Enable PCA module 0 interrupt Interrupt Priority 0 (IP0) Register IP0.7 (reserved) PPC IP0.6 PCA interrupt priority PT2 IP0.5 Timer 2 interrupt priority PS IP0.4 Serial I/O interrupt priority PT1 IP0.3 Timer 1 interrupt priority PX1 IP0.2 External interrupt 1 priority PT0 IP0.1 Timer 0 interrupt priority PX0 IP0.0 External interrupt 0 priority Interrupt Priority 1 (IP1) Register POB IP1.7 OBE interrupt priority PIB IP1.6 IBF interrupt priority PAD IP1.5 ADC interrupt priority PC4 IP1.4 PCA module 4 interrupt priority PC3 IP1.3 PCA module 3 interrupt priority PC2 IP1.2 PCA module 2 interrupt priority PC1 IP1.1 PCA module 1 interrupt priority PC0 IP1.0 PCA module 0 interrupt priority An oscillator frequency of 12MHz results in a repetition range of 92Hz to 23.5KHz. The high/low ratio of PWMn is PWMn/(255–PWMn) for PWMn values except 255. A PWMn value of 255 results in a high PWMn output. In order for the PWMn output to be used as a standard I/O pin, PWMn must be reset. The PWM counter can still be used as an internal timer by setting EN/CLR#. 1998 Jun 04 25 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 fOSC INTERNAL BUS 1/2 PWMP REG 8-BIT PRESCALER 8-BIT UP COUNTER 8-BIT DETECT OUTPUT BUFFER P2.6 PWM0 PWM1 8-BIT DETECT OUTPUT BUFFER P2.7 SU00256A Figure 23. Block Diagram of PWMs PCA Interrupt System The PCA on most 80C51 family devices provides a single interrupt source, EC (IE.6). The 8xC576 expands the flexibility of the PCA by providing additional interrupt sources for each of the five PCA modules, EC0 (IE1.0) through EC4 (IE1.4), in addition to the original interrupt source EC (IE.6). Any of these sources can be enabled at any time. It is possible for both a module source (EC0 through EC4) to be enabled at the same time that the single source, EC, is enabled. In this case, a module event will generate an interrupt for both the module source and the single source, EC. Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Source INT0 ADC TIMER 0 INT1 TIMER 1 SERIAL PCA0 PCA1 PCA2 PCA3 PCA4 PCA TIMER 2 UPI UPI Flag IE0 ADF TF0 IE1 TF1 RI,TI CC0 CC1 CC2 CC3 CC4 ECF TF2/EXF2 IBF OBE Vector 03H 3BH 0BH 13H 1BH 23H 43H 4BH 53H 5BH 63H 33H 2BH 6BH 73H highest priority from the host CPU bus, which qualifies RD and WR (these pins have no effect when CS=1). The A0 pin is an address input from the host CPU which selects either the port 0 output buffer or the UCS register to be output during a read operation. During a write operation, the value of the A0 pin is latched in the AF flag in the UCS register. The following is a summary of the UPI data control inputs: CS 0 0 0 0 1 RD 0 0 1 1 x WR 1 1 0 0 x A0 0 1 0 1 x read port 0 output buffer, clear OBF/set OBE read UPI control/ status register write data to input buffer set IBF, clear AF write command to input buffer set IBF, AF disable input/output lowest priority Power Control (PCON) Register SMOD1 SMOD0 OSF POF LVF WDTOF PD IDL PCON.7 PCON.6 PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 PCON.0 double baud rate bit SCON.7 access control oscillator fail flag power off flag low voltage flag watchdog timeout flag power down mode bit idle mode bit UNIVERSAL PERIPHERAL INTERFACE UPI mode allows the 8XC576 to function as a slave processor connected to a host CPU bus via port 0. The interface consists of port 0 input and output buffer registers and the UPI control/status register (UCS). UPI mode is enabled by setting the UPI enable bit (UE) in the UCS. When operating in UPI mode, port 0 pins should be programmed to High-Z (P0M1=1 and P0M2=0) by user firmware. Access to port 0 is controlled by inputs WR, RD, CS, and A0. RD and WR are the external read and write strobes controlled by the host CPU. CS is the chip select input, normally a decoded address UPI Control Status Register (UCS, Reset value = 00H) UCS.7 ST7 User defined status bit UCS.6 ST6 User defined status bit UCS.5 ST5 User defined status bit UCS.4 ST4 User defined status bit UCS.3 UE UPI Enable bit – if UE=1, UPI is enabled (read only AF, IBF, and OBE/OBF), if UE=0, UPI is disabled and port 0 functions normally. UCS.2 AF Address Flag – contains status of the A0 (address) pin during the last write. If A0=0, the input buffer should be interpreted as data by the 8XC576 software, if A0=1, the input buffer should be interpreted as a command. USC.1 IBF Input Buffer Full flag – set by hardware on trailing (rising) edge of WR when CS=0, cleared by hardware when port 0 SFR is read (by the 8XC576 software). USC.0 OBE/OBF Output Buffer Full flag – set by hardware during writes (by 8XC576 software) to the port 0 SFR, set/cleared by hardware on the trailing (rising) edge of RD when CS=0 and A0=0. NOTE: This bit is defined as OBE (1=empty) when read by the MCU, and, as OBF (—full) when read by the external host. The IBF and OBF flag bits reflect the status of the input/output buffers. The host CPU writes to the 8XC576 by driving data on the external bus connected to port 0 and strobing the WR pin while CS=0. The WR strobe latches port 0 data in the input buffer and sets the IBF flag on the trailing (rising) edge. When the 8XC576 reads from port 0 in UPI mode, it reads from the input buffer and 1998 Jun 04 26 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 clears the IBF. When the 8XC576 writes to port 0 in UPI mode, it writes to the output buffer which sets the OBF and clears the OBE flag. The host CPU can read the output buffer or the UCS register enabling the port 0 drivers, the OBF flag is cleared and the OBE flag is set when the output buffer is read. When the UPI is enabled, the AF, IBF, and OBE/OBF flags are read-only, and thus can only be modified by specific hardware events. The UPI runs in idle mode. It can interrupt the part out of Idle mode for all UPI write and data read operations. It will not interrupt out of idle mode for a UCS register read operation. idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. Also see UPI section. POWER-DOWN MODE In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. The control bits for the reduced power modes are in the special function register PCON. Power-down mode can be terminated with either a hardware reset or external interrupt. With an external interrupt INT0 or INT1 must be enabled and configured as level sensitive. Holding the pin low restarts to oscillator and bringing the pin back high completes the exit. Power-down mode can be disabled by the DPD bit in the WDCON register. Reset and waking up from power-down will also enable the DPD bit, therefore, the DPD bit must be cleared again before the power-down mode. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the Logic Symbol, page 4. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. DESIGN CONSIDERATIONS IDLE MODE In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the At power-on, the voltage on VCC must come up with RST low for a proper start-up. Table 2 shows the state of I/O ports during low current operating modes. Table 2. External Pin Status During Idle and Power-Down Modes MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data 1998 Jun 04 27 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 ROM CODE SUBMISSION When submitting ROM code for the 83C576, the following must be specified: 1. 8k byte user ROM data 2. 32 byte ROM encryption key 3. ROM security bits 4. The watchdog timer parameters. (See Watchdog Timer Specifications for definition of WDL and WDCON bits.) ADDRESS 0000H to 1FFFH 2000H to 201FH 2020H CONTENT DATA KEY SEC BIT(S) 7:0 7:0 0 COMMENT User ROM Data ROM Encryption Key FFH = no encryption ROM Security Bit 1 0 = enable security 1 = disable security ROM Security Bit 2 0 = enable security 1 = disable security PRE2:0 LVRE OFRE DPD WDRUN = 0, not ROM coded WDMOD Watchdog autoload value (see specification) 1 2030H WDCON 7:5 4 3 2 1 0 2031H WDL 7:0 Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. If the ROM code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box and send to Philips along with the code: Security Bit #1: Security Bit #2: Encryption: V V V Enabled Enabled No V V V Disabled Disabled Yes If Yes, must send key file. Watchdog/Timer Modes: Prescaler Value: V Watchdog Mode V Timer Mode (Value = 64, 128, 256, 512, 1024, 2048, 4096, 8192) Value Autoload Value (range 0–255): Low Voltage Reset (Value 0 or 1): Oscillator Fail Reset (Value 0 or 1): Power-Down (Value 0 or 1): 1998 Jun 04 28 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING –55 to +125 –65 to +150 0 to +13.0 –0.5 to +6.5 15 1.5 UNIT °C °C V V mA W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 1998 Jun 04 29 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; VCC = 5V ±10%, VSS = 0V TEST SYMBOL VIL VIL1 VIL2 VIH VIH1 HYS VOL VOL1 VOH VOH1 VOH2 VIO VCR IIL IIH IL2 ILA ICC PARAMETER Input low voltage (except Port 1, EA) Input low voltage (EA) Input low voltage (Port 1) Input high voltage (except Port 1, XTAL1, RST) Input high voltage (XTAL1, RST, Port 1) Hysteresis voltage (Port 1) Output voltage low (Ports 1, 2, 3) Output voltage low (Ports 0, ALE, PSEN) Output voltage high (Ports 1, 2, 3 in push-pull mode) Output voltage high (Port 0, ALE, PSEN) Output voltage high in weak pullup mode (Port 0, 2, 3) Offset voltage comparator inputs Common mode range comparator inputs Logical 0 input current (Ports 0, 2, 3) (weak pull-up) Input pulldown current (Port 0, Port2 in open drain mode) Input leakage current (EA, P0. 2. 3 High-Z) Input leakage current comparator/ADC inputs Power supply Active mode @ 16MHz5 Idle mode @ 16MHz Power-down mode Internal reset pull-up resistor Low VCC detect voltage Pin capacitance9 f = 1MHz current:7 VIN = 0.45V 0.45 < VIN < VCC 0.45 < VIN < VCC 0 < VIN < VCC See note 6 20 8 5 VIN = 0V 50 3.75 30 12 75 200 4.25 15 mA mA µA kΩ V pF 2 –10 –1.0 IOL = 1.6mA IOL = 3.2mA IOH = –1.6mA IOH = –3.2mA IOH = –10µA VCC–1.0 VCC–0.7 VCC–1.0 –35 0 +35 VCC –250 40 +10 +1.0 IIH < 2mA IIH < 2mA CONDITIONS MIN –0.5 –0.5 –0.5 0.2VCC+0.9 0.7VCC 200 0.45 0.45 LIMITS TYP1 MAX 0.2VCC–0.1 0.2VCC–0.45 0.3VCC VCC+0.5 VCC+0.5 UNIT V V V V V mV V V V V V mV V µA µA µA µA RRST VLOW CIO NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is between VIH and VIL. 5. ICCMAX at other frequencies can be determined from Figure 33. 6. See Figures 34 through 37 for ICC test conditions. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 10mA Maximum IOL per port pin: Maximum IOL per 8-bit port: 26mA 71mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. 20pF MAX for CERDIP package; 15pF MAX for all other packages. 1998 Jun 04 30 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 A/D CONVERTER DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; VCC = 5V ±10%, VSS = 0V TEST SYMBOL Static Characteristics R ILe DLe FSe OSe Resolution Integral non-linearity error 2, 5, 8 Differential non-linearity error2, 3, 4, 7, 8 Full Scale error Offset error 2, 8 LIMITS MIN MAX UNIT PARAMETER CONDITIONS Monotonic with no missing codes 10 ±2 ±1 ±3 ±2 Bits LSB LSB LSB LSB 2, 6, 8 Dynamic Characteristics tADC tADS Conversion time (including sampling time) Sampling tme 48tCY 8tCY µs µs Analog Input Characteristics AVIN CIA MCTC Ct Analog input voltage Analog input capacitance Channel-to-channel matching7 Crosstalk between inputs of port 17 0–100kHz AVSS – 0.2 AVDD + 0.2 15 ±1 –60 V pF LSB dB Power Requirements AVCC/VREF+ AICC Analog supply and reference voltage Analog supply current: operating: (16MHz) AVCC = VCC ± 0.2 AVCC = 6.0V 4.0 6.0 1.2 V mA NOTES: 1. The following condition must not be exceeded: VDD – 0.2V < AVDD < VDD + 0.2V. 2. Conditions: AVSS = 0V; AVCC = 4.997V; VCC = 5.0V. 3. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 24). 4. The ADC is monotonic; there are no missing codes. 5. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. (See Figure 24). 6. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. (See Figure 24). 7. Guaranteed by design. 8. To meet Error Specification, analog input voltage must be less than 1V/ms. (AV CC 1023) 1000 Slew Rate MAX + (V ms) 4 (12 Osc Freq (MHz)) For 16MHz @ 5.0V slew rate = 1.6V/ms. 1998 Jun 04 31 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 Offset error OSe 1023 Full Scale error FSe Gain error Ge 1022 1021 1020 1019 1018 (2) 7 Code Out 6 (1) 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 AVIN (LSBideal) Offset error OSe 1 LSB = (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Center of a step of the actual transfer curve. AVREF+ – AVREF– 1024 SU00710 Figure 24. ADC Conversion Characteristic 1998 Jun 04 32 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; VCC = 5V ±10%, VSS = 0V1, 2 VARIABLE CLOCK SYMBOL 1/tCLCL OSCF TR tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 28 28 28 28 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 12tCLCL 10tCLCL–133 2tCLCL–60 0 ns ns ns ns 26, 27 26, 27 26, 27 26, 27 26, 27 26, 27 26, 27 26, 27 26, 27 26, 27 26, 27 26, 27 26, 27 29 29 29 29 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time tCLCL–40 20 20 20 20 3tCLCL–50 4tCLCL–130 tCLCL–50 tCLCL–50 0 tCLCL+40 0 2tCLCL–60 8tCLCL–150 9tCLCL–165 3tCLCL+50 6tCLCL–100 6tCLCL–100 5tCLCL–165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 25 25 25 25 25 25 25 25 25 25 FIGURE 25 PARAMETER Oscillator frequency: Speed Version 8XC576 E Oscillator fail detect frequency Comparator response time ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 tCLCL–25 5tCLCL–105 10 tCLCL–30 3tCLCL–45 3tCLCL–105 2tCLCL–40 tCLCL–40 tCLCL–30 4tCLCL–100 MIN 6 0.6 MAX 16 5.5 10 UNIT MHz MHz µs ns ns ns ns ns ns ns ns ns ns ns External Clock tXHDV 28 Clock rising edge to input data valid 10tCLCL–133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 83C576/87C576 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 1998 Jun 04 33 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 UPI AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; VCC = 5V ±10%, VSS = 0V SYMBOL tAR tRA tRR tAD tRD tDF tAW tWA tWW tDW tWD CS, A setup to RD CS, A hold after RD RD pulse width CS, A to data out delay RD to data out delay RD to data float delay (guaranteed by design) CS, A setup to WR CS, A hold after WR WR pulse width Data setup to WR Data hold after WR 0 15 45 5 25 PARAMETER MIN 0 35 35 45 35 30 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. tLHLL ALE tAVLL tLLPL PSEN tPLPH tLLIV tPLIV tPLAZ tPXIX INSTR IN tLLAX tPXIZ PORT 0 A0–A7 A0–A7 tAVIV PORT 2 A0–A15 A8–A15 SU00006 Figure 25. External Program Memory Read Cycle 1998 Jun 04 34 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 ALE tWHLH PSEN tLLDV tLLWL RD tRLRH tAVLL PORT 0 tLLAX tRLAZ A0–A7 FROM RI OR DPL tRLDV tRHDX DATA IN tRHDZ A0–A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00025 Figure 26. External Data Memory Read Cycle ALE tWHLH PSEN tLLWL WR tWLWH tAVLL PORT 0 tLLAX tQVWX tWHQX A0–A7 FROM RI OR DPL DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00069 Figure 27. External Data Memory Write Cycle 1998 Jun 04 35 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 tXLXL CLOCK tQVXH OUTPUT DATA 0 WRITE TO SBUF tXHQX 1 2 3 4 5 6 7 tXHDV INPUT DATA VALID CLEAR RI VALID tXHDX SET TI VALID VALID VALID VALID VALID VALID SET RI SU00027 Figure 28. Shift Register Mode Timing VCC–0.5 0.45V 0.7VCC 0.2VCC–0.1 tCHCL tCLCX tCLCL tCHCX tCLCH SU00009 Figure 29. External Clock Drive VCC–0.5 0.2VCC+0.9 0.2VCC–0.1 0.45V NOTE: AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. SU00010 Figure 30. AC Testing Input/Output VLOAD+0.1V VLOAD VLOAD–0.1V TIMING REFERENCE POINTS VOH–0.1V VOL+0.1V NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA. SU00011 Figure 31. Float Waveform 1998 Jun 04 36 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 AO, CS tAR tAW RD WR tRR tWW tRA tWA tRD tAD D0–D7 tDW tDF tWD SU00518 Figure 32. UPI Read/Write Cycles 30 MAX ACTIVE 25 20 TYP ACTIVE ICC (mA) 15 MAX IDLE 10 TYP IDLE 5 0 0 4 5 10 FREQUENCY (MHz) 15 16 20 SU00245 Figure 33. ICC vs. FREQ Valid only within frequency specifications of the device under test VCC ICC VCC AVSS RST EA (NC) CLOCK SIGNAL XTAL2 AVCC XTAL1 VSS VCC SU00661 Figure 34. ICC Test Condition, Active Mode All other pins are disconnected 1998 Jun 04 37 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 VCC ICC VCC VCC RST AVCC AVCC AVSS EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS SU00662 Figure 35. ICC Test Condition, Idle Mode All other pins are disconnected VCC–0.5 0.45V 0.7VCC 0.2VCC–0.1 tCHCL tCLCX tCLCL tCHCX tCLCH SU00009 Figure 36. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns VCC VCC VCC RST AVCC AVSS EA (NC) XTAL2 XTAL1 VSS ICC SU00663A Figure 37. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V 1998 Jun 04 38 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 EPROM CHARACTERISTICS To put the 87C576 in the parallel EPROM programming mode, PSEN must be held high during power up, then driven low with reset active. The 87C576 is programmed by using a modified Quick-Pulse Programming™ algorithm. The 87C576 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C576 manufactured by Philips. Table 3 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 38 and 39. Figure 40 shows the circuit configuration for normal program memory verification. Quick-Pulse Programming (Parallel) The setup for microcontroller quick-pulse programming is shown in Figure 38. Note that the 87C576 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 3 and 2, as shown in Figure 38. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 1 specified in Table 3 are held at the ‘Program Code Data’ levels indicated in Table 3. The ALE/PROG is pulsed low 25 times as shown in Figure 39. To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the ‘Pgm Encryption Table’ levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 25 pulse programming sequence using the ‘Pgm Security Bit’ levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. On-Board Programming (OBP) The On-Board Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the 87C576 through the serial port. The OBP function is invoked by having the EA/VPP pin at the VPP voltage level at the time that the part exits reset. The OBP function only requires that the TxD, RxD, VSS, VCC, and VPP pins be connected to an external circuit in order to use this feature. The OBP feature provides for the use of a wide range of baud rates independent of the oscillator frequency used. It is also adaptable to a wide range of oscillator frequencies. The OBP facility provides for both auto-echo and no-echo of received characters. The OBP feature requires that an initial character, an uppercase U, be sent to the 87C576 to establish the baud rate to be used. Once baud rate initialization has been performed, the OBP facility only accepts Intel Hex records. The record-type field of these hex records are used to indicate either commands or data for the OBP facility. The maximum number of data bytes in a record is limited to 16 (decimal). These commands/data are summarized below: Record Type 00 01 02 Command/Data Function Data record, programs the part with data indicated in record starting with load address in the record EOF record, no operation Specify timing parameters – rec length = 3 bytes – load address = 0000 – 1st byte = timer count for 50µs programming pulse – 2nd byte = timer count for 10µs delay between pulses – 3rd byte = 0AH Program security bits – rec length = 1 byte – load address = 0000 – 1st byte = sec bit values (xxxx xxB2B1) Display contents of USER EPROM array – rec length = 00 – load address = 0000 Verify security bit status – rec length = 00 – load address = 0000 Program Verification If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 3 and 2 as shown in Figure 40. The other pins are held at the ‘Verify Code Data’ levels indicated in Table 3. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P1.0 and P1.1 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (B6H) = B6H indicates 87C576 03 Program/Verify Algorithms Any algorithm in agreement with the conditions listed in Table 3, and which satisfies the timing specifications, is suitable. 04 05 ™Trademark phrase of Intel Corporation. 1998 Jun 04 39 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 Table 3. EPROM Programming Modes MODE RST 0 0 0 0 0 0 PSEN 0 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* 0* EA/VPP 1 VPP 1 VPP VPP VPP P2.7 0 1 0 1 1 1 P2.6 0 0 0 0 1 1 P1.1 0 1 1 1 1 0 P1.0 0 1 1 0 1 0 Read signature Program code data Verify code data Pgm encryption table Pgm security bit 1 Pgm security bit 2 NOTES: 1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin. 2. VPP = 12.75V ±0.25V. 3. VCC = 5V±10% during programming and verification. * ALE/PROG receives 5 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 50µs (±10µs) and high for a minimum of 10µs. 1998 Jun 04 40 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 +5V +5V AVCC A0–A7 0 1 1 P3 RST P1.0 P1.1 XTAL2 4–6MHz XTAL1 AVSS VSS 87C576 VCC P0 PGM DATA +12.75V 5 50µs PULSES TO GROUND 0 1 0 A8–A12 EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0–P2.4 SU00257B Figure 38. Programming Configuration 5 PULSES 1 ALE/PROG: 0 10µs MIN 1 ALE/PROG: 0 50µs+10 SU00664 Figure 39. PROG Waveform +5V +5V AVCC A0–A7 0 1 1 P3 RST P1.0 P1.1 XTAL2 4–6MHz XTAL1 AVSS VSS 87C576 VCC P0 PGM DATA 1 1 0 0 ENABLE 0 A8–A12 EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0–P2.4 SU00258B Figure 40. Program Verification 1998 Jun 04 41 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 41) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 40 60 48tCLCL 48tCLCL 48tCLCL µs µs µs µs PARAMETER MIN 12.5 MAX 13.0 50 12 UNIT V mA MHz PROGRAMMING* P3.0–P3.7 P2.0–P2.4 ADDRESS VERIFICATION* ADDRESS tAVQV PORT 0 DATA IN DATA OUT tDVGL tAVGL ALE/PROG tGHDX tGHAX tGLGH tSHGL tGHGL tGHSL LOGIC 1 EA/VPP LOGIC 0 LOGIC 1 tEHSH P2.7 ENABLE tELQV tEHQZ SU00207 * FOR PROGRAMMING VERIFICATION SEE FIGURE 38. FOR VERIFICATION CONDITIONS SEE FIGURE 40. Figure 41. EPROM Programming and Verification 1998 Jun 04 42 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 1998 Jun 04 43 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 1998 Jun 04 44 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 1998 Jun 04 45 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer 83C576/87C576 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 06-98 Document order number: 9397 750 04024 Philips Semiconductors 1998 Jun 04 46