87C652

INTEGRATED CIRCUITS 87C652/87C654 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C Product specification Replaces data sheets 87C652 of 1998 May 01 and 87C654 of 1998 May 01 1999 Jul 23 IC20 Data Handbook Philips Semiconductors Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 DESCRIPTION The 87C652/87C654 single-chip 8-Bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 87C652/87C654 has the same instruction set as the 80C51. Three versions of the derivative exist: 80C652—ROMless 83C652/83C654—8 Kbyte, 16 Kbyte ROM 87C652/87C654—8 Kbyte, 16 Kbyte OTP The ROMless and ROM are in separate datasheets. This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The 87C654 contains a non-volatile 16k × 8 EPROM and the 87C652 contains an 8k x 8 EPROM. Both have a volatile 256 × 8 read/write data memory, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a multi-source, two-priority-level, nested interrupt structure, an I2C interface, UART and on-chip oscillator and timing circuits. For systems that require extra capability, the 87C652/87C654 can be expanded using standard TTL compatible memories and logic. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. With a 16 MHz crystal, 58% of the instructions are executed in 0.75 µs and 40% in 1.5 µs. Multiply and divide instructions require 3 µs. PIN CONFIGURATIONS P1.0 P1.1 P1.2 P1.3 P1.4 1 2 3 4 5 6 7 8 9 PLASTIC DUAL IN-LINE PACKAGE 40 VCC 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA/VPP 30 ALE/PROG 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8 FEATURES P1.5 SCL/P1.6 SDA/P1.7 RST • 80C51 central processing unit • 16k × 8 EPROM or 8k x 8 EPROM expandable externally to 64k bytes • 256 × 8 RAM, expandable externally to 64k bytes RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 XTAL1 VSS 18 19 20 • Two standard 16-bit timer/counters • Four 8-bit I/O ports • I2C-bus serial I/O port with byte oriented master and slave functions • Full-duplex UART facilities • Power control modes – Idle mode – Power-down mode • Extended temperature range • OTP package available • Two speed ranges – 16 MHz – 20 MHz SU00259 ORDERING INFORMATION EPROM TEMPERATURE RANGE °C AND PACKAGE RANGE AND PACKAGE FREQ MHz 16 16 16 16 16 16 20 20 16 16 16 16 Drawing g Number SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT129-1 SOT187-2 SOT307-2 SOT187-2 S87C654-4N40 0 to +70, Plastic Dual In-line Package S87C654-4A44 0 to +70, Plastic Leaded Chip Carrier S87C654–4B44 0 to +70, Plastic Quad Flat Pack S87C654-5N40 –40 to +85, Plastic Dual In-line Package S87C654-5A44 –40 to +85, Plastic Leaded Chip Carrier S87C654-5B44 –40 to +85, Plastic Quad Flat Pack S87C654–7N40 0 to +70, Plastic Dual In-line Package S87C654–7A44 0 to +70, Plastic Leaded Chip Carrier S87C652-4N40 0 to +70, Plastic Dual In-line Package S87C652-4A44 0 to +70, Plastic Leaded Chip Carrier S87C652-4B44 0 to +70, Plastic Quad Flat Pack S87C652-5A44 –40 to +85, Plastic Leaded Chip Carrier NOTES: 1. For ROM see 83C654 data sheet and 83C652/80C652 data sheet 1999 Jul 23 2 853-1689 22042 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 BLOCK DIAGRAM FREQUENCY REFERENCE XTAL2 XTAL1 COUNTERS T0 T1 OSCILLATOR AND TIMING PROGRAM MEMORY (16K x 8 EPROM) DATA MEMORY (256 x 8 RAM) TWO 16-BIT TIMER/EVENT COUNTERS SDA CPU I2C SERIAL I/O SCL SHARED WITH PORT 1 INTERNAL INTERRUPTS 64K BYTE BUS EXPANSION CONTRTOL PROG SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFT PROGRAMMABLE I/O INT0 INT1 CONTROL PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS SERIAL IN SERIAL OUT EXTERNAL INTERRUPTS SHARED WITH PORT 3 SU00271 LOGIC SYMBOL VCC VSS ADDRESS AND DATA BUS SCL SDA RxD TxD INT0 INT1 T0 T1 WR RD ADDRESS BUS RST PORT 0 PORT 2 PORT 1 XTAL1 XTAL2 VPP/EA PSEN PROG/ALE ALTERNATE FUNCTIONS PORT 3 SU00262 1999 Jul 23 3 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS 6 1 40 PLASTIC QUAD FLAT PACK PIN FUNCTIONS 44 34 7 39 1 LCC 33 PQFP 17 29 11 23 18 28 12 Function NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 22 Function P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NC* P1.0 P1.1 P1.2 P.13 P1.4 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function NC* P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6/SCL P1.7/SDA RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 * NO INTERNAL CONNECTION SU00260 * NO INTERNAL CONNECTION SU00261 1999 Jul 23 4 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 PIN DESCRIPTIONS PIN NUMBER MNEMONIC VSS VCC P0.0–0.7 DIP 20 40 39–32 LCC 22 44 43–36 QFP 16 38 37–30 TYPE I I I/O NAME AND FUNCTION Ground: 0 V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the 87C654. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7 which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions include: SCL: I2C-bus serial port clock line. SDA: I2C-bus serial port data line. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. Program Store Enable: The read strobe to external program memory. When the 87C654 is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 1FFFH for 87C652 and 3FFFH for 87C654. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 3FFFH. This pin also receives the 12.75 V programming supply voltage (VPP) during EPROM programming. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. P1.0–P1.7 1–8 2–9 40–44, 1–3 I/O P1.6 P1.7 P2.0–P2.7 7 8 21–28 8 9 24–31 2 3 18–25 I/O I/O I/O P3.0–P3.7 10–17 11, 13–19 5, 7–13 I/O 10 11 12 13 14 15 16 17 RST 9 11 13 14 15 16 17 18 19 10 5 7 8 9 10 11 12 13 4 I O I I I I O O I ALE/PROG 30 33 27 I/O PSEN 29 32 26 O EA/VPP 31 35 29 I XTAL1 19 21 15 I XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively. 1999 Jul 23 5 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 Table 1. SYMBOL ACC* B* DPTR: DPH DPL 8XC652/654 Special Function Registers DESCRIPTION Accumulator B register Data pointer (2 bytes) Data pointer high Data pointer low DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION ADDRESS MSB LSB E0H F0H E7 F7 E6 F6 E5 F5 E4 F4 E3 F3 E2 F2 E1 F1 E0 F0 RESET VALUE 00H 00H 83H 82H AF AE AD ES1 BE BD PS1 86 AD6 96 SCL A6 A14 B6 WR – 9E SM1 A5 A13 B5 T1 – 9D SM2 A4 A12 B4 T0 – 9C REN A3 A11 B3 INT1 GF1 9B TB8 A2 A10 B2 INT0 GF0 9A RB8 A1 A9 B1 TXD PD 99 TI A0 A8 B0 RXD IDL 98 RI 85 AD5 95 AC ES0 BC PS0 84 AD4 94 AB ET1 BB PT1 83 AD3 93 AA EX1 BA PX1 82 AD2 92 A9 ET0 B9 PT0 81 AD1 91 A8 EX0 B8 PX0 80 AD0 90 00H 00H IE*# Interrupt enable A8H EA BF 0x000000B IP*# Interrupt priority B8H – 87 xx000000B P0* Port 0 80H AD7 97 FFH P1*# Port 1 90H SDA A7 FFH P2* Port 2 A0H A15 B7 FFH P3* PCON# Port 3 Power control B0H 87H RD SMOD 9F FFH 0xxx0000B S0CON*# S0BUF# Serial 0 port control Serial 0 data buffer 98H 99H SM0 00H xxxxxxxxB D7 PSW* S1DAT# SP S1ADR# Program status word Serial 1 data Stack pointer Serial 1 address D0H DAH 81H DBH CY D6 AC D5 F0 D4 RS1 D3 RS0 D2 OV D1 F1 D0 P 00H 00H 07H  SLAVE ADDRESS  SC4 DF SC3 DE ENS1 8E TR1 SC2 DD STA 8D TF0 SC1 DC STO 8C TR0 SC0 DB SI 8B IE1 0 DA AA 8A IT1 0 D9 CR1 89 IE0 GC 00H S1STA# Serial 1 status D9H 0 D8 CR0 88 IT0 F8H S1CON*# Serial 1 control D8H CR2 8F 00000000B TCON* TH1 TH0 TL1 TL0 Timer control Timer high 1 Timer high 0 Timer low 1 Timer low 0 88H 8DH 8CH 8BH 8AH TF1 00H 00H 00H 00H 00H TMOD Timer mode 89H GATE * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. C/T M1 M0 GATE C/T M1 M0 00H 1999 Jul 23 6 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the Logic Symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Idle Mode In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register PCON. Table 2 shows the state of the I/O ports during low current operating modes. I2C SERIAL COMMUNICATION—SIO1 The I2C serial port is identical to the I2C serial port on the 8XC552. The operation of this subsystem is described in detail in the 8XC552 section of this manual. Note that in both the 8XC652/4 and the 8XC552 the I2C pins are alternate functions to port pins P1.6 and P1.7. Because of this, P1.6 and P1.7 on these parts do not have a pull-up structure as found on the 80C51. Therefore P1.6 and P1.7 have open drain outputs on the 8XC652/4. Reset A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few Power-Down Mode In the power-down mode, the oscillator is stopped and the instruction to invoke Table 2. External Pin Status During Idle and Power-Down Mode MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data Serial Control Register (S1CON) – See Table 3 S1CON (D8H) CR2 ENS1 STA STO SI AA CR1 CR0 Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation. Table 3. Serial Clock Rates BIT FREQUENCY (kHz) AT fOSC CR2 0 0 0 0 1 1 1 1 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 6 MHZ 23 27 31.25 37 6.25 50 100 0.25 < 62.5 0 to 255 12 MHz 47 54 62.5 75 12.5 100 2001 0.5 < 62.5 0 to 254 16 MHz 62.5 71 83.3 100 17 1331 2671 0.65 < 55.6 0 to 253 20 MHz 78 891 1041 1251 21 1661 3341 0.81 < 69.4 0 to 253 fOSC DIVIDED BY 256 224 192 160 960 120 60 96 × (256 – (reload value Timer 1)) (Reload value range: 0 – 254 in mode 2) NOTE: 1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application. 1999 Jul 23 7 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C ABSOLUTE MAXIMUM RATINGS1, 2, 3 PARAMETER Storage temperature range Voltage on EA/VPP to VSS Voltage on any other pin to VSS Input, output current on any single pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING –65 to +150 –0.5 to + 13 –0.5 to + 6.5 ±5 1 UNIT °C V V mA W 87C652/87C654 NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. DEVICE SPECIFICATIONS SUPPLY VOLTAGE (V) TYPE S87C652-4 and S87C654-4 S87C652-5 and S87C654-5 S87C654–7 MIN. 4.5 4.5 4.5 MAX. 5.5 5.5 5.5 FREQUENCY (MHz) MIN. 3.5 3.5 3.5 MAX. 16 16 20 TEMPERATURE RANGE (°C) 0 to +70 –40 to +85 0 to +70 1999 Jul 23 8 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 DC ELECTRICAL CHARACTERISTICS VSS = 0 V TEST SYMBOL VIL VIL1 VIL2 VIH VIH1 VIH2 VOL VOL1 VOL2 VOH VOH1 IIL ITL IL1 IL2 ICC PARAMETER Input low voltage, except EA, P1.6/SCL, P1.7/SDA Input low voltage to EA Input low voltage to P1.6/SCL, P1.7/SDA1 Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA Input high voltage, XTAL1, RST Input high voltage, P1.6/SCL, P1.7/SDA1 Output low voltage, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA Output low voltage, port 0, ALE, PSEN Output low voltage, P1.6/SCL, P1.7/SDA Output high voltage, ports 1, 2, 3 Output high voltage; port 0 in external bus mode, ALE, PSEN, RST4 Logical 0 input current, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA Logical 1-to-0 transition current, ports 1, 2, 3, except P1.6/SCL, P1.7/SDA Input leakage current, port 0 Input leakage current, P1.6/SCL, P1.7/SDA Power supply current: Active mode @ 16 MHz7 Idle mode @ 16 MHz8 Power down mode9, 10 Power down mode9, 10 RRST CIO Internal reset pull-down resistor Pin capacitance Freq.=1 MHz 0 to +70°C –40 to +85°C 0 to +70°C –40 to +85°C 0 to +70°C –40 to +85°C 0 to +70°C –40 to +85°C IOL = 1.6mA2, 3 IOL = 3.2mA2, 3 IOL = 3.0mA IOH = –60µA IOH = –25µA IOH = –400µA IOH = –150µA VIN = 0.45V See note 5 0.45V < VI < VCC 0V < VI < 6.0V 0V < VCC < 6.0V See note 6 VCC=6.0V 25 6 50 135 50 150 10 mA mA µA µA kΩ pF 2.4 0.75VCC 2.4 0.75VCC –50 –75 –650 –750 ±10 ±10 0 to +70°C –40 to +85°C 0 to +70°C –40 to +85°C PART TYPE 0 to +70°C –40 to +85°C 0 to +70°C –40 to +85°C CONDITIONS MIN. –0.5 –0.5 –0.5 –0.5 –0.5 0.2VCC+0.9 0.2VCC+1.0 0.7VCC 0.7VCC+0.1 0.7VCC LIMITS MAX. 0.2VCC–0.1 0.2VCC–0.15 0.2VCC–0.3 0.2VCC–0.35 0.3VCC VCC+0.5 VCC+0.5 VCC+0.5 VCC+0.5 6.0 0.45 0.45 0.4 UNIT V V V V V V V V V V V V V V V V V µA µA µA µA µA µA µA 0 to +70°C –40 to +85°C NOTES: 1. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 0.3VCC will be recognized as a logic 0 while an input voltage above 0.7VCC will be recognized as a logic 1. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL = 10 mA per port pin; Maximum IOL = 26 mA total for Port 0; Maximum IOL = 15 mA total for Ports 1, 2, and 3; Maximum IOL = 71 mA total for all output pins. If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 4. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 5. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 6. See Figures 9 through 11 for ICC test conditions. 7. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5 V; VIH = VCC –0.5 V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VCC; fCLK = 16 MHz. See Figure 9. 8. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VCC –0.5 V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VCC; EA = RST = VSS; fCLK = 16 MHz. See Figure 10. 9. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VCC; EA = RST = VSS. See Figure 11. 10. 2V ≤ VPD ≤ VCCmax. 1999 Jul 23 9 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C AC ELECTRICAL CHARACTERISTICS1, 2 16 MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tAVLL tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tDW tWHQX tRLAZ tWHLH Shift Register tXLXL tQVXH tXHQX tXHDX tXHDV External Clock tCHCX tCLCX tCLCH tCHCL 6 6 6 6 High time3 Low time3 Rise time3 Fall time3 20 20 20 20 20 20 5 5 5 5 5 Serial port clock cycle time3 Output data setup to clock rising edge3 edge3 Output data hold after clock rising edge3 Input data hold after clock rising Clock rising edge to input data valid3 0.75 492 80 0 492 12tCLCL 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 Address valid to ALE low RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data setup time before WR Data hold after WR RD low to address float RD or WR high to ALE high 23 138 120 3 288 13 0 103 0 55 350 398 238 28 275 275 148 0 FIGURE 2 2 2 2 2 2 2 2 2 2 2 2 PARAMETER Oscillator frequency Speed Versions 87C654 –4, –5 ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 38 208 10 23 143 83 0 85 8 28 150 MIN MAX 87C652/87C654 VARIABLE CLOCK MIN 3.5 2tCLCL–40 tCLCL–55 tCLCL–35 4tCLCL–100 tCLCL–40 3tCLCL–45 3tCLCL–105 tCLCL–25 5tCLCL–105 10 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns tCLCL–35 6tCLCL–100 6tCLCL–100 5tCLCL–165 2tCLCL–70 8tCLCL–150 9tCLCL–165 3tCLCL–50 4tCLCL–130 tCLCL–60 7tCLCL–150 tCLCL–50 0 tCLCL–40 tCLCL+40 3tCLCL+50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns 10tCLCL–133 tCLCL – tLOW tCLCL – tHIGH 20 20 ns 10tCLCL–133 2tCLCL–117 0 ns ns ns ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. These values are characterized but not 100% production tested. 1999 Jul 23 10 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C AC ELECTRICAL CHARACTERISTICS1, 2 20 MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tAVLL tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tDW tWHQX tRLAZ tWHLH Shift Register tXLXL tQVXH tXHQX tXHDX tXHDV External Clock tCHCX tCLCX tCLCH tCHCL 6 6 6 6 High time3 Low time3 Rise time3 Fall time3 17 17 20 20 17 17 5 5 5 5 5 Serial port clock cycle time3 Output data setup to clock rising edge3 edge3 Output data hold after clock rising edge3 Input data hold after clock rising Clock rising edge to input data valid3 0.6 367 40 0 367 12tCLCL 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 3, 4 Address valid to ALE low RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data setup time before WR Data hold after WR RD low to address float RD or WR high to ALE high 25 100 125 20 220 25 0 75 0 72 250 285 200 25 200 200 160 0 FIGURE 2 2 2 2 2 2 2 2 2 2 2 2 PARAMETER Oscillator frequency: Speed Versions 87C654 –7, –8 ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 25 170 10 25 105 90 0 60 25 25 135 MIN MAX 87C652/87C654 VARIABLE CLOCK MIN 3.5 2tCLCL–40 tCLCL–25 tCLCL–25 4tCLCL–65 tCLCL–25 3tCLCL–45 3tCLCL–60 tCLCL–25 5tCLCL–80 10 MAX 20 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns tCLCL–25 6tCLCL–100 6tCLCL–100 5tCLCL–90 2tCLCL–28 8tCLCL–150 9tCLCL–165 3tCLCL–50 4tCLCL–75 tCLCL–30 7tCLCL–130 tCLCL–25 0 tCLCL–25 tCLCL+25 3tCLCL+50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns 10tCLCL–133 tCLCL – tLOW tCLCL – tHIGH 20 20 ns 10tCLCL–133 2tCLCL–60 0 ns ns ns ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. These values are characterized but not 100% production tested. 1999 Jul 23 11 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C AC ELECTRICAL CHARACTERISTICS – I2C INTERFACE SYMBOL PARAMETER INPUT 87C652/87C654 OUTPUT SCL TIMING CHARACTERISTICS tHD; STA tLOW tHIGH tRC tFC tSU; DAT1 tSU; DAT2 tSU; DAT3 tHD; DAT tSU; STA tSU; STO tBUF tRD START condition hold time SCL LOW time SCL HIGH time SCL rise time SCL fall time Data set-up time SDA set-up time (before rep. START cond.) SDA set-up time (before STOP cond.) Data hold time Repeated START set-up time STOP condition set-up time Bus free time SDA rise time ≥ 14 tCLCL ≥ 16 tCLCL ≥ 14 tCLCL ≤ 1 µs ≤ 0.3 µs ≥ 250 ns ≥ 250 ns ≥ 250 ns ≥ 0 ns ≥ 14 tCLCL ≥ 14 tCLCL ≥ 14 tCLCL ≤ 1µs > 4.0 µs1 > 4.7 µs1 > 4.0 µs1 –2 < 0.3 µs3 > 20 tCLCL – tRD > 1 µs1 > 8 tCLCL > 8 tCLCL – tFC > 4.7 µs1 > 4.0 µs1 > 4.7 µs1 –2 SDA TIMING CHARACTERISTICS tFD SDA fall time ≤ 0.3µs < 0.3 µs3 NOTES: 1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs. 3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 62 ns < tCLCL < 285 ns (16 MHz) > fOSC > 3.5 MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s. TIMING SIO1 (I2C) INTERFACE repeated START condition START or repeated START condition tRD STOP condition 0.7 VCC 0.3 VCC tBUF tFD tRC tFC tSU;STO 0.7 VCC 0.3 VCC tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tHD;DAT tSU;DAT2 tSU;STA START condition SDA (INPUT/OUTPUT) SCL (INPUT/OUTPUT) SU00107A 1999 Jul 23 12 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. tLHLL ALE tAVLL tLLPL PSEN tPLPH tLLIV tPLIV tPLAZ tPXIX INSTR IN tLLAX tPXIZ PORT 0 A0–A7 A0–A7 tAVIV PORT 2 A0–A15 A8–A15 SU00006 Figure 1. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL RD tRLRH tAVLL PORT 0 tLLAX tRLAZ A0–A7 FROM RI OR DPL tRLDV tRHDX DATA IN tRHDZ A0–A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH SU00177 Figure 2. External Data Memory Read Cycle 1999 Jul 23 13 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 ALE tWHLH PSEN tLLWL WR tWLWH tAVLL PORT 0 tLLAX A0–A7 FROM RI OR DPL tQVWX tDW DATA OUT tWHQX A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH SU00213 Figure 3. External Data Memory Write Cycle INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 tXLXL CLOCK tQVXH OUTPUT DATA 0 WRITE TO SBUF tXHQX 1 2 3 4 5 6 7 tXHDV INPUT DATA VALID CLEAR RI VALID tXHDX SET TI VALID VALID VALID VALID VALID VALID SET RI SU00027 Figure 4. Shift Register Mode Timing VCC–0.5 0.45V 0.7VCC 0.2VCC–0.1 tCHCL tCLCX tCLCL tCHCX tCLCH SU00009 Figure 5. External Clock Drive 1999 Jul 23 14 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 VCC–0.5 0.2VCC+0.9 0.2VCC–0.1 0.45V NOTE: AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. SU00010 Figure 6. AC Testing Input/Output VLOAD+0.1V VLOAD VLOAD–0.1V TIMING REFERENCE POINTS VOH–0.1V VOL+0.1V NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA. SU00011 Figure 7. Float Waveform VCC ICC VCC VCC VCC RST P0 87C652/4 (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS EA P1.6 P1.7 * * SU00272 Figure 8. ICC Test Condition, Active Mode All other pins are disconnected NOTE: * Ports 1.6 and 1.7 should be connected to VCC through resistors of sufficiently high value such that the sink current into these pins does not exceed the IOL1 specification. 1999 Jul 23 15 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 VCC ICC VCC RST EA P0 VCC 87C652/4 (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS P1.6 P1.7 * * SU00273 Figure 9. ICC Test Condition, Idle Mode All other pins are disconnected VCC–0.5 0.45V 0.7VCC 0.2VCC–0.1 tCHCL tCLCX tCLCL tCHCX tCLCH SU00009 Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 10 ns VCC ICC VCC RST EA P0 VCC 87C652/4 (NC) XTAL2 XTAL1 VSS P1.6 P1.7 * * SU00274 Figure 11. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2 V to 5.5 V NOTE: * Ports 1.6 and 1.7 should be connected to VCC through resistors of sufficiently high value such that the sink current into these pins does not exceed the IOL1 specification. 1999 Jul 23 16 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 EPROM CHARACTERISTICS The 87C652/87C654 is programmed by using a modified Quick-Pulse Programming™ algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87C652/87C654 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C652/87C654 manufactured by Philips Components. Table 4 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 12 and 13. Figure 14 shows the circuit configuration for normal program memory verification. shown in Figure 12. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 4 are held at the ‘Program Code Data’ levels indicated in Table 4. The ALE/PROG is pulsed low 25 times as shown in Figure 13. To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the ‘Pgm Encryption Table’ levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the lock bits, repeat the 25 pulse programming sequence using the ‘Pgm Lock Bit’ levels. After one lock bit is programmed, further programming of the code memory and encryption table is disabled. However, the other lock bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. Program Verification If lock bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 14. The other pins are held at the ‘Verify Code Data’ levels indicated in Table 4. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 99H Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in Figure 12. Note that the 87C652/87C654 is running with a 4 to 6 MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as Program/Verify Algorithms Any algorithm in agreement with the conditions listed in Table 4, and which satisfies the timing specifications, is suitable. Table 4. EPROM Programming Modes MODE Read signature Program code data Verify code data Pgm encryption table Pgm lock bit 1 RST 1 1 1 1 1 PSEN 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* EA/VPP 1 VPP 1 VPP VPP P2.7 0 1 0 1 1 P2.6 0 0 0 0 1 P3.7 0 1 1 1 1 P3.6 0 1 1 0 1 Pgm lock bit 2 1 0 0* VPP 1 1 0 0 NOTES: 1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin. 2. VPP = 12.75 V ±0.25 V. 3. VCC = 5 V±10% during programming and verification. * ALE/PROG receives 25 programming pulses while VPP is held at 12.75 V. Each programming pulse is low for 100 µs (±10 µs) and high for a minimum of 10 µs. ™Trademark phrase of Intel Corporation. 1999 Jul 23 17 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 +5V VCC A0–A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4–6MHz XTAL1 VSS P0 PGM DATA +12.75V 25 100µs PULSES TO GROUND 0 1 0 A8–A13 EA/VPP ALE/PROG 87C652/4 PSEN P2.7 P2.6 P2.0–P2.5 SU00275 Figure 12. Programming Configuration 1 ALE/PROG: 0 25 PULSES 1 ALE/PROG: 0 10µs MIN 100µs+10 SU00018 Figure 13. PROG Waveform +5V VCC A0–A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4–6MHz XTAL1 VSS P0 EA/VPP ALE/PROG PGM DATA 1 1 0 0 ENABLE 0 A8–A13 87C652/4 PSEN P2.7 P2.6 P2.0–P2.5 SU00276 Figure 14. Program Verification 1999 Jul 23 18 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 15) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL PARAMETER Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL µs µs µs µs MIN 12.5 MAX 13.0 50 6 UNIT V mA MHz PROGRAMMING* P1.0–P1.7 P2.0–P2.3 ADDRESS VERIFICATION* ADDRESS tAVQV PORT 0 DATA IN DATA OUT ALE/PROG tDVGL tAVGL tGHDX tGHAX tGLGH tSHGL tGHGL tGHSL LOGIC 1 EA/VPP LOGIC 0 LOGIC 1 tEHSH P2.7 ENABLE tELQV tEHQZ SU00270 * FOR PROGRAMMING VERIFICATION SEE FIGURE 12. FOR VERIFICATION CONDITIONS SEE FIGURE 14. Figure 15. EPROM Programming and Verification Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. 1999 Jul 23 19 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 1999 Jul 23 20 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 1999 Jul 23 21 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 1999 Jul 23 22 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 NOTES 1999 Jul 23 23 Philips Semiconductors Product specification 80C51 8-bit microcontroller 8K/16K, 256 OTP, I2C 87C652/87C654 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 © Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 07-99 Document order number: 9397-750-06607 Philips Semiconductors 1999 Jul 23 24