9535

INTEGRATED CIRCUITS PCA9535 16-bit I2C and SMBus, low power I/O port with interrupt Product data 2003 Jun 27 Philips Semiconductors Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 I2C/SMBus applications and was developed to enhance the Philips family of I2C I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, pushbuttons, LEDs, fans, etc. The PCA9535 consist of two 8-bit Configuration (Input or Output selection); Input, Output and Polarity inversion (Active HIGH or Active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion Register. All registers can be read by the system master. Although pin-to-pin and I2C address compatible with the PCF8575, software changes are required due to the enhancements and are discussed in Application Note AN469. The PCA9535 is identical to the PCA9555 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW. The PCA9535 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I2C address and allow up to eight devices to share the same I2C/SMBus. The fixed I2C address of the PCA9535 is the same as the PCA9554 allowing up to eight of these devices in any combination to share the same I2C/SMBus. FEATURES • Operating power supply voltage range of 2.3 V-5.5 V • 5 V tolerant I/Os • Polarity inversion register • Active LOW interrupt output • Low stand-by current • Noise filter on SCL/SDA inputs • No glitch on power-up • Internal power-on reset • 16 I/O pins which default to 16 inputs • 0 to 400 kHz clock frequency • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V • Latch-up testing is done to JESDEC Standard JESD78 which • Offered in three different packages: SO24, TSSOP24, and HVQFN24 exceeds 100 mA MM per JESD22-A115, and 1000 V CDM per JESD22-C101 DESCRIPTION The PCA9535 is a 24-pin CMOS device that provide 16 bits of General Purpose parallel Input/Output (GPIO) expansion for ORDERING INFORMATION PACKAGES 24-Pin Plastic SO 24-Pin Plastic TSSOP TEMPERATURE RANGE -40 to +85 °C -40 to +85 °C ORDER CODE PCA9535D PCA9535PW TOPSIDE MARK PCA9535D PCA9535PW DRAWING NUMBER SOT137-1 SOT355-1 SOT616-1 24-Pin Plastic HVQFN -40 to +85 °C PCA9535BS 9535 Standard packing quantities and other packing data are available at www.philipslogic.com/packaging . I2C is a trademark of Philips Semiconductors Corporation. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent. 2003 Jun 27 2 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 PIN CONFIGURATION — SO, TSSOP INT A1 A2 I/O0.0 I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 1 2 3 4 5 6 7 8 9 24 VDD 23 SDA 22 SCL 21 A0 20 I/O1.7 19 I/O1.6 18 I/O1.5 17 I/O1.4 16 I/O1.3 PIN CONFIGURATION —HVQFN 21 VDD 20 SDA 19 SCL 18 A0 17 I/O1.7 16 I/O1.6 15 I/O1.5 14 I/O1.4 13 I/O1.3 I/O1.2 12 I/O1.0 10 I/O1.1 11 7 8 I/O0.7 9 VSS 22 INT 24 A2 I/O0.0 I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 1 2 3 4 5 6 I/O0.6 23 A1 I/O0.6 10 I/O0.7 11 VSS 12 15 I/O1.2 14 I/O1.1 13 I/O1.0 TOP VIEW SU01438 su01683 Figure 1. Pin configuration — SO, TSSOP Figure 2. Pin configuration — HVQFN PIN DESCRIPTION SO, TSSOP PIN NUMBER 1 2 3 4-1 1 12 13-20 21 22 23 24 HVQFN PIN NUMBER 22 23 24 1-8 9 10-17 18 19 20 21 SYMBOL INT A1 A2 I/O0.0-I/O0.7 VSS I/O1.0-I/O1.7 A0 SCL SDA VDD FUNCTION Interrupt output (open drain) Address input 1 Address input 2 I/O0.0 to I/O0.7 Supply ground I/O1.0 to I/O1.7 Address input 0 Serial clock line Serial data line Supply voltage 2003 Jun 27 3 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 BLOCK DIAGRAM I/O1.0 I/O1.1 A0 A1 A2 WRITE pulse READ pulse 8-BIT INPUT/ OUTPUT PORTS I/O1.2 I/O1.3 I/O1.4 I/O1.5 I/O1.6 I/O1.7 I2C/SMBUS CONTROL I/O0.0 I/O0.1 SCL SDA I/O0.2 INPUT FILTER 8-BIT INPUT/ OUTPUT PORTS I/O0.3 I/O0.4 I/O0.5 I/O0.6 I/O0.7 VINT VSS POWER-ON RESET LP FILTER INT NOTE: ALL I/Os ARE SET TO INPUTS AT RESET WRITE pulse READ pulse VDD SU01439 Figure 3. Block diagram 2003 Jun 27 4 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 SIMPLIFIED SCHEMATIC OF I/Os DATA FROM SHIFT REGISTER CONFIGURATION REGISTER DATA FROM SHIFT REGISTER D FF WRITE CONFIGURATION PULSE WRITE PULSE CK Q D FF I/O PIN CK Q Q2 Q Q Q1 OUTPUT PORT REGISTER DATA VDD OUTPUT PORT REGISTER INPUT PORT REGISTER D FF READ PULSE CK Q Q VSS INPUT PORT REGISTER DATA TO INT DATA FROM SHIFT REGISTER WRITE POLARITY PULSE D FF CK Q POLARITY REGISTER DATA Q POLARITY INVERSION REGISTER SU01682 NOTE: At Power-on Reset, all registers return to default values. Figure 4. Simplified schematic of I/Os I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low impedance path that exists between the pin and either VDD or VSS. 2003 Jun 27 5 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 REGISTERS Command Byte Command 0 1 2 3 4 5 6 7 Register Input port 0 Input port 1 Output port 0 Output port 1 Polarity inversion port 0 Polarity inversion port 1 Configuration port 0 Configuration port 1 POWER-ON RESET When power is applied to VDD, an internal power-on reset holds the PCA9535 in a reset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9535 registers and SMBus state machine will initialize to their default states. DEVICE ADDRESS slave address 0 1 0 0 A2 A1 A0 R/W fixed programmable su01441 The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. Figure 5. PCA9535 address BUS TRANSACTIONS Registers 0 and 1 — Input Port Registers This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. Writing to the port registers Data is transmitted to the PCA9535 by sending the device address and setting the least significant bit to a logic 0 (see Figure 5 for device address). The command byte is sent after the address and determines which register will receive the data following the command byte. The eight registers within the PCA9535 are configured to operate as four register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Configuration Ports. After sending data to one register, the next data byte will be sent to the other register in the pair (see Figures 6 and 7). For example, if the first byte is sent to Output Port (register 3), then the next byte will be stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. Registers 2 and 3 — Output Port Registers bit default O0.7 1 O1.7 1 O0.6 1 O1.6 1 O0.5 1 O1.5 1 O0.4 1 O1.4 1 O0.3 1 O1.3 1 O0.2 1 O1.2 1 O0.1 1 O1.1 1 O0.0 1 O1.0 1 bit default This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register 6 and 7. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin value. Reading the port registers In order to read data from the PCA9535, the bus master must first send the PCA9535 address with the least significant bit set to a logic 0 (see Figure 5 for device address). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again but this time, the least significant bit is set to a logic 1. Data from the register defined by the command byte will then be sent by the PCA9535 (see Figures 8 , 9, and 10). Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other register in the pair. For example, if you read Input Port 1, then the next byte read would be Input Port 0. There is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data. Registers 4 and 5 — Polarity Inversion Registers bit default N0.7 0 N0.6 0 N0.5 0 N0.4 0 N0.3 0 N0.2 0 N0.1 0 N0.0 0 bit default N1.7 0 N1.6 0 N1.5 0 N1.4 0 N1.3 0 N1.2 0 N1.1 0 N1.0 0 This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with ‘1’), the Input Port data polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained. Registers 6 and 7 — Configuration Registers bit default C0.7 1 C0.6 1 C0.5 1 C0.4 1 C0.3 1 C0.2 1 C0.1 1 C0.0 1 Interrupt Output The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the input port register is read (see Figure 9). A pin configured as an output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. bit default C1.7 1 C1.6 1 C1.5 1 C1.4 1 C1.3 1 C1.2 1 C1.1 1 C1.0 1 This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is enabled as an output. At reset the device’s ports are inputs. 2003 Jun 27 6 2003 Jun 27 7 Philips Semiconductors 16-bit I2C and SMBus, low power I/O port with interrupt SCL 1 2 3 4 5 6 7 8 9 command byte data to port 0 1 0 A 0.7 DATA 0 0.0 A 1.7 acknowledge from slave data to port 1 DATA 1 1.0 A P slave address SDA S 0 1 0 0 A2 A1 A0 0 R/W A 0 0 0 0 0 0 start condition acknowledge from slave acknowledge from slave WRITE TO PORT DATA OUT FROM PORT 0 tpv DATA OUT FROM PORT 1 DATA VALID tpv SU01442 Figure 6. WRITE to output port registers SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 slave address SDA S 0 1 0 0 A2 A1 A0 0 R/W A 0 0 command byte data to register 1 0 A MSB acknowledge from slave DATA 0 LSB A MSB acknowledge from slave data to register DATA 1 LSB A P 0 0 0 1 start condition acknowledge from slave SU01443 Figure 7. WRITE to configuration registers PCA9535 Product data 2003 Jun 27 S 0 1 SCL 1 2 3 4 Philips Semiconductors 16-bit I2C and SMBus, low power I/O port with interrupt slave address acknowledge from slave acknowledge from slave slave address acknowledge from slave data from lower or upper byte of register acknowledge from master 0 0 A2 A1 A0 0 R/W A COMMAND BYTE A S 0 0 1 0 A2 A1 A0 1 R/W A MSB DATA first byte LSB A at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter data from upper or lower byte of register no acknowledge from master MSB DATA last byte LSB NA P SU01463 NOTE: Transfer can be stopped at any time by a STOP condition. Figure 8. READ from register 5 6 7 8 9 I0.x I1.x 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 I0.x 4 3 2 1 0 A 7 6 5 4 I1.x 3 2 1 0 1 P 8 SDA S 0 1 0 0 A2 A1 A0 1 A 7 6 5 4 3 R/W ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MASTER NON ACKNOWLEDGE FROM MASTER READ FROM PORT 0 DATA INTO PORT 0 READ FROM PORT 1 DATA INTO PORT 1 INT tIV tIR SU01464 PCA9535 NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to 00 (read input port port register). Figure 9. READ input port register — scenario 1 Product data 2003 Jun 27 9 Philips Semiconductors 16-bit I2C and SMBus, low power I/O port with interrupt SCL 1 2 3 4 5 6 7 8 9 I0.x I1.x A DATA 10 A I0.x DATA 03 A I1.x DATA 12 1 P SDA S 0 1 0 0 A2 A1 A0 1 A DATA 00 R/W ACKNOWLEDGE FROM SLAVE tph READ FROM PORT 0 ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MASTER tps ACKNOWLEDGE FROM MASTER NON ACKNOWLEDGE FROM MASTER DATA INTO PORT 0 DATA 00 DATA 01 tph DATA 02 DATA 03 tps READ FROM PORT 1 DATA INTO PORT 1 DATA 10 DATA 11 DATA 12 INT tIV tIR SU01651 NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to 00 (read input port port register). Figure 10. READ input port register — scenario 2 PCA9535 Product data Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 TYPICAL APPLICATION VDD VDD SCL MASTER CONTROLLER SDA INT GND I/O0.4 I/O0.5 PCA9535 VDD I/O0.6 I/O0.7 A2 I/O1.0 I/O1.1 A1 A0 I/O1.2 I/O1.3 I/O1.4 I/O1.5 I/O1.6 VSS I/O1.7 10 DIGIT NUMERIC KEYPAD Controlled Switch (e.g. CBT device) ALARM SUBSYSTEM 3 (e.g. alarm system) B 1.6 kΩ 1.6 kΩ 1.1 kΩ 2 kΩ 2 kΩ VDD SCL SDA INT I/O0.0 I/O0.1 I/O0.2 I/O0.3 ENABLE SUBSYSTEM 1 (e.g. temp sensor) INT SUBSYSTEM 2 (e.g. counter) RESET A NOTE: Device address configured as 0100100 for this example I/O0.0, I/O0.1, I/O0.2, configured as outputs I/O0.3, I/O0.4, I/O0.5, configured as inputs I/O0.6, I/O0.7, and I/O1.0 to I/O1.7 configured as inputs SW02094 Figure 11. Typical application Minimizing IDD when the I/O is used to control LEDs When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 11. Since the LED acts as a diode, when the LED is off the I/O VIN is about 1.2 V less than VDD. The supply current, IDD, increases as VIN becomes lower than VDD and is specified as ∆IDD in the DC characteristics table. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VDD and prevents additional supply current consumption when the LED is off. VDD 3.3 V 5V LED VDD 100 k VDD LED LEDx LEDx SW02086 SW02087 Figure 12. High value resistor in parallel with the LED Figure 13. Device supplied by a lower voltage 2003 Jun 27 10 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD VI/O II/O II IDD ISS Ptot Tstg Tamb Supply voltage DC input current on an I/O DC output current on an I/O DC input current Supply current Supply current Total power dissipation Storage temperature range Operating ambient temperature PARAMETER CONDITIONS MIN -0.5 VSS - 0.5 — — — — — -65 -40 MAX 6.0 6 ± 50 ± 20 160 200 200 +150 +85 UNIT V V mA mA mA mA mW °C °C 2003 Jun 27 11 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”. DC CHARACTERISTICS VDD = 2.3 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS Supplies VDD IDD Istbl Istbh VPOR VIL VIH IOL IL CI I/Os VIL VIH IOL LOW-level input voltage HIGH-level input voltage LOW-level output current VOL = 0.5 V; VDD = 2.3-5.5 V; Note 1 VOL = 0.7 V; VDD = 2.3-5.5 V; Note 1 IOH = -8 mA; VDD = 2.3 V; Note 2 IOH = -10 mA; VDD = 2.3 V; Note 2 VOH HIGH-level output voltage IOH = -8 mA; VDD = 3.0 V; Note 2 IOH = -10 mA; VDD = 3.0 V; Note 2 IOH = -8 mA; VDD = 4.75 V; Note 2 IOH = -10 mA; VDD = 4.75 V; Note 2 IIH IIL CI CO IOL VIL VIH ILI Input leakage current Input leakage current Input capacitance Output capacitance LOW-level output current LOW-level input voltage HIGH-level input voltage Input leakage current VOL = 0.4 V VDD = 5.5 V; VI = VDD VDD = 5.5 V; VI = VSS -0.5 2.0 8 10 1.8 1.7 2.6 2.5 4.1 4.0 — — — — 3 -0.5 2.0 -1 — — 8-20 10-24 — — — — — — — — 3.7 3.7 — — — — 0.8 5.5 — — — — — — — — 1 -1 5 5 — 0.8 5.5 1 V V mA mA V V V V V V µA µA pF pF mA V V µA Supply voltage Supply current Standby current Standby current Power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current Leakage current Input capacitance VOL = 0.4V VI = VDD = VSS VI = VSS Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs No load; VI = VDD or VSS 2.3 — — — — -0.5 0.7 VDD 3 -1 — — 135 0.25 0.25 1.5 — — — — 6 5.5 200 1 1 1.65 0.3 VDD 5.5 — +1 10 V µA µA µA V V V mA µA pF MIN TYP MAX UNIT input SCL; input/output SDA Interrupt INT Select Inputs A0, A1, A2 NOTES: 1. The total current sunk by all I/Os must be limited to 200 mA. 2. The total current sourced by all I/Os must be limited to 160 mA. 2003 Jun 27 12 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 SDA tF tLOW tR tSU;DAT tF tHD;STA tSP tR tBUF SCL S tHD;STA tHD;DAT tHIGH tSU;STA SR tSU;STD P S SU01469 Figure 14. Definition of timing AC CHARACTERISTICS SYMBOL fSCL tBUF tHD;STA tSU;STA tSU;STO tVD;ACK tHD;DAT tVD;DAT tSU;DAT tLOW tHIGH tF tR tSP Port Timing tPV tPS tPH tIV tIR Output data valid Input data set-up time Input data hold time Interrupt valid Interrupt reset — 150 1 — — 200 — — 4 4 — 150 1 — — 200 — — 4 4 ns ns µs µs µs Operating frequency Bus free time between STOP and START conditions Hold time after (repeated) START condition Repeated START condition setup time Set-up time for STOP condition Valid time of ACK Data in hold time Data out valid time3 Data set-up time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters condition2 PARAMETER STANDARD MODE I2C BUS MIN 0 4.7 4.0 4.7 4.0 0.3 0 300 250 4.7 4.0 — — — MAX 100 — — — — 3.45 — — — — — 300 1000 50 FAST MODE I2C BUS MIN 0 1.3 0.6 0.6 0.6 0.1 0 50 100 1.3 0.6 20 + 0.1Cb — 1 UNITS kHz µs µs µs µs µs ns ns ns µs µs ns ns ns MAX 400 — — — — 0.9 — — — — — 300 300 50 20 + 0.1Cb 1 Interrupt Timing NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. 4. tPV measured from 0.7VDD on SCL to 50% I/O output. 2003 Jun 27 13 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 VDD VIN PULSE GENERATOR RT D.U.T. VOUT CL RL TEST CIRCUIT FOR OUTPUTS DEFINITIONS RL = 1 kΩ CL = 50 pF RT = Termination resistance should be equal to ZOUT of pulse generators. su01760 Figure 15. tPV set-up conditions 2003 Jun 27 14 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 2003 Jun 27 15 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 2003 Jun 27 16 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm SOT616-1 2003 Jun 27 17 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 REVISION HISTORY Rev Date _1 20030627 Description Product data (9397 750 11681); ECN 853-2430 30019 dated 11 June 2003. Initial version 2003 Jun 27 18 Philips Semiconductors Product data 16-bit I2C and SMBus, low power I/O port with interrupt PCA9535 Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Level I Data sheet status[1] Objective data Product status[2] [3] Development Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com . Fax: +31 40 27 24825  Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 06-03 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . Document order number: 9397 750 11681 Philips Semiconductors 2003 Jun 27 19