ADC0820

Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 DESCRIPTION By using a half-flash conversion technique, the 8-bit ADC0820 CMOS A/D offers a 1.5µs conversion time while dissipating a maximum 75mW of power. The half-flash technique consists of 31 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC. The input to the ADC0820 is tracked and held by the input sampling circuitry, eliminating the need for an external sample-and-hold for signals slewing at less than 100mV/µs. For ease of interface to microprocessors, the ADC0820 has been designed to appear as a memory location or I/O port without the need for external interfacing logic. PIN CONFIGURATION D, F, N Packages VIN 1 20 19 18 17 16 15 14 13 12 11 TOP VIEW VDD NC OFL DB7 DB6 DB5 DB4 CS VREF(+) VREF(–) DB0 2 DB1 3 DB2 4 DB3 5 WR/RDY MODE RD INT 6 7 8 9 10 FEATURES GND • Built-in track-and-hold function • No missing codes • No external clocking • Single supply—5VDC • Easy interface to all microprocessors, or operates stand-alone • Latched 3-State outputs • Logic inputs and outputs meet both MOS and TTL voltage level specifications APPLICATIONS • Operates ratiometrically or with any reference value equal to or • 0V to 5V analog input voltage range with single 5V supply • No zero- or full-scale adjust required • Overflow output available for cascading • 0.3″ standard width 20-pin DIP ORDERING INFORMATION DESCRIPTION 20-Pin Plastic Dual In-Line Package (DIP) 20-Pin Plastic Small Outline (SO) package less than VDD • Microprocessor-based monitoring and control systems • Transducer/µP interface • Process control • Logic analyzers • Test and measurement TEMPERATURE RANGE 0 to +70°C 0 to +70°C ORDER CODE ADC0820CNEN ADC0820CNED DWG # 0408B 1021B August 31, 1994 568 853-1631 13721 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 BLOCK DIAGRAM VREF(+) OFL 4–BIT FLASG ADC (4MSBs) OFL DB7 DB6 DB5 DB4 VREF(–) VIN VREF(+) – ∑ + 4–BIT DAC VREF(–) VREF (+) 16 OUTPUT LATCH AND THREE–STATE BUFFERS 4–BIT FLASG ADC (4LSBs) DB3 DB2 DB1 DB0 VREF(–) TIMING AND CONTROL CIRCUITRY INT MODE WR/RDY CS RD PIN DESCRIPTION PIN NO 1 2 3 4 5 6 SYMBOL VIN DB0 DB1 DB2 DB3 WR/RDY Analog input; range=GND≤VIN≤VDD 3-state data output—Bit 0 (LSB) 3-state data output—Bit 1 3-state data output—Bit 2 3-state data output—Bit 3 DESCRIPTION WR-RD Mode WR: With CS Low, the conversion is started on the falling edge of WR. Approximately 800ns (the preset internal time out, tI) after the WR rising edge, the result of the conversion will be strobed into the output latch, provided that RD does not occur prior to this time out (see Figures 3a and 3b). RD Mode RDY: This is an open-drain output (no internal pull-up device). RDY will go Low after the falling edge of CS; RDY will go 3-State when the result of the conversion is strobed into the output latch. It is used to simplify the interface to a microprocessor system (see Figure 1). 7 Mode Mode: Mode selection input—it is internally tied to GND through a 30µA current source. RD Mode: When mode is Low. WR-RD Mode: When mode is High. 8 RD WR-RD Mode With CS Low, the 3-State data outputs (DB0-DB7) will be activated when RD goes Low. RD can also be used to increase the speed of the converter by reading data prior to the preset internal time out (TI ~ 800ns). If this is done, the data result transferred to output latch is latched after the falling edge of the RD (see Figures 3a and 3b). RD Mode With CS Low, the conversion will start with RD going Low; also, RD will enable the 3-State data outputs at the completion of the conversion. RDY going 3-State and INT going Low indicate the completion of the conversion (see Figure 1). 9 INT WR-RD Mode INT going Low indicates that the conversion is completed and the data result is in the output latch. INT will go Low ~ 800ns (the preset internal time out, tI) after the rising edge of WR (see Figure 3a); or INT will go Low after the falling edge of RD, if RD goes Low prior to the 800ns time out (see Figure 3b). INT is reset by the rising edge of RD or CS (see Figures 3a and 3b). August 31, 1994 569 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 PIN DESCRIPTION (Continued) PIN NO SYMBOL DESCRIPTION RD Mode INT going Low indicates that the conversion is completed and the data result is in the output latch. INT is reset by the rising edge of RD or CS (see Figure 1). 10 11 12 13 14 15 16 17 18 GND VREF(-) VREF(+) CS DB4 DB5 DB6 DB7 OFL Ground The bottom of resistor ladder, voltage range: GND≤VREF(-)≤VREF(+) The top of resistor ladder, voltage range: VREF(-)≤VREF(+)≤VDD. CS must be Low in order for the RD or WR to be recognized by the converter. 3-State data output—Bit 4 3-State data output—Bit 5 3-State data output—Bit 6 3-State data output—Bit 7 (MSB) Overflow output—if the analog input is higher than the VREF(+)- LSB, OFL will be low at the end of conversion. It can be used to cascade 2 or more devices to have more resolution (9, 10-bit). It is always active and never becomes 3-state. No connection Power supply voltage 19 20 NC VDD ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VDD Supply voltage Logic control inputs Voltage at other inputs and output TSTG PD Storage temperature range Maximum power dissipation3 TA=25°C(still-air) N package D package TSOLD TA Lead temperature (soldering, 10sec) Operating ambient temperature range ADC0820CNEN/CNED NOTES: 1. Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. 2. All voltages are measured with respect to GND, unless otherwise specified. 3. Derate above 25°C at the following rates: N package at 13.5mW/°C D package at 11.1mW/°C 1690 1390 300 TMIN≤TA≤TMAX 0 to +70 °C mW mW °C PARAMETER RATING 7 -0.2 to VDD+0.2 -0.2 to VDD+0.2 -65 to +150 UNIT V V V °C August 31, 1994 570 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 DC ELECTRICAL CHARACTERISTICS RD mode (Pin 7=0), VDD=5V, VREF(+)=5V, and VREF(-)=GND, unless otherwise specified. Limits apply from TMIN to TMAX. SYMBOL Resolution Unadjusted error1 RREF VREF(+) VREF(-) VIN Reference resistance Input voltage5 Input voltage Input voltage5 Maximum analog input leakage current Power supply sensitivity VIN(1) VIN(0) Logical “1” input voltage Logical “0” input voltage CS=VDD VIN=VDD VIN=GND VDD=5V±5% VDD=5.25V VDD=4.75V CS, WR, RD Mode CS, WR, RD Mode 2.0 3.5 GND GND ADC0820C 1 VREF(-) GND GND-0.1 -3 ±1/16 1.6 PARAMETER TEST CONDITIONS LIMITS Min 8 Typ3 8 Max 8 ±1 4 VDD VREF(+) VDD+0.1 3 ±1/4 VDD VDD 0.8 1.5 1 3 30 -1 2.4 4.5 4.6 4.74 V 200 µA µA UNIT bits LSB kΩ V V V µA LSB V V VIN(1)=5V; CS, RD IIN(1) IIN(0) Logical “1” input current Logical “0” input current VIN(1)=5V; WR VIN(1)=5V; Mode VIN(0)=0V; CS, RD, WR, Mode VDD=4.75V, IOUT=-360µA; VOUT(1) Logical “1” output voltage DB0-DB7, OFL, INT VDD=4.75V, IOUT=-10µA DB0-DB7, OFL, INT VOUT(0) Logical “0” output voltage VDD=4.75V, IOUT=1.6mA; DB0-DB7, OFL, INT, RDY VOUT=5V; DB0-DB7, RDY IOZ 3-state output current VOUT=0V; DB0-DB7, RDY VOUT=0V, DB0-DB7, OFL ISOURCE ISINK IDD VDD Output source current INT Output sink current Supply current Range VOUT=5V; DB0-DB7, OFL, INT, RDY CS=WR=RD=0 4.5 4.5 7 8 20 6 -3 6 12 0.2 0.4 3 V µA mA mA 15 5.5 mA V August 31, 1994 571 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 AC ELECTRICAL CHARACTERISTICS VDD = 5V, tR = tF = 20ns, VREF(+) = 5V, VREF(-) = 0V, and TA = 25°C, unless otherwise specified. SYMBOL tCRD tACCO tCWR-RD tWR tRD tACC1 PARAMETER Conversion time for RD mode Access time (delay from falling edge of RD to output valid) Conversion time for WR-RD mode Write time Read time Min Max Min TEST CONDITIONS Mode=0, Figure 1 Mode=0, Figure 1 Mode=VDD, tWR=600ns, tRD=600ns; Figures 3a and 3b Mode=VDD, Figures 3a and 3b2 Mode=VDD, Figures 3a and 3b2 Mode=VDD, tRDtI; Figure 3a, CL=15pF CL=100pF tI t1H, t0H tINTL tINTH tINTHWR tRDY tID tRI tP SR CVIN COUT CIN Internal comparison time Three-state control (delay from rising edge of RD to Hi-Z state) Delay from rising edge of WR to falling edge of INT Delay from rising edge of RD to rising edge of INT Delay from rising edge of WR to rising edge of INT Delay from CS to RDY Delay from INT to output valid Delay from RD to INT Delay from end of conversion to next conversion Slew rate, tracking Analog input capacitance Logic output capacitance Logic input capacitance Mode=VDD; Figures 2 and 3a, CL=50pF RL=1kΩ, CL=10pF Mode=VDD, CL=50pF tRD>tI; Figure 3a tRD tI) Figure 6. August 31, 1994 576 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 before reading the conversion result. INT will typically go Low 800ns after WR’s rising edge. However, if a shorter conversion time is desired, the processor need not wait for INT and can exercise a Read after only 600ns. If this is done, INT will immediately go Low and data will appear at the outputs. Stand-Alone (Figure 7) For stand-alone operation in WR-RD mode, CS and RD can be tied Low and a conversion can be started with WR. Data will be valid approximately 800ns following WR’s rising edge. This reference flexibility lets the input span not only be varied, but also offset from zero. The voltage at VREF(-) sets the input level which produces a digital output of all zeroes. Though VIN is not itself differential, the reference design affords nearly differential-input capability for most measurement applications. Figure 9 shows some of the configurations that are possible. Input Current Due to the unique conversion techniques employed by the ADC0820, the analog input behaves somewhat differently than in conventional devices. The A/D’s sampled data comparators take varying amounts of input current depending on which cycle the conversion is in. The equivalent input circuit of the ADC0820 is shown in Figure 10a. When a conversion starts (WR Low, WR-RD mode), all input switches close, connecting VIN to 31 1pF capacitors. Although the two 4-bit flash circuits are not both in their compare cycle at the same time, VIN still sees all input capacitors at once. This is because the MS flash converter is connected to the input during its compare interval and the LS flash is connected to the input during its zeroing phase. In other words, the LS ADC uses VIN as its zero-phase input. The input capacitors must charge to the input voltage through the on resistance of the analog switches (about 5kΩ to 10kΩ). In addition, about 12pF of input stray capacitance must also be charged. For large source resistances, the analog input can be modeled as an RC network as shown in Figure 10b. As RS increases, it will take longer for the input capacitance to charge. In RD mode, the input switches are closed for approximately 800ns at the start of the conversion. In WR-RD mode, the time that the switches are closed to allow this charging is the time that WR is Low. Since other factors force this time to be at least 600ns, input time constants of 100ns can be accommodated without special consideration. Typical total input capacitance values of 45pF allow RS to be 1.5kΩ without lengthening WR to give VIN more time to settle. Other Interface Considerations In order to maintain conversion accuracy, WR has a maximum width spec of 50µs. When the MS flash ADC’s sampled data comparators are in comparison mode (WR is Low), the input capacitors (C, Figure 5) must hold their charge. Switch leakage can cause errors if the comparator is left in this phase for too long. Since the MS flash ADC enters its zeroing phase at the end of a conversion, a new conversion cannot be started until this phase is complete. The minimum spec for this time is 500ns (tP in Figures 1, 2, 3a, and 3b). ANALOG CONSIDERATIONS Reference and Input The two VREF inputs of the ADC0820 are fully differential and define the zero- to full-scale input range of the A/D converter. This allows the designer to easily vary the span of the analog input since this range will be equivalent to the voltage difference between VIN(+) and VIN(-). By reducing VREF(VREF=VREF(+) -VREF(-)) to less than 5V, the sensitivity of the converter can be increased (i.e., if VREF=2V, then 1 LSB=7.8mV). The input/reference arrangement also facilitates ratiometric operation and, in many cases, the chip power supply can be used for transducer power as well as the VREF source. CS LOW RD LOW WR Input Filtering It should be made clear that transients in the analog input signal, caused by charging current flowing into VIN, will not degrade the A/D’s performance in most cases. In effect, the ADC0820 does not “look” at the input when these transients occur. The comparators’ outputs are not latched while WR is Low, so at least 600ns will be provided to charge the ADC’s input capacitance. It is INT DB0–DB7 Figure 7. WR-RD Mode (Pin 7 is High) Stand-Alone Operation August 31, 1994 577 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 WR 600ns • • MS COMPARATORS ZERO TO REFERENCE LADDER. LS COMPARATORS FLOAT • MS COMPARATORS COMPARE VIN TO THEIR REFERENCE LADDER TAP. THE COMPARATOR VIN • VLADDER TAP. • MS COMPARATORS OUT– PUTS ARE LATCHED. THE MS DAC IS SET. THE MS COMPARATOR FLOATS. LS COMPARATORS COM– PARE LSB SECTION OF REF– ERENCE LADDER • LS COMPARATORS OUTPUTS ARE LATCHED AND CAN BE READ • MS COMPARATORS RE TURN TO ZERO MODE. • LS COMPARATORS ZERO TO VIN THE COMPARATOR’S INPUT CAPACTORS TRACK VIN. • Figure 8. Operating Sequence (WR-RD Mode) VIN(+) IN+ VIN(+) IN+ VIN(+) IN+ VIN(–) GND VIN(–) GND GND 1.2k 5V REF (+) 5V REF (+) 5V 1.2k REF (+) 2.5V 2.5V REF(–) REF(–) VIN(–) REF(–) • CURRENT PATH MUST STILL EXIST FROM VIN(–) TO GROUND a. External Reference 2.5V Full-Scale b. Power Supply as Reference Figure 9. Analog Input Options c. Input not Referred to GND August 31, 1994 578 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 ≈12pF RS VIN RON RON 1pF RS 350 TO LSB R–LADDER 1pF VIN CS 12pF 31pF 15 LSB COMPARATORS RON RON 1pF TO LSB R–LADDER 1pF b. a. Figure 10. August 31, 1994 579 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 therefore not necessary to filter out these transients by putting an external cap on the VIN terminal, if an input amplifier that can settle within 600ns is used to drive the input. The NE530 is a suitable op amp for driving the input of the ADC0820. Inherent Sample-Hold Another benefit of the ADC0820’s input mechanism is its ability to measure a variety of high-speed signals without the help of an external sample-and-hold. In a conventional SAR type converter, regardless of its speed, the input must remain at least 1/2LSB stable throughout the conversion process if full accuracy is to be maintained. Consequently, for many high-speed signals, this signal must be externally sampled, and held stationary during the conversion. Sampled data comparators, by nature of their input switching, already accomplish this function to a large degree (Section 1.2). Although the conversion time for the ADC0820 is 1.5µs, the time through which VIN must be 1/2LSB stable is much smaller. Since the MS flash ADC uses VIN as its “compare” input and the LS ADC uses VIN as its “zero” input, the ADC0820 only “samples” VIN when WR is Low. Even though the two flashes are not done simultaneously, the analog signal is measured at one instant. The value of VIN approximately 100ns after the rising edge of WR (100ns due to internal logic propagation delay) will be the measured value. 25k Input signals with slew rates typically below 100mV/µs can be converted without error. However, because of the input time constants, and charge injection through the opened comparator input switches, faster signals may cause errors. Still, the ADC0820’s loss in accuracy for a given increase in signal slope is far less than what would be witnessed in a conventional successive approximation device. An SAR type converter with a conversion time as fast as 1µs would still not be able to measure a 5V, 1kHz sine wave without the aid of an external sample-and-hold. The ADC0820, with no such help, can typically measure 5V, 7kHz waveforms. VDD +5V 0.1µF 47µF VREF VIN INT RDY VREF(+) CS VIN RD VDD MODE VREF(–) GND DB7 DB0 Figure 11. 8-Bit Resolution Configuration 40k VIN (+4VCC, 3kHz MAX) 27k +5V 12k + WR RD +5V VREF(+) INT – VIN CS +5V VDD DB7 0.1µF 47µF VREF(–) GND MODE DB0 Figure 12. Telecom A/D Converter August 31, 1994 580 Philips Semiconductors Linear Products Product specification 8-Bit, high-speed, µP-compatible A/D converter with track/hold function ADC0820 +5V 0.1µF 47µF VDD MODE CS WR CS WR RD RD D8 VREF VIN VREF(+) VIN DB7 DB0 D0–D7 VREF(–) 1k GND OFL 5k +5V VDD 1k MODE CS WR RD VREF(+) VIN DB7 DB0 VREF(–) GND OFL Figure 13. 9-Bit Resolution Configuration August 31, 1994 581