ADC1112D125HN

ADC1112D125 Dual 11-bit ADC; CMOS or LVDS DDR digital outputs Rev. 2 — 3 March 2011 Product data sheet 1. General description The ADC1112D125 is a dual channel 11-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power consumption. Pipelined architecture and output error correction ensure the ADC1112D125 is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in Complementary Metal Oxide Semiconductor (CMOS) mode, because of a separate digital output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a programmable full-scale SPI to allow a flexible input voltage range of 1 V (p-p) to 2 V (p-p). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1112D125 is ideal for use in communications, imaging and medical applications. 2. Features and benefits SNR, 66.2 dBFS SFDR, 87 dBc Sample rate up to 125 Msps Clock input divided by 2 to reduce jitter contribution Single 3 V supply Flexible input voltage range: 1 V (p-p) to 2 V (p-p) CMOS or LVDS DDR digital outputs Power-down and Sleep modes Input bandwidth, 600 MHz Power dissipation, 1230 mW Serial Peripheral Interface (SPI) Duty cycle stabilizer Fast OuT-of-Range (OTR) detection Pin and software compatible with ADC1412D series and ADC1212D series. Offset binary, two’s complement, gray code HVQFN64 package 3. Applications Wireless and wired broadband communications Spectral analysis Ultrasound equipment Portable instrumentation Imaging systems Software defined radio NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 4. Ordering information Table 1. Ordering information fs (Msps) Package Name ADC1112D125HN/C1 125 Description Version SOT804-3 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 × 9 × 0.85 mm Type number 5. Block diagram SDIO/ODS SCLK/DFS CS ADC1112D125 ERROR CORRECTION AND DIGITAL PROCESSING SPI INTERFACE OTRA INAP T/H INPUT STAGE INAM ADC A CORE 11-BIT PIPELINED OUTPUT DRIVERS CMOS: DA10 to DA0 or LVDS/DDR: DA9_DA10_P to LOW_DA0_P DA9_DA10_M to LOW_DA0_M CMOS: DAV or LVDS/DDR: DAVP DAVM CMOS: DB10 to DB0 or LVDS/DDR: DB9_DB10_P to LOW_DB0_P DB9_DB10_M to LOW_DB0_M OTRB CLKP CLKM CLOCK INPUT STAGE AND DUTY CYCLE CONTROL OUTPUT DRIVERS INBP T/H INPUT STAGE INBM ADC B CORE 11-BIT PIPELINED OUTPUT DRIVERS ERROR CORRECTION AND DIGITAL PROCESSING SYSTEM REFERENCE AND POWER MANAGEMENT CTRL REFBT REFBB VCMB VCMA SENSE VREF REFAB REFAT 005aaa161 Fig 1. Block diagram ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 2 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 6. Pinning information 6.1 CMOS outputs selected 6.1.1 Pinning 62 SENSE 50 VDDO terminal 1 index area INAP INAM AGND VCMA REFAT REFAB AGND CLKP CLKM 1 2 3 4 5 6 7 8 9 49 VDDO 48 DA2 47 DA1 46 DA0 45 n.c. 44 n.c. 43 n.c. 42 DAV 41 n.c. 40 n.c. 39 n.c. 38 n.c. 37 DB0 36 DB1 35 DB2 34 DB3 33 DB4 VDDO 32 005aaa162 64 VDDA 61 VDDA 60 DECA 59 OTRA 63 VREF 58 DA10 57 DA9 56 DA8 55 DA7 54 DA6 53 DA5 DB7 28 52 DA4 DB6 29 ADC1112D125 HVQFN64 AGND 10 REFBB 11 REFBT 12 VCMB 13 AGND 14 INBM 15 INBP 16 VDDA 17 VDDA 18 SCLK/DFS 19 SDIO/ODS 20 CS 21 CTRL 22 DECB 23 OTRB 24 DB10 25 DB9 26 DB8 27 DB5 30 VDDO 31 Transparent top view Fig 2. Pin configuration with CMOS digital outputs selected 6.1.2 Pin description Table 2. Symbol INAP INAM AGND VCMA REFAT REFAB AGND CLKP CLKM AGND REFBB REFBT ADC1112D125 Pin description (CMOS digital outputs) Pin 1 2 3 4 5 6 7 8 9 10 11 12 Type [1] I I G O O O G I I G O O Description analog input; channel A complementary analog input; channel A analog ground common-mode output voltage; channel A top reference; channel A bottom reference; channel A analog ground clock input complementary clock input analog ground bottom reference; channel B top reference; channel B © NXP B.V. 2011. All rights reserved. All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 3 March 2011 51 DA3 3 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Pin description (CMOS digital outputs) …continued Pin 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Type [1] O G I I P P I I/O I I O O O O O O O O P P O O O O O O O O O O O O O O O P P O O O O O O Description common-mode output voltage; channel B analog ground complementary analog input; channel B analog input; channel B analog power supply analog power supply SPI clock/data format select SPI data input/output/output data standard SPI chip select, active LOW control mode select regulator decoupling node; channel B out-of-range; channel B data output bit 10 (Most Significant Bit (MSB)); channel B data output bit 9; channel B data output bit 8; channel B data output bit 7; channel B data output bit 6; channel B data output bit 5; channel B output power supply output power supply data output bit 4; channel B data output bit 3; channel B data output bit 2; channel B data output bit 1; channel B data output bit 0 (Least Significant Bit (LSB)); channel B not connected not connected not connected not connected data valid output clock not connected not connected not connected data output bit 0 (LSB); channel A data output bit 1; channel A data output bit 2; channel A output power supply output power supply data output bit 3; channel A data output bit 4; channel A data output bit 5; channel A data output bit 6; channel A data output bit 7; channel A data output bit 8; channel A © NXP B.V. 2011. All rights reserved. Table 2. Symbol VCMB AGND INBM INBP VDDA VDDA SCLK/DFS SDIO/ODS CS CTRL DECB OTRB DB10 DB9 DB8 DB7 DB6 DB5 VDDO VDDO DB4 DB3 DB2 DB1 DB0 n.c. n.c. n.c. n.c. DAV n.c. n.c. n.c. DA0 DA1 DA2 VDDO VDDO DA3 DA4 DA5 DA6 DA7 DA8 ADC1112D125 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 3 March 2011 4 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Pin description (CMOS digital outputs) …continued Pin 57 58 59 60 61 62 63 64 Type [1] O O O O P I I/O P Description data output bit 9; channel A data output bit 10 (MSB); channel A out-of-range; channel A regulator decoupling node; channel A analog power supply reference programming pin voltage reference input/output analog power supply Table 2. Symbol DA9 DA10 OTRA DECA VDDA SENSE VREF VDDA [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. 6.2 LVDS DDR outputs selected 6.2.1 Pinning 58 DA9_DA10_M 57 DA9_DA10_P 56 DA7_DA8_M 54 DA5_DA6_M 52 DA3_DA4_M 55 DA7_DA8_P 53 DA5_DA6_P 51 DA3_DA4_P 62 SENSE 50 VDDO terminal 1 index area INAP INAM AGND VCMA REFAT REFAB AGND CLKP CLKM 1 2 3 4 5 6 7 8 9 49 VDDO 48 DA1_DA2_M 47 DA1_DA2_P 46 LOW_DA0_M 45 LOW_DA0_P 44 n.c. 43 n.c. 42 DAVP 41 DAVM 40 n.c. 39 n.c. 38 LOW_DB0_P 37 LOW_DB0_M 36 DB1_DB2_P 35 DB1_DB2_M 34 DB3_DB4_P 33 DB3_DB4_M VDDO 32 005aaa163 64 VDDA 61 VDDA 60 DECA CS 21 AGND 10 REFBB 11 REFBT 12 VCMB 13 AGND 14 INBM 15 INBP 16 VDDA 17 VDDA 18 SCLK/DFS 19 SDIO/ODS 20 CTRL 22 DECB 23 OTRB 24 DB9_DB10_M 25 DB9_DB10_P 26 DB7_DB8_M 27 DB7_DB8_P 28 DB5_DB6_M 29 DB5_DB6_P 30 VDDO 31 Fig 3. Pin configuration with LVDS DDR digital outputs selected ADC1112D125 All information provided in this document is subject to legal disclaimers. 59 OTRA 63 VREF ADC1112D125 HVQFN64 Transparent top view © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 5 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 6.2.2 Pin description Table 3. Symbol DB9_DB10_M DB9_DB10_P DB7_DB8_M DB7_DB8_P DB5_DB6_M DB5_DB6_P DB3_DB4_M DB3_DB4_P DB1_DB2_M DB1_DB2_P LOW_DB0_M LOW_DB0_P n.c. n.c. DAVM DAVP n.c. n.c. LOW_DA0_P LOW_DA0_M DA1_DA2_P DA1_DA2_M DA3_DA4_P DA3_DA4_M DA5_DA6_P DA5_DA6_M DA7_DA8_P DA7_DA8_M DA9_DA10_P DA9_DA10_M [1] [2] Pin description (LVDS DDR) digital outputs) [1] Pin 25 26 27 28 29 30 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 51 52 53 54 55 56 57 58 Type [2] O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Description differential output data DB9 and DB10 multiplexed, complement differential output data DB9 and DB10 multiplexed, true differential output data DB7and DB8 multiplexed, complement differential output data DB7 and DB8 multiplexed, true differential output data DB5 and DB6 multiplexed, complement differential output data DB5 and DB6 multiplexed, true differential output data DB3 and DB4 multiplexed, complement differential output data DB3 and DB4 multiplexed, true differential output data DB1 and DB2 multiplexed, complement differential output data DB1 and DB2 multiplexed, true differential output data DB0 multiplexed, complement differential output data DB0 multiplexed, true not connected not connected data valid output clock, complement data valid output clock, true not connected not connected differential output data DA0 multiplexed, true differential output data DA0 multiplexed, complement differential output data DA1 and DA2 multiplexed, true differential output data DA1 and DA2 multiplexed, complement differential output data DA3 and DA4 multiplexed, true differential output data DA3 and DA4 multiplexed, complement differential output data DA5 and DA6 multiplexed, true differential output data DA5 and DA6 multiplexed, complement differential output data DA7 and DA8 multiplexed, true differential output data DA7 and DA8 multiplexed, complement differential output data DA9 and DA10 multiplexed, true differential output data DA9 and DA10 multiplexed, complement Pins 1 to 24, pin 59 to 64 and pins 31, 32, 49 and 50 are the same for both CMOS and LVDS DDR outputs (see Table 2). P: power supply; G: ground; I: input; O: output; I/O: input/output. ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 6 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VO output voltage Conditions pins DA10 to DA0 and DB10 to DB0 or pins DA9_DA10_P to LOW_DA0_P, DA9_DA10_M to LOW_DA0_M, DB9_DB10_P to LOW_DB0_P and DB9_DB10_M to LOW_DB0_M Min −0.4 Max +3.9 Unit V VDDA VDDO Tstg Tamb Tj analog supply voltage output supply voltage storage temperature ambient temperature junction temperature −0.4 −0.4 −55 −40 - +3.9 +3.9 +125 +85 125 V V °C °C °C 8. Thermal characteristics Table 5. Symbol Rth(j-a) Rth(j-c) [1] Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions [1] [1] Typ 15.6 6.3 Unit K/W K/W Value for six layers board in still air with a minimum of 64 thermal vias. 9. Static characteristics Table 6. Symbol Supplies VDDA VDDO IDDA IDDO analog supply voltage output supply voltage analog supply current output supply current CMOS mode LVDS DDR mode fclk = 125 Msps; fi = 70 MHz CMOS mode; fclk = 125 Msps; fi = 70 MHz LVDS DDR mode: fclk = 125 Msps; fi = 70 MHz P power dissipation ADC1112D125; analog supply only Power-down mode Sleep mode 2.85 1.65 2.85 3.0 1.8 3.0 400 16 82 1230 24 80 3.4 3.6 3.6 V V V mA mA mA mW mW mW Static characteristics[1] Parameter Conditions Min Typ Max Unit ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 7 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Table 6. Symbol Static characteristics[1] …continued Parameter Conditions Min Typ Max Unit Clock inputs: pins CLKP and CLKM Low-Voltage Positive Emitter-Coupled Logic (LVPECL) Vi(clk)dif Sine Vi(clk)dif VIL VIH VIL differential clock input voltage LOW-level input voltage HIGH-level input voltage LOW-level input voltage LOW-medium level medium-HIGH level VIH IIL IIH VIL VIH IIL IIH CI HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance peak-to-peak ±0.8 0.7VDDA −10 −10 0 0.7VDDA −10 −50 ±3.0 0 0.3VDDA 0.6VDDA VDDA 4 V Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) 0.3VDDA V +10 +10 V V V V V μA μA differential clock input voltage peak-to-peak ±1.6 V Logic input: pin CTRL Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS 0.3VDDA V VDDA +10 +50 V μA μA pF Digital outputs, CMOS mode: pins DA10 to DA0, DB10 to DB0, OTRA, OTRB and DAV Output levels, VDDO = 3 V VOL VOH CO VOL VOH LOW-level output voltage HIGH-level output voltage output capacitance LOW-level output voltage HIGH-level output voltage high impedance; see Table 10 AGND 0.8VDDO AGND 0.8VDDO 3 0.2VDDO V VDDO V pF Output levels, VDDO = 1.8 V 0.2VDDO V VDDO V Digital outputs, LVDS DDR mode: pins DA9_DA10_P to LOW_DA0_P, DA9_DA10_M to LOW_DA0_M, DB9_DB10_P to LOW_DB0_P, DB9_DB10_M to LOW_DB0_M, DAVP and DAVM Output levels, VDDO = 3 V only, RL = 100 Ω VO(offset) VO(dif) CO II RI CI VI(cm) ADC1112D125 output offset voltage differential output voltage output capacitance input current input resistance input capacitance common-mode input voltage output buffer current set to 3.5 mA output buffer current set to 3.5 mA −5 - 1.2 350 3 19.8 2.8 1.5 +5 2 V mV pF μA kΩ pF V 8 of 41 Analog inputs: pins INAP, INAM, INBP and INBM VINAP = VINAM; VINBP = VINBM Rev. 2 — 3 March 2011 0.9 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Table 6. Symbol Bi VI(dif) VO(cm) IO(cm) VVREF Accuracy INL DNL Eoffset EG MG(CTC) Supply PSRR [1] Static characteristics[1] …continued Parameter input bandwidth differential input voltage common-mode output voltage common-mode output current voltage on pin VREF output input integral non-linearity differential non-linearity offset error gain error channel-to-channel gain matching power supply rejection ratio 200 mV (p-p) on VDDA; fi = DC full-scale guaranteed no missing codes peak-to-peak Conditions Min 1 0.5 −0.6 −0.2 Typ 600 0.5VDDA 4 0.5 to 1 ±0.12 ±0.06 ±2 ±0.5 1.1 Max 2 1 +0.6 +0.2 Unit MHz V V mA V V LSB LSB mV % % Common-mode output voltage: pins VCMA and VCMB I/O reference voltage: pin VREF - −37 - dB Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 9 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7. Symbol α2H Dynamic characteristics[1] Parameter second harmonic level Conditions fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz α3H third harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz THD total harmonic distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz ENOB effective number of bits fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SNR signal-to-noise ratio fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SFDR spurious-free dynamic range fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz IMD Intermodulation distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz αct(ch) [1] Min - Typ 88 87 85 83 87 86 84 82 84 83 81 79 10.7 10.7 10.7 10.6 66.2 66.2 66.0 65.8 87 86 84 82 89 88 86 84 100 Max - Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc dBc Analog signal processing channel crosstalk fi = 70 MHz Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 10 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 10.2 Clock and digital output timing Table 8. Symbol fclk tlat(data) δclk td(s) twake tPD tsu th tr tf Clock and digital output timing characteristics[1] Parameter clock frequency data latency time clock duty cycle sampling delay time wake-up time propagation delay set-up time hold time rise time fall time DATA DAV DATA [2] [2] Conditions Min 100 - Typ 14 50 50 0.8 76 3.9 4.2 5.7 1.4 - Max 125 70 55 2.4 2.4 2.4 Unit MHz clock cycles % % ns μs ns ns ns ns ns ns ns Clock timing input: pins CLKP and CLKM DCS_EN = 1 DCS_EN = 0 30 45 - CMOS mode timing: pins DA10 to DA0, DB10 to DB0 and DAV DATA DAV 0.5 0.5 0.5 LVDS DDR mode timing: pins DA9_DA10_P to LOW_DA0_P, DA9_DA10 M to LOW_DA0_M, DB9_DB10_P to LOW_DB0_P, DB9_DB10_M to LOW_DB0_M, DAVP and DAVM tPD tsu th tr tf propagation delay set-up time hold time rise time fall time DATA DAV DATA DAV [1] [3] [3] DATA DAV 50 50 50 50 3.9 4.2 1.4 2.0 100 100 100 100 200 200 200 200 ns ns ns ns ps ps ps ps Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V; VINAP − VINAM = −1 dBFS; VINBP − VINBM = −1 dBFS; unless otherwise specified. Measured between 20 % to 80 % of VDDO. Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV. [2] [3] ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 11 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs N N+1 td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tPD tsu DAV th tclk 005aaa060 tclk = 1 / fclk Fig 4. CMOS mode timing N N+1 td(s) N+2 tclk CLKP CLKM tPD DAx_DAx + 1_P/ DBx_DBx + 1_P DAx_DAx + 1_M/ DBx_DBx + 1_M (N − 14) (N − 13) (N − 12) (N − 11) DAx/ DBx DAx+1/ DBx+1 DAx/ DBx tsu th DAx+1/ DBx+1 tsu th DAx/ DBx DAx+1/ DBx+1 DAx/ DBx DAx+1/ DBx+1 DAx/ DBx DAx+1/ DBx+1 tPD DAVP DAVM tclk 005aaa114 tclk = 1 / fclk Fig 5. LVDS DDR mode timing ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 12 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 10.3 SPI timings Table 9. Symbol tw(SCLK) tw(SCLKH) tw(SCLKL) tsu th fclk(max) [1] Characteristics Parameter SCLK pulse width SCLK HIGH pulse width SCLK LOW pulse width set-up time hold time maximum clock frequency data to SCLK HIGH CS to SCLK HIGH data to SCLK HIGH CS to SCLK HIGH Conditions Min Typ 40 16 16 5 5 2 2 25 Max Unit ns ns ns ns ns ns ns MHz SPI timings Typical values measured at VDDA = 3 V, VDDO = 1.8 V, Tamb = 25 °C; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V. tsu CS tsu th tw(SCLKL) tw(SCLK) tw(SCLKH) th SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 6. SPI timing ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 13 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 10.4 Typical characteristics 3.2 C (pF) 3.0 001aam619 16 R (kΩ) 12 001aam614 2.8 8 2.6 4 2.4 50 150 250 350 450 550 f (MHz) 0 50 150 250 350 450 550 f (MHz) Fig 7. Capacitance as a function of frequency Fig 8. Resistance as a function of frequency 100 SFDR (dBc) 80 001aam616 80 SNR (dBFS) 60 (1) 001aam615 (1) 60 (2) (2) 40 40 20 20 0 10 30 50 70 δ (%) 90 0 10 30 50 70 δ (%) 90 T = 25 °C; VDD = 3 V; fi = 170 MHz; fs = 125 Msps (1) DCS on (2) DCS off T = 25 °C; VDD = 3 V; fi = 170 MHz; fs = 125 Msps (1) DCS on (2) DCS off Fig 9. SFDR as a function of duty cycle (δ) Fig 10. SNR as a function of duty cycle (δ) ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 14 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 92 SFDR (dBc) 88 001aam617 80 SNR (dBFS) 60 001aam618 (1) (2) (1) (2) (3) (3) 84 40 80 10 30 50 70 δ (%) 90 20 10 30 50 70 δ (%) 90 (1) Tamb = −40 °C/typical supply voltages (2) Tamb = +25 °C/typical supply voltages (3) Tamb = +90 °C/typical supply voltages (1) Tamb = −40 °C/typical supply voltages (2) Tamb = +25 °C/typical supply voltages (3) Tamb = +90 °C/typical supply voltages Fig 11. SFDR as a function of duty cycle (δ) Fig 12. SNR as a function of duty cycle (δ) 90 SFDR (dBc) 86 001aam659 75 SNR (dBFS) 73 001aam660 82 71 78 69 74 67 70 0 0.5 1.0 1.5 2.0 2.5 3.0 VI(cm) (V) 3.5 65 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VI(cm) (V) Fig 13. SFDR as a function of common-mode input voltage (VI(cm)) Fig 14. SNR as a function of common-mode input voltage (VI(cm)) ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 15 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 11. Application information 11.1 Device control The ADC1112D125 can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been enabled, the device remains in this mode. The transition from Pin control mode to SPI control mode is illustrated in Figure 15. CS Pin control mode Data format offset binary SPI control mode SCLK/DFS Data format two's complement LVDS DDR SDIO/ODS CMOS R/W W1 W0 A12 005aaa039 Fig 15. Control mode selection When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO as soon as a transition is triggered by a falling edge on CS. 11.1.2 Operating mode selection The active ADC1112D125 operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 21) or by using pin CTRL in Pin control mode. Table 10. Pin CTRL 0 0.3VDDA 0.6VDDA VDDA Operating mode selection via pin CTRL Operating mode Power-down Sleep Power-up Power-up Output high-Z yes yes yes no 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 24) or by using pin ODS in Pin control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected. ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 16 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 24) or by using pin DFS in Pin control mode (offset binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1112D125 supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INAP, INAM, INBP and INBM set to 0.5VDDA. The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 23). The equivalent circuit of the sample-and-hold input stage, including ElectroStatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 16. Package ESD Parasitics Switch Ron = 14 Ω 4 pF INAP/INBP internal clock Sampling capacitor Ron = 14 Ω Switch 4 pF INAM/INBM internal clock Sampling capacitor 005aaa092 Fig 16. Input sampling circuit The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. 11.2.2 Anti-kickback circuitry Anti-kickback circuitry (RC filter in Figure 17 is needed to counteract the effects of charge injection generated by the sampling capacitance. The RC-filter is also used to filter noise from the signal before it reaches the sampling stage. The value of the capacitor should be chosen to maximize noise attenuation without degrading the settling time excessively. ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 17 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs R INAP/ INBP C R INAM/ INBM 001aan679 Fig 17. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. RC coupling versus input frequency, typical values R (Ω) 25 12 12 C (pF) 12 8 8 3 70 170 Input frequency (MHz) 11.2.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 18 would be suitable for a baseband application. ADT1-1WT 100 nF Analog input 100 nF 25 Ω 25 Ω INAP/INBP 12 pF 100 nF 25 Ω 25 Ω 100 nF INAM/INBM VCMA/VCMB 100 nF 100 nF 005aaa094 Fig 18. Single transformer configuration suitable for baseband applications The configuration shown in Figure 19 is recommended for high frequency applications. In both cases, the choice of transformer is a compromise between cost and performance. ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 18 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs ADT1-1WT 100 nF 50 Ω ADT1-1WT 50 Ω 12 Ω INAP/INBP Analog input 8.2 pF 50 Ω 50 Ω 12 Ω INAM/INBM VCMA/VCMB 100 nF 100 nF 100 nF 005aaa095 Fig 19. Dual transformer configuration suitable for high intermediate frequency application 11.3 System reference and power management 11.3.1 Internal/external references The ADC1112D125 has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and −6 dB via control bits INTREF[2:0] when bit INTREF_EN = logic 1; see Table 23). See Figure 21 to Figure 24. The equivalent reference circuit is shown in Figure 20. An external reference is also possible by providing a voltage on pin VREF as described in Figure 23. ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 19 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs REFAT/ REFBT REFERENCE AMP REFAB/ REFBB VREF EXT_ref BUFFER EXT_ref BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 001aan670 Fig 20. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 12. Table 12. Selection Internal (Figure 21) Internal (Figure 22) External (Figure 23) Internal via SPI (Figure 24) [1] Reference selection SPI bit INTREF_EN 0 0 0 1 SENSE pin AGND VREF pin 330 pF capacitor to AGND Full-scale (V (p-p)) 2V 1V 1 V to 2 V 1 V to 2 V pin VREF connected to pin SENSE and via a 330 pF capacitor to AGND VDDA external voltage between 0.5 V and 1 V[1] pin VREF connected to pin SENSE and via 330 pF capacitor to AGND The voltage on pin VREF is doubled internally to generate the internal reference voltage. Figure 21 to Figure 24 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 20 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs VREF 330 pF VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa116 005aaa117 Fig 21. Internal reference, 2 V (p-p) full-scale Fig 22. Internal reference, 1 V (p-p) full-scale VREF 0.1 μF VREF V 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE REFERENCE EQUIVALENT SCHEMATIC SENSE VDDA 005aaa119 005aaa118 Fig 23. External reference, 1 V (p-p) to 2 V (p-p) full-scale Fig 24. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale 11.3.2 Programmable full-scale The full-scale is programmable between 1 V (p-p) to 2 V (p-p) (see Table 13). Table 13. INTREF 000 001 010 011 100 101 110 111 Programmable full-scale Level (dB) 0 −1 −2 −3 −4 −5 −6 reserved Full-scale (V (p-p)) 2 1.78 1.59 1.42 1.26 1.12 1 x 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 μF filter capacitor should be connected between pin VCMA/VCMB and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCMA/VCMB can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 21 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Package ESD Parasitics COMMON MODE REFERENCE VCMA/VCMB 1.5 V 0.1 μF ADC CORE 005aaa099 Fig 25. Equivalent schematic of the common-mode reference circuit 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INAP/INBP and INAM/INBM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V (see Table 6). 11.4 Clock input 11.4.1 Drive modes The ADC1112D125 can be driven differentially (LVPECL). It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin CLKM (pin CLKP should be connected to ground via a capacitor). LVCMOS clock input CLKP CLKP CLKM LVCMOS clock input CLKM 005aaa174 005aaa053 a. Rising edge LVCMOS Fig 26. LVCMOS single-ended clock input b. Falling edge LVCMOS ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 22 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs CLKP Sine clock input Sine clock input CLKP CLKM CLKM 005aaa173 005aaa054 a. Sine clock input b. Sine clock input (with transformer) CLKP LVPECL clock input CLKM 005aaa172 c. LVPECL clock input Fig 27. Differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 28. The common-mode voltage of the differential input stage is set via internal 5 kΩ resistors. Package ESD Parasitics CLKP Vcm(clk) SE_SEL SE_SEL 5 kΩ 5 kΩ CLKM 005aaa056 Vcm(clk) = common-mode voltage of the differential input stage. Fig 28. Equivalent input circuit ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 23 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Single-ended or differential clock inputs can be selected via the SPI interface (see Table 22). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performance of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = logic 1; see Table 22), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and 55 %. 11.4.4 Clock input divider The ADC1112D125 contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = logic 1; see Table 22). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to logic 0 (see Table 24). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 29. The buffer is powered by a separate AGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. VDDO Parasitics ESD Package LOGIC DRIVER 50 Ω Dx AGND 005aaa057 Fig 29. CMOS digital output buffer ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 24 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs The output resistance is 50 Ω and is the combination of an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both DATA and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 31). 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to logic 1 (see Table 24). VDDO 3.5 mA typical + DAn_DAn + 1_P; DBn_DBn + 1_P 100 Ω RECEIVER DAn_DAn + 1_M; DBn_DBn + 1_M + AGND 005aaa112 Fig 30. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver side (Figure 30) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 31 and Table 33). VDDO 3.5 mA typical + DAn_DAn + 1_P; DBn_DBn + 1_P 100 Ω 100 Ω RECEIVER DAn_DAn + 1_M; DBn_DBn + 1_M + AGND 005aaa113 Fig 31. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 32) in order to adjust the output logic voltage levels. ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 25 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs LVDS DDR output register 2 Resistor value (Ω) no internal termination 300 180 110 150 100 81 60 Table 14. 000 001 010 011 100 101 110 111 LVDS_INT_TER[2:0] 11.5.3 DAta Valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1112D125. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 4 and Figure 5 respectively. In LVDS DDR mode, it is highly recommended to shift ahead the DAV by 1 ns (bits DAVPHASE[2:0] = 0b100; see Table 25). 11.5.4 OuT-of-Range (OTR) An out-of-range signal is provided on pin OTRA for ADC channel A and on pin OTRB for ADC channel B. The latency of OTRA/OTRB is fourteen clock cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = logic 1; see Table 30). In this mode, the latency of OTRA/OTRB is reduced to only four clock cycles (per ADC channel). The Fast OTR detection threshold (below full-scale) can be programmed via bits FASTOTR_DET[2:0]. Table 15. 000 001 010 011 100 101 110 111 Fast OTR register Detection level (dB) −20.56 −16.12 −11.02 −7.82 −5.49 −3.66 −2.14 −0.86 FASTOTR_DET[2:0] 11.5.5 Digital offset By default, the ADC1112D125 delivers output code that corresponds to the analog input. However, it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET[5:0]; see Table 26). ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 26 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 11.5.6 Test patterns For test purposes, the ADC1112D125 can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 27). A custom test pattern can be defined by the user (TESTPAT_USER[10:3]; see Table 28 and TESTPAT_USER[2:0]; see Table 29) and is selected when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted regardless of the analog input. 11.5.7 Output codes versus input voltage Table 16. < −1 −1.0000000 −0.9990234 −0.9980469 −0.9970703 −0.996093 .... −0.0019531 −0.0009766 0.0000000 +0.0009766 +0.0019531 .... +0.9960938 +0.9970703 +0.9980469 +0.9990234 +1.0000000 > +1 Output codes Offset binary 000 0000 0000 000 0000 0000 000 0000 0001 000 0000 0010 000 0000 0011 000 0000 0100 .... 011 1111 1110 011 1111 1111 100 0000 0000 100 0000 0001 100 0000 0010 .... 111 1111 1011 111 1111 1100 111 1111 1101 111 1111 1110 111 1111 1111 111 1111 1111 Two’s complement 100 0000 0000 100 0000 0000 100 0000 0001 100 0000 0010 100 0000 0011 100 0000 0100 .... 111 1111 1110 111 1111 1111 000 0000 0000 000 0000 0001 000 0000 0010 .... 011 1111 1011 011 1111 1100 011 1111 1101 011 1111 1110 011 1111 1111 011 1111 1111 OTRA/OTRB pin 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VINAP − VINAM/VINBP − VINBM 11.6 Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1112D125 serial interface is a synchronous serial communications port that allows easy interfacing with many commonly used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and pin CS acts as the serial chip select. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 18). ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 27 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Instruction bytes for the SPI MSB LSB 6 W1[2] A6 5 W0[2] A5 4 A12 A4 3 A11 A3 2 A10 A2 1 A9 A1 0 A8 A0 7 R/W[1] A7 Table 17. Bit Description [1] [2] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation. Bits W1 and W0 indicate the number of bytes to be transferred (see Table 18). Table 18. W1 0 0 1 1 Number of data bytes to be transferred after the instruction bytes W0 0 1 0 1 Number of bytes transferred 1 byte 2 bytes 3 bytes 4 bytes or more Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows: 1. A falling edge on pin CS in combination with a rising edge on pin SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on pin CS indicates the end of data transmission. CS SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction bytes Register N (data) Register N + 1 (data) 005aaa086 Fig 32. SPI mode timing 11.6.2 Default modes at start-up During circuit initialization it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on pin CS triggers a transition to SPI control mode. When the ADC1112D125 enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 33). Once in SPI control mode, the output data standard can be changed via bit LVDS_CMOS (see Table 24). ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 28 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs When the ADC1112D125 enters SPI control mode, the output data format (two’s complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] (see Table 24). CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data format) SDIO (CMOS LVDS DDR) two's complement, CMOS default mode at start-up 005aaa064 Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 29 of 41 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 11.6.3 Register allocation map Table 19. Register allocation map Access Bit 7 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TESTPAT_USER[2:0] RESERVED DAVI[1:0] BIT_BYTE_WISE SW_ RST Bit 6 Bit 5 Bit 4 RESERVED[5:0] RESERVED[2:0] SE_SEL LVDS_ CMOS DIFF_SE INTREF_EN OUTBUF DAVINV DIG_OFFSET[5:0] TESTPAT_USER[10:3] FASTOTR DAV_DRV[1:0] RESERVED FASTOTR_DET[2:0] DATA_DRV[1:0] DATAI[1:0] LVDS_INT_TER[2:0] TESTPAT_SEL[2:0] RESERVED OUTBUS_SWAP Bit definition Bit 3 Bit 2 Bit 1 ADCB Bit 0 ADCA Default (bin) 1111 1111 0000 0000 Address Register name (hex) 0003 0005 0006 0008 0011 0012 0013 0014 0015 0016 0017 0020 0021 0022 Channel index Reset and operating mode Clock Output data standard. Output clock Offset Test pattern 1 Test pattern 2 Test pattern 3 Fast OTR CMOS output Product data sheet Rev. 2 — 3 March 2011 30 of 41 ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. NXP Semiconductors OP_MODE[1:0] CLKDIV INTREF[2:0] DATA_FORMAT[1:0] DCS_EN 0000 0001 0000 0000 0000 0000 0000 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Internal reference R/W DAVPHASE[2:0] Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 0000 1110 0000 0000 0000 0000 LVDS DDR O/P 1 R/W LVDS DDR O/P 2 R/W ADC1112D125 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Table 20. Channel index control register (address 0003h) bit description Default values are highlighted. Bit 7 to 2 1 Symbol RESERVED[5:0] ADCB Access R/W 0 1 0 ADCA R/W 0 1 Value 111111 Description reserved next SPI command for ADC B ADC B not selected ADC B selected next SPI command for ADC A ADC A not selected ADC A selected Table 21. Reset and operating mode control register (address 0005h) bit description Default values are highlighted. Bit 7 Symbol SW_RST Access R/W 0 1 6 to 4 3 to 2 1 to 0 RESERVED[2:0] OP_MODE[1:0] R/W 00 01 10 11 Table 22. Clock control register (address 0006h) bit description Default values are highlighted. Bit 7 to 5 4 Symbol SE_SEL Access R/W 0 1 3 DIFF_SE R/W 0 1 2 1 RESERVED CLKDIV R/W 0 1 0 DCS_EN R/W 0 1 0 Value 000 Description not used single-ended clock input pin select CLKM CLKP differential/single-ended clock input select fully differential single-ended reserved clock input divide by 2 disabled enabled duty cycle stabilizer disabled enabled 000 00 Value Description reset digital section no reset performs a reset on SPI registers reserved not used operating mode normal (Power-up) Power-down Sleep normal (Power-up) ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 31 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Table 23. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol INTREF_EN Access R/W 0 1 2 to 0 INTREF[2:0] R/W 000 001 010 011 100 101 110 111 Value 0000 Description not used programmable internal reference enable disabled active programmable internal reference 0 dB (FS = 2 V) −1 dB (FS = 1.78 V) −2 dB (FS = 1.59 V) −3 dB (FS = 1.42 V) −4 dB (FS = 1.26 V) −5 dB (FS = 1.12 V) −6 dB (FS = 1 V) reserved Table 24. Output data standard control register (address 0011h) bit description Default values are highlighted. Bit 7 to 5 4 Symbol LVDS_CMOS Access R/W 0 1 3 OUTBUF R/W 0 1 2 OUTBUS_SWAP R/W 0 1 1 to 0 DATA_FORMAT[1:0] R/W 00 01 10 11 Value 000 Description not used output data standard: LVDS DDR or CMOS CMOS LVDS DDR output buffers enable output enabled output disabled (high-Z) output bus swap no swapping output bus is swapped (MSB becomes LSB and vice versa) output data format offset binary two’s complement gray code offset binary ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 32 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Table 25. Output clock register (address 0012h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol DAVINV Access R/W 0 1 2 to 0 DAVPHASE[2:0] R/W 000 001 010 011 100 101 110 111 [1] tclk = 1 / fclk Value 0000 Description not used output clock data valid (DAV) polarity normal inverted DAV phase select output clock shifted (ahead) by 6/16 × tclk[1] output clock shifted (ahead) by 5/16 × tclk[1] output clock shifted (ahead) by 4/16 × tclk[1] output clock shifted (ahead) by 3/16 × tclk[1] output clock shifted (ahead) by 2/16 × tclk[1] output clock shifted (ahead) by 1/16 × tclk[1] default value as defined in timing section output clock shifted (delayed) by 1/16 × tclk[1] Table 26. Offset register (address 0013h) bit description Default values are highlighted. Bit 7 to 6 5 to 0 Symbol DIG_OFFSET[5:0] Access R/W 011111 ... 000000 ... 100000 Table 27. Test pattern 1 register (address 0014h) bit description Default values are highlighted. Bit 7 to 3 2 to 0 Symbol TESTPAT_SEL[2:0] Access R/W 000 001 010 011 100 101 110 111 Value 00000 Description not used digital test pattern select off mid scale −FS +FS toggle ‘1111..1111’/’0000..0000’ custom test pattern ‘0101..0101’ ‘1010..1010.’ Value 00 Description not used digital offset adjustment +31 LSB ... 0 ... −32 LSB ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 33 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Table 28. Test pattern 2 register (address 0015h) bit description Default values are highlighted. Bit 7 to 0 Symbol TESTPAT_USER[10:3] Access R/W Value 0000 0000 Description custom digital test pattern (bits 10 to 3) Table 29. Test pattern 3 register (address 0016h) bit description Default values are highlighted. Bit 7 to 5 4 to 0 Symbol TESTPAT_USER[2:0] Access R/W Value 000 00000 Description custom digital test pattern (bits 2 to 0) not used Table 30. Fast OTR register (address 0017h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol FASTOTR Access R/W 0 1 2 to 0 FASTOTR_DET[2:0] R/W 000 001 010 011 100 101 110 111 Table 31. CMOS output register (address 0020h) bit description Default values are highlighted. Bit 7 to 4 3 to 2 Symbol DAV_DRV[1:] Access R/W 00 01 10 11 1 to 0 DATA_DRV[1:0] R/W 00 01 10 11 Value 00 Description not used drive strength for DAV CMOS output buffer low medium high very high drive strength for DATA CMOS output buffer low medium high very high Value 0000 Description not used fast OuT-of-Range (OTR) detection disabled enabled set fast OTR detect level −20.56 dB −16.12 dB −11.02 dB −7.82 dB −5.49 dB −3.66 dB −2.14 dB −0.86 dB ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 34 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs Table 32. LVDS DDR output register 1 (address 0021h) bit description Default values are highlighted. Bit 7 to 6 5 4 to 3 Symbol RESERVED DAVI[1:0] Access R/W 00 01 10 11 2 1 to 0 RESERVED DATAI[1:0] R/W 00 01 10 11 0 Value 00 0 Description not used reserved LVDS current for DAV LVDS buffer 3.5 mA 4.5 mA 1.25 mA 2.5 mA reserved LVDS current for DATA LVDS buffer 3.5 mA 4.5 mA 1.25 mA 2.5 mA Table 33. LVDS DDR output register 2 (address 0022h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol BIT_BYTE_WISE Access R/W 0 Value 0000 Description not used DDR mode for LVDS output bit wise (even data bits output on DAV rising edge/odd data bits output on DAV falling edge) byte wise (MSB data bits output on DAV rising edge/LSB data bits output on DAV falling edge) internal termination for LVDS buffer (DAV and DATA) 000 001 010 011 100 101 110 111 no internal termination 300 Ω 180 Ω 110 Ω 150 Ω 100 Ω 81 Ω 60 Ω 1 2 to 0 LVDS_INT_TER[2:0] R/W ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 35 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 12. Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm SOT804-3 D B A terminal 1 index area E A A1 c detail X e1 1/2 e L 17 16 e b 32 33 v w CAB C y1 C C y e Eh 1/2 e e2 1 terminal 1 index area 64 Dh 49 48 X 0 Dimensions Unit mm A A1 b c 0.2 D(1) 9.1 9.0 8.9 Dh 7.25 7.10 6.95 E(1) 9.1 9.0 8.9 Eh 7.25 7.10 6.95 e 0.5 2.5 scale e1 7.5 e2 7.5 5 mm L 0.5 0.4 0.3 v 0.1 w y y1 0.1 max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT804-3 References IEC --JEDEC --JEITA --European projection sot804-3_po Issue date 09-02-24 10-08-06 Fig 35. Package outline SOT804-3 (HVQFN64) ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 36 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 13. Abbreviations Table 34. Acronym ADC CMOS DAV DCS DFS ESD FS IMD LSB LVCMOS LVDS DDR LVPECL MSB OTR SFDR SNR SPI TX Abbreviations Description Analog-to-Digital Converter Complementary Metal Oxide Semiconductor DAta Valid Duty Cycle Stabilizer Data Format Select ElectroStatic Discharge Full-Scale InterModulation Distortion Least Significant Bit Low Voltage Complementary Metal Oxide Semiconductor Low Voltage Differential Signalling Double Data Rate Low-Voltage Positive Emitter-Coupled Logic Most Significant Bit OuT-of-Range Spurious-Free Dynamic Range Signal-to-Noise Ratio Serial Peripheral Interface Transmitter ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 37 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 14. Revision history Table 35. Revision history Release date 20110303 Data sheet status Product data sheet Change notice Supersedes ADC1112D125 v.1 Document ID ADC1112D125 v.2 Modifications: • • • • Data sheet status changed from Preliminary to Product. Text and drawings updated throughout entire data sheet. Section 10.4 “Typical characteristics” has been added to the data sheet. Section 13 “Abbreviations” has been added to the data sheet. Preliminary data sheet - ADC1112D125 v.1 20100806 ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 38 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. © NXP B.V. 2011. All rights reserved. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or ADC1112D125 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 2 — 3 March 2011 39 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1112D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 3 March 2011 40 of 41 NXP Semiconductors ADC1112D125 Dual 11-bit ADC: CMOS or LVDS DDR digital outputs 17. Contents 1 2 3 4 5 6 6.1 6.1.1 6.1.2 6.2 6.2.1 6.2.2 7 8 9 10 10.1 10.2 10.3 10.4 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 CMOS outputs selected . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 LVDS DDR outputs selected. . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal characteristics . . . . . . . . . . . . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Clock and digital output timing . . . . . . . . . . . . 11 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Typical characteristics . . . . . . . . . . . . . . . . . . 14 Application information. . . . . . . . . . . . . . . . . . 16 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI and Pin control modes . . . . . . . . . . . . . . . 16 Operating mode selection. . . . . . . . . . . . . . . . 16 Selecting the output data standard . . . . . . . . . 16 Selecting the output data format. . . . . . . . . . . 17 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 17 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 18 System reference and power management . . 19 Internal/external references . . . . . . . . . . . . . . 19 Programmable full-scale . . . . . . . . . . . . . . . . . 21 Common-mode output voltage (VO(cm)) . . . . . 21 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 22 Equivalent input circuit . . . . . . . . . . . . . . . . . . 23 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 24 Clock input divider . . . . . . . . . . . . . . . . . . . . . 24 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 24 Digital output buffers: CMOS mode . . . . . . . . 24 Digital output buffers: LVDS DDR mode . . . . . 25 DAta Valid (DAV) output clock . . . . . . . . . . . . 26 OuT-of-Range (OTR) . . . . . . . . . . . . . . . . . . . 26 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11.5.6 11.5.7 11.6 11.6.1 11.6.2 11.6.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . Output codes versus input voltage. . . . . . . . . Serial Peripheral Interface (SPI) . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . . Default modes at start-up. . . . . . . . . . . . . . . . Register allocation map . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 27 28 30 36 37 38 39 39 39 39 40 40 41 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 March 2011 Document identifier: ADC1112D125