ADC1415S080HN

ADC1415S series Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs Rev. 4 — 17 December 2010 Product data sheet 1. General description The ADC1415S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1415S is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. The ADC1415S supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1415S is ideal for use in communications, imaging and medical applications - especially in high Intermediate Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures that the input impedance remains constant and low and the performance consistent over a wide frequency range. 2. Features and benefits SNR, 72 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps 14-bit pipelined ADC core Clock input divided by 2 for less jitter contribution Integrated input buffer Flexible input voltage range: 1 V (p-p) to 2 V (p-p) CMOS or LVDS DDR digital outputs Pin compatible with ADC1215S series, ADC1015S series and the ADC1115S125 Input bandwidth, 600 MHz Power dissipation, 635 mW at 80 Msps, including analog input buffer Serial Peripheral Interface (SPI) Duty cycle stabilizer Fast OuT-of-Range (OTR) detection Offset binary, two’s complement, gray code Power-down mode and Sleep mode HVQFN40 package NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 3. Applications Wireless and wired broadband communications Portable instrumentation Imaging systems Digital predistortion loop, power amplifier linearization Spectral analysis Ultrasound equipment Software defined radio 4. Ordering information Table 1. Ordering information fs (Msps) Package Name ADC1415S125HN/C1 125 ADC1415S105HN/C1 105 ADC1415S080HN/C1 80 ADC1415S065HN/C1 65 Description Version SOT618-6 SOT618-6 SOT618-6 SOT618-6 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm Type number ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 2 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 5. Block diagram SDIO/ODS CS SCLK/DFS ADC1415S ERROR CORRECTION AND DIGITAL PROCESSING SPI OTR CMOS: D13 to D0 or LVDS DDR: D12_D13_P to D0_D1_P D12_D13_M to D0_D1_M CMOS: DAV or LVDS DDR: DAVP DAVM INP INPUT BUFFER INM S/H INPUT STAGE ADC CORE 14-BIT PIPELINED OUTPUT DRIVERS OUTPUT DRIVERS CLOCK INPUT STAGE AND DUTY CYCLE CONTROL SYSTEM REFERENCE AND POWER MANAGEMENT PWD OE CLKP CLKM VREF REFB VCM SENSE REFT 005aaa101 Fig 1. Block diagram ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 3 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 6. Pinning information 6.1 Pinning 36 SCLK/DFS 37 SDIO/ODS 39 SENSE 34 OGND 33 VDDO 40 VREF 35 OTR 36 SCLK/DFS 37 SDIO/ODS 39 SENSE 34 OGND 33 VDDO 40 VREF 35 OTR terminal 1 index area REFB REFT AGND VCM VDDA5V AGND INM INP AGND 1 2 3 4 5 6 7 8 9 31 DAV 32 n.c. 38 CS REFB REFT 30 D0 29 D1 28 D2 27 D3 26 D4 25 D5 24 D6 23 D7 22 D8 21 D9 AGND VCM VDDA5V AGND INM INP AGND 1 2 3 4 5 6 7 8 9 38 CS terminal 1 index area 31 DAV 30 D0_D1_P 29 D0_D1_M 28 D2_D3_P 27 D2_D3_M 26 D4_D5_P 25 D4_D5_M 24 D6_D7_P 23 D6_D7_M 22 D8_D9_P 21 D8_D9_M D10_D11_P 20 005aaa103 ADC1215S HVQFN40 ADC1415S HVQFN40 VDDA3V 10 VDDA3V 11 CLKP 12 CLKM 13 DEC 14 OE 15 PWD 16 D12_D13_M 17 D12_D13_P 18 D10_D11_M 19 VDDA3V 10 VDDA3V 11 CLKP 12 CLKM 13 DEC 14 OE 15 PWD 16 D13 17 D12 18 D11 19 D10 20 Transparent top view 005aaa102 Transparent top view Fig 2. Pin configuration with CMOS digital outputs selected Fig 3. Pin configuration with LVDS/DDR digital outputs selected 6.2 Pin description Table 2. Symbol REFB REFT AGND VCM VDDA5V AGND INM INP AGND VDDA3V VDDA3V CLKP CLKM DEC OE PWD ADC1415S_SER Pin description (CMOS digital outputs) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type [1] O O G O P G I I G P P I I O I I Description bottom reference top reference analog ground common-mode output voltage 5 V analog power supply analog ground complementary analog input analog input analog ground 3 V analog power supply 3 V analog power supply clock input complementary clock input regulator decoupling node output enable, active LOW power down, active HIGH © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 4 — 17 December 2010 32 n.c. 4 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Pin description (CMOS digital outputs) …continued Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Type [1] O O O O O O O O O O O O O O O P G O I I/O I I I/O Description data output bit 13 (Most Significant Bit (MSB)) data output bit 12 data output bit 11 data output bit10 data output bit 9 data output bit 8 data output bit 7 data output bit 6 data output bit 5 data output bit 4 data output bit 3 data output bit 2 data output bit 1 data output bit 0 (Least Significant Bit (LSB)) data valid output clock not connected output power supply output ground out of range SPI clock / data format select SPI data IO / output data standard SPI chip select reference programming pin voltage reference input/output Table 2. Symbol D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAV n.c. VDDO OGND OTR SCLK/DFS SDIO/ODS CS SENSE VREF [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 3. Symbol Pin description (LVDS DDR) digital outputs) Pin [1] 17 18 19 20 21 22 23 24 25 26 27 28 29 Type [2] O O O O O O O O O O O O O Description differential output data D12 and D13 multiplexed, complement differential output data D12 and D13 multiplexed, true differential output data D10 and D11 multiplexed, complement differential output data D10 and D11 multiplexed, true differential output data D8 and D9 multiplexed, complement differential output data D8 and D9 multiplexed, true differential output data D6 and D7 multiplexed, complement differential output data D6 and D7 multiplexed, true differential output data D4 and D5 multiplexed, complement differential output data D4 and D5 multiplexed, true differential output data D2 and D3 multiplexed, complement differential output data D2 and D3 multiplexed, true differential output data D0 and D1 multiplexed, complement D12_D13_M D12_D13_P D10_D11_M D10_D11_P D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 5 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Pin description …continued (LVDS DDR) digital outputs) Pin [1] 30 31 32 Type [2] O O O Description differential output data D0 and D1 multiplexed, true data valid output clock, complement data valid output clock, true Table 3. Symbol D0_D1_P DAVM DAVP [1] [2] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2) P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VO Parameter output voltage Conditions pins D13 to D0 or pins D12_D13_P to D0_D1_P and D12_D13_M to D0_D1_M on pin VDDA3V on pin VDDA5V Min −0.4 Max +3.9 Unit V VDDA(3V) VDDA(5V) VDDO Tstg Tamb Tj analog supply voltage 3 V analog supply voltage 5 V output supply voltage storage temperature ambient temperature junction temperature −0.4 −0.5 −0.4 −55 −40 - +4.6 +6.0 +4.6 +125 +85 125 V V V °C °C °C 8. Thermal characteristics Table 5. Symbol Rth(j-a) Rth(j-c) [1] Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions [1] [1] Typ 30.5 13.3 Unit K/W K/W Value for six layers board in still air with a minimum of 25 thermal vias. ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 6 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 9. Static characteristics Table 6. Symbol Supplies VDDA(5V) VDDA(3V) VDDO IDDA(5V) IDDA(3V) IDDO analog supply voltage 5 V analog supply voltage 3 V output supply voltage analog supply current 5 V analog supply current 3 V output supply current CMOS mode LVDS DDR mode fclk = 125 Msps; fi = 70 MHz fclk = 125 Msps; fi = 70 MHz CMOS mode; fclk = 125 Msps; fi = 70 MHz LVDS DDR mode: fclk = 125 Msps; fi = 70 MHz P power dissipation ADC1415S125; analog supply only ADC1415S105; analog supply only ADC1415S080; analog supply only ADC1415S065; analog supply only Power-down mode Standby mode Clock inputs: pins CLKP and CLKM LVPECL Vi(clk)dif SINE wave Vi(clk)dif LVCMOS VIL VIH VIL VIH IIL IIH VIL VIH ADC1415S_SER Static characteristics[1] Parameter Conditions Min 4.75 2.85 1.65 2.85 Typ 5.0 3.0 1.8 3.0 46 205 14 Max 5.25 3.4 3.6 3.6 Unit V V V V mA mA mA - 43 - mA - 840 770 635 580 2 40 - mW mW mW mW mW mW differential clock input voltage differential clock input voltage LOW-level input voltage HIGH-level input voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage peak-to-peak peak 0.7VDDA(3V) 0 2 0 0.7VDDA(3V) 1.6 ±3.0 55 65 - 0.3VDDA(3V) 0.8 VDDA(3V) 0.3VDDA(3V) VDDA(3V) V V V V V V μA μA V V Logic inputs: pins PWD and OE Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 7 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Table 6. Symbol IIL IIH CI Static characteristics[1] …continued Parameter LOW-level input current HIGH-level input current input capacitance Conditions Min −10 −50 Typ 4 Max +10 +50 Unit μA μA pF Digital outputs, CMOS mode: pins D13 to D0, OTR, DAV Output levels, VDDO = 3 V VOL VOH CO LOW-level output voltage HIGH-level output voltage output capacitance high impedance; OE = HIGH OGND 0.8VDDO 3 0.2VDDO VDDO V V pF Output levels, VDDO = 1.8 V VOL VOH LOW-level output voltage HIGH-level output voltage OGND 0.8VDDO 0.2VDDO VDDO V V Digital outputs, LVDS mode: pins D12_D13_P to D0_D1_P, D12_D13_M to D0_D1_M, DAVP and DAVM Output levels, VDDO = 3 V only, Rload = 100 Ω VO(offset) VO(dif) CO II RI CI VI(cm) Bi VI(dif) VO(cm) IO(cm) VVREF output offset voltage differential output voltage output capacitance input current input resistance input capacitance common-mode input voltage input bandwidth differential input voltage common-mode output voltage common-mode output current voltage on pin VREF output input peak-to-peak VINP = VINM output buffer current set to 3.5 mA output buffer current set to 3.5 mA −5 0.9 1 0.5 1.2 350 3 550 1.3 1.5 600 0.5VDDA(3V) 4 0.5 to 1 +5 2 2 1 V mV pF μA Ω pF V MHz V V mA V V Analog inputs: pins INP and INM Common mode output voltage: pin VCM I/O reference voltage: pin VREF ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 8 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Table 6. Symbol Accuracy INL DNL Eoffset EG Supply PSRR Static characteristics[1] …continued Parameter integral non-linearity differential non-linearity offset error gain error power supply rejection ratio 200 mV (p-p) on VDDA(3V) guaranteed no missing codes Conditions Min −5 −0.95 Typ ±0.5 ±2 ±0.5 −54 Max +5 +0.95 Unit LSB LSB mV %FS dBc [1] Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 9 of 42 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7. Symbol Dynamic characteristics[1] Parameter Conditions ADC1415S065 Min Analog signal processing α2H second harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz α3H third harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz THD total harmonic distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz ENOB effective number of bits fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SNR signal-tonoise ratio fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz 87 86 85 82 86 85 84 81 83 82 81 78 11.7 11.6 11.5 11.4 72.1 71.3 70.7 70.2 86 85 84 81 87 86 85 82 86 85 84 81 83 82 81 78 11.7 11.5 11.5 11.4 72.0 71.2 70.7 70.1 86 85 84 81 86 86 84 81 85 85 83 80 82 82 80 77 11.6 11.5 11.4 11.3 71.8 71.2 70.6 70.0 85 85 83 80 88 87 85 83 87 86 84 82 84 83 81 79 11.6 11.5 11.4 11.3 71.4 71.1 70.5 69.9 87 86 84 82 dBc dBc dBc dBc Typ Max ADC1415S080 Min Typ Max ADC1415S105 Min Typ Max ADC1415S125 Min Typ Max Unit Product data sheet Rev. 4 — 17 December 2010 10 of 42 ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBFS dBFS dBFS dBFS dBc dBc dBc dBc ADC1415S series SFDR spuriousfree dynamic range fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 7. Symbol IMD Dynamic characteristics[1] …continued Parameter Intermodulation distortion Conditions fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz [1] Product data sheet Rev. 4 — 17 December 2010 11 of 42 ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors ADC1415S065 Min Typ 89 88 87 84 Max - ADC1415S080 Min Typ 89 88 87 85 Max - ADC1415S105 Min Typ 88 88 86 83 Max - ADC1415S125 Min Typ 89 88 86 84 Max Unit dBc dBc dBc dBc Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs ADC1415S series xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.2 Clock and digital output timing Table 8. Symbol Clock and digital output timing characteristics[1] Parameter Conditions ADC1410S065 Min Clock timing input: pins CLKP and CLKM fclk tlat(data) δclk td(s) clock frequency data latency time clock duty cycle DCS_EN = 1 DCS_EN = 0 sampling delay time wake-up time propagation delay set-up time hold time rise time fall time DATA DAV tf DATA [2] [2] Product data sheet Rev. 4 — 17 December 2010 12 of 42 ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors ADC1410S080 Min 60 30 45 11.9 0.39 0.26 0.19 13.5 50 50 0.8 76 12.9 3.6 9.8 3.3 Typ Max 80 70 55 14.4 2.4 2.4 2.4 ADC1410S105 Min 75 30 45 8.0 0.39 0.26 0.19 13.5 50 50 0.8 76 10.8 3.3 6.8 3.1 Typ Max 105 70 55 12.4 2.4 2.4 2.4 ADC1410S125 Min 100 30 45 8.2 0.39 0.26 0.19 13.5 50 50 0.8 76 9.7 3.4 5.6 2.8 Typ Max 125 70 55 11.3 2.4 2.4 2.4 Unit Typ 13.5 50 50 0.8 76 14.9 4.2 12.5 3.4 - Max 65 70 55 16.4 2.4 2.4 2.4 40 30 45 DATA DAV 13.6 0.39 0.26 0.19 MHz clock cycles % % ns Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs twake tPD tsu th tr μs ns ns ns ns ns ns ns CMOS Mode timing output: pins D13 to D0 and DAV ADC1415S series xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 8. Symbol Clock and digital output timing characteristics[1] …continued Parameter Conditions ADC1410S065 Min tPD tsu th tr tf All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 13 of 42 ADC1415S_SER NXP Semiconductors ADC1410S080 Min 2.9 0.5 0.18 0.15 Typ 4.6 2.5 4.1 2.0 Max 7.1 5 2.4 1.6 ADC1410S105 Min 2.5 0.5 0.18 0.15 Typ 4.2 2.3 2.6 1.8 Max 6.8 5 2.4 1.6 ADC1410S125 Min 2.2 0.5 0.18 0.15 Typ 4.0 2.2 1.9 1.7 Max 6.6 5 2.4 1.6 Unit Typ 5.1 2.8 5.4 2.2 - Max 7.6 5 2.4 1.6 LVDS DDR mode timing output: pins D12_D13_P to D0_D1_P, D12_D13_M to D0_D1_M, DAVP and DAVM propagation delay set-up time hold time rise time fall time DATA DAV DATA [3] [3] DATA DAV 3.3 0.5 0.18 0.15 ns ns ns ns ns ns ns [1] Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Measured between 20 % to 80 % of VDDO. Rise time measured from −50 mV to +50 mV; fall time measured from +50 mV to −50 mV. Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs [2] [3] ADC1415S series NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs N N+1 td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tPD tsu DAV th tclk 005aaa060 Fig 4. CMOS mode timing N N+1 td(s) N+2 tclk CLKP CLKM tPD Dx_Dx + 1_P Dx Dx_Dx + 1_M tsu th tsu th DAVP DAVM tclk 005aaa061 (N − 14) (N − 13) (N − 12) (N − 11) Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 tPD Fig 5. LDVS DDR mode timing ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 14 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 10.3 SPI timings Table 9. Symbol tw(SCLK) tw(SCLKH) tw(SCLKL) tsu th fclk(max) [1] SPI timings characteristics[1] Parameter SCLK pulse width SCLK HIGH pulse width SCLK LOW pulse width set-up time hold time maximum clock frequency data to SCLK HIGH CS to SCLK HIGH data to SCLK HIGH CS to SCLK HIGH Conditions Min Typ 40 16 16 5 5 2 2 25 Max Unit ns ns ns ns ns ns ns MHz Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V, VDDO = 1.8 V tsu CS th tsu tw(SCLKL) tw(SCLK) tw(SCLKH) th SCLK SDIO R/W W1 W0 A12 A11 D2 D1 D0 005aaa065 Fig 6. SPI timing ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 15 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 10.4 Typical characteristics 100 SFDR (dBc) 80 60 001aam616 80 SNR (dBFS) (1) 001aam615 (1) 60 (2) (2) 40 40 20 20 0 10 30 50 70 δ (%) 90 0 10 30 50 70 δ (%) 90 T = 25 °C; VDD = 3 V; fi = 170 MHz; fs = 125 Msps (1) DCS on (2) DCS off T = 25 °C; VDD = 3 V; fi = 170 MHz; fs = 125 Msps (1) DCS on (2) DCS off Fig 7. Spurious-free dynamic range as a function of duty cycle (δ) Fig 8. Signal-to-noise ratio as a function of duty cycle (δ) 92 SFDR (dBc) 88 001aam617 80 SNR (dBFS) 60 001aam618 (1) (2) (1) (2) (3) (3) 84 40 80 10 30 50 70 δ (%) 90 20 10 30 50 70 δ (%) 90 (1) Tamb = −40 °C, typical supply voltages (2) Tamb = +25 °C, typical supply voltages (3) Tamb = +90 °C, typical supply voltages (1) Tamb = −40 °C, typical supply voltages (2) Tamb = +25 °C, typical supply voltages (3) Tamb = +90 °C, typical supply voltages Fig 9. Spurious-free dynamic range as a function of duty cycle (δ) Fig 10. Signal-to-noise ratio as a function of duty cycle (δ) ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 16 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 90 SFDR (dBc) 86 001aam659 75 SNR (dBFS) 73 001aam660 82 71 78 69 74 67 70 0 0.5 1.0 1.5 2.0 2.5 3.0 VI(cm) (V) 3.5 65 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VI(cm) (V) Fig 11. Spurious-free dynamic range as a function of common-mode input voltage (Vi(cm)) Fig 12. Signal-to-noise ratio as a function of common-mode input voltage (Vi(cm)) 11. Application information 11.1 Device control The ADC1415S can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been enabled, the device remains in this mode. The transition from Pin control mode to SPI control mode is illustrated in Figure 13. CS Pin control mode Data format offset binary SPI control mode SCLK/DFS Data format two's complement LVDS DDR SDIO/ODS CMOS R/W W1 W0 A12 005aaa039 Fig 13. Control mode selection. When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO as soon as a transition is triggered by a falling edge on CS. ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 17 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 11.1.2 Operating mode selection The active ADC1415S operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 19) or using pins PWD and OE in Pin control mode, as described in Table 10. Table 10. Pin PWD 0 0 1 1 Operating mode selection via pin PWD and OE Pin OE 0 1 0 1 Operating mode Power-up Power-up Sleep Power-down Output high-Z no yes yes yes 11.1.3 Selecting the output data standard The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 23) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected. 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 23) or using pin DFS in Pin control mode (offset binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.1 Input stage The analog input of the ADC1415S supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs. The ADC inputs are internally biased and need to be decoupled. The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 21). The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input stage, including ElectroStatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 14. ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 18 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs package ESD parasitics switch INP 8 Ron = 15 Ω 4 pF internal clock INPUT BUFFER Ron = 15 Ω sampling capacitor switch INM 7 4 pF internal clock sampling capacitor 005aaa107 Fig 14. Input sampling circuit and input buffer The integrated input buffer offers the following advantages: • The kickback effect is avoided - the charge injection and glitches generated by the S/H input stage are isolated from the input circuitry. So there’s no need for additional filtering. • The input capacitance is very low and constant over a wide frequency range, which makes the ADC1415S easy to drive. The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core. ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 19 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 11.2.2 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 15 would be suitable for a baseband application. ADT1-1WT Analog input 100 nF 100 nF INP 50 Ω 100 nF 100 nF INM VCM 100 nF 100 nF 005aaa108 Fig 15. Single transformer configuration suitable for baseband applications The configuration shown in Figure 16 is recommended for high frequency applications. In both cases, the choice of transformer is a compromise between cost and performance. ADT1-1WT 100 nF 50 Ω ADT1-1WT 100 nF INP Analog input 100 Ω 50 Ω 100 nF INM VCM 100 nF 100 nF 100 nF 005aaa109 Fig 16. Dual transformer configuration suitable for high intermediate frequency application ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 20 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 11.3 System reference and power management 11.3.1 Internal/external references The ADC1415S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and −6 dB via control bits INTREF[2:0] when bit INTREF_EN = logic 1; see Table 21) See Figure 18 to Figure 21. The equivalent reference circuit is shown in Figure 17. External reference is also possible by providing a voltage on pin VREF as described in Figure 20. REFAT/ REFBT REFERENCE AMP REFAB/ REFBB VREF EXT_ref BUFFER EXT_ref BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 005aaa164 Fig 17. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 11. Table 11. Selection internal (Figure 18) internal (Figure 19) external (Figure 20) internal via SPI (Figure 21) [1] ADC1415S_SER Reference selection SPI bit INTREF_EN 0 0 0 1 SENSE pin AGND VREF pin 330 pF capacitor to AGND Full-scale (p-p) 2V 1V 1 V to 2 V 1 V to 2 V pin VREF connected to pin SENSE and via a 330 pF capacitor to AGND VDDA(3V) external voltage between 0.5 V and 1 V[1] pin VREF connected to pin SENSE and via 330 pF capacitor to AGND The voltage on pin VREF is doubled internally to generate the internal reference voltage. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 21 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs VREF 330 pF VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa116 005aaa117 Fig 18. Internal reference, 2 V (p-p) full scale Fig 19. Internal reference, 1 V (p-p) full scale VREF 0.1 μF VREF V REFERENCE EQUIVALENT SCHEMATIC 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE VDDA 005aaa119 005aaa118 Fig 20. External reference, 1 V (p-p) to 2 V (p-p) full-scale Fig 21. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale Figure 18 to Figure 21 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. 11.3.2 Programmable full-scale The full-scale is programmable between 1 V (peak-to-peak) to 2 V (peak-to-peak) (see Table 12). Table 12. INTREF 000 001 010 011 100 101 110 111 Reference SPI Gain Control Gain 0 dB −1 dB −2 dB −3 dB −4 dB −5 dB −6 dB reserved Full-scale (p-p) 2V 1.78 V 1.59 V 1.42 V 1.26 V 1.12 V 1V x 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 μF filter capacitor should be connected between pin VCM and ground. 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INP and INM is set internally. The input buffer bias current can be set to one of three levels (high, medium or low) via the SPI (see Table 22). ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 22 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 11.4 Clock input 11.4.1 Drive modes The ADC1415S can be driven differentially (LVPECL). It can also be driven by a single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or CLKM (pin CLKP should be connected to ground via a capacitor). LVCMOS clock input CLKP CLKP CLKM LVCMOS clock input CLKM 005aaa174 005aaa053 a. Rising edge LVCMOS Fig 22. LVCMOS single-ended clock input b. Falling edge LVCMOS CLKP Sine clock input Sine clock input CLKP CLKM CLKM 005aaa173 005aaa054 a. Sine clock input b. Sine clock input (with transformer) CLKP LVPECL clock input CLKM 005aaa172 c. LVPECL clock input Fig 23. Differential clock input ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 23 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 24. The common-mode voltage of the differential input stage is set via internal 5 kΩ resistors. Package ESD Parasitics CLKP Vcm(clk) SE_SEL SE_SEL 5 kΩ 5 kΩ CLKM 005aaa056 Vcm(clk) = common-mode voltage of the differential input stage. Fig 24. Equivalent input circuit Single-ended or differential clock inputs can be selected via the SPI interface (see Table 20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.3 Duty cycle stabilizer The duty cycle stabilizer can improve the overall performance of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = logic 1; see Table 20), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and 55 %. 11.4.4 Clock input divider The ADC1415S contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = logic 1; see Table 20). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed. ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 24 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to logic_0 (see Table 23). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 25. The buffer is powered by a separate OGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF. VDDO Parasitics ESD Package LOGIC DRIVER 50 Ω Dx OGND 005aaa057 Fig 25. CMOS digital output buffer The output resistance is 50 Ω and is the combination of the an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 30): ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 25 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to logic_1 (see Table 23). VCCO 3.5 mA typ − + DnP/Dn + 1P 100 Ω DnM/Dn + 1M RECEIVER + − OGND 005aaa058 Fig 26. LVDS DDR digital output buffer - externally terminated Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver side (Figure 26) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 27 and Table 32). VCCO 3.5 mA typ − + DxP/Dx + 1P RECEIVER DxM/Dx + 1M 100 Ω + − OGND 005aaa059 Fig 27. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic voltage levels. Table 13. 000 001 010 011 100 ADC1415S_SER LVDS DDR output register 2 Resistor value (Ω) no internal termination 300 180 110 150 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. LVDS_INT_TER[2:0] Product data sheet Rev. 4 — 17 December 2010 26 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs LVDS DDR output register 2 …continued Resistor value (Ω) 100 81 60 Table 13. 101 110 111 LVDS_INT_TER[2:0] 11.5.3 DAta Valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1415S. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 4 and Figure 5 respectively. 11.5.4 Out-of-Range (OTR) An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = logic 1; see Table 29). In this mode, the latency of OTR is reduced to only four clock cycles. The Fast OTR detection threshold (below full-scale) can be programmed via bits FASTOTR_DET[2:0]. Table 14. 000 001 010 011 100 101 110 111 Fast OTR register Detection level (dB) −20.56 −16.12 −11.02 −7.82 −5.49 −3.66 −2.14 −0.86 FASTOTR_DET[2:0] 11.5.5 Digital offset By default, the ADC1415S delivers output code that corresponds to the analog input. However it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET[5:0]; see Table 25). 11.5.6 Test patterns For test purposes, the ADC1415S can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern can be defined by the user (TESTPAT_USER; see Table 27 and Table 28) and is selected when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted regardless of the analog input. ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 27 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 11.5.7 Output codes versus input voltage Table 15. VINP − VINM < −1 −1 −0.9998779 −0.9997559 −0.9996338 −0.9995117 .... −0.0002441 −0.0001221 0 +0.0001221 +0.0002441 .... +0.9995117 +0.9996338 +0.9997559 +0.9998779 +1 > +1 Output codes Offset binary 00 0000 0000 0000 00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0010 00 0000 0000 0011 00 0000 0000 0100 .... 01 1111 1111 1110 01 1111 1111 1111 10 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0010 .... 11 1111 1111 1011 11 1111 1111 1100 11 1111 1111 1101 11 1111 1111 1110 11 1111 1111 1111 11 1111 1111 1111 Two’s complement 10 0000 0000 0000 10 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0010 10 0000 0000 0011 10 0000 0000 0100 .... 11 1111 1111 1110 11 1111 1111 1111 00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0010 .... 01 1111 1111 1011 01 1111 1111 1100 01 1111 1111 1101 01 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 OTR pin 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 11.6 Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1415S serial interface is a synchronous serial communications port that allows easy interfacing with many commonly-used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 17). Table 16. Bit Description Instruction bytes for the SPI MSB 7 R/W[1] A7 [1] [2] LSB 6 W1[2] A6 5 W0[2] A5 4 A12 A4 3 A11 A3 2 A10 A2 1 A9 A1 0 A8 A0 Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation. Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 17). ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 28 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Number of data bytes to be transferred after the instruction bytes W0 0 1 0 1 Number of bytes transmitted 1 byte 2 bytes 3 bytes 4 bytes or more Table 17. W1 0 0 1 1 Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows: 1. A falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on CS indicates the end of data transmission. CS SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction bytes Register N (data) Register N + 1 (data) 005aaa062 Fig 28. SPI mode timing 11.6.2 Default modes at start-up During circuit initialization it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on CS triggers a transition to SPI control mode. When the ADC1415S enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 29). Once in SPI control mode, the output data standard can be changed via bit LVDS/CMOS in Table 23. When the ADC1415S enters SPI control mode, the output data format (two’s complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] in Table 23. ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 29 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data format) SDIO (CMOS LVDS DDR) two's complement, CMOS default mode at start-up 005aaa064 Fig 30. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 30 of 42 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 11.6.3 Register allocation map Table 18. Add Hex Register allocation map R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DAVI_x2_ EN DAVI[1:0] BIT_BYTE_ WISE Bit definition Bit 7 SW_RST TESTPAT_USER[13:6] TESTPAT_USER[5:0] FASTOTR DAV_DRV[1:0] DATAI_x2_EN FASTOTR_DET[2:0] DATA_DRV[1:0] DATAI[1:0] Bit 6 Bit 5 Bit 4 Bit 3 DIFF_SE INTREF_EN LVDS_ CMOS OUTBUF DAVINV DIG_OFFSET[5:0] TESTPAT_SEL[2:0] OUTBUS_SWAP Bit 2 Bit 1 Bit 0 OP_MODE[1:0] CLKDIV INTREF[2:0] IB_IBIAS[1:0] DATA_FORMAT[1:0] DCS_EN RESERVED[2:0] SE_SEL Default Bin 0000 0000 0000 0001 0000 0000 0000 0011 0000 0000 0000 1110 Register name Product data sheet Rev. 4 — 17 December 2010 31 of 42 ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors 0005 Reset and operating mode 0006 Clock 0008 Internal reference 0010 Input buffer 0011 Output data standard. 0012 Output clock 0013 Offset 0014 Test pattern 1 0015 Test pattern 2 0016 Test pattern 3 0017 Fast OTR 0020 CMOS output 0021 LVDS DDR O/P 1 0022 LVDS DDR O/P 2 DAVPHASE[2:0] Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 0000 0000 0000 0000 LVDS_INT_TER[2:0] ADC1415S series NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Table 19. Reset and operating mode control register (address 0005h) bit description Default values are highlighted. Bit 7 Symbol SW_RST Access R/W 0 1 6 to 4 3 to 2 1 to 0 RESERVED[2:0] OP_MODE[1:0] R/W 00 01 10 11 000 00 Value Description reset digital section no reset performs a reset on SPI registers reserved not used operating mode normal (Power-up) Power-down Sleep normal (Power-up) Table 20. Clock control register (address 0006h) bit description Default values are highlighted. Bit 7 to 5 4 Symbol SE_SEL R/W 0 1 3 DIFF_SE R/W 0 1 2 1 CLKDIV R/W 0 1 0 DCS_EN R/W 0 1 0 Access Value 000 Description not used single-ended clock input pin select CLKM CLKP differential/single ended clock input select fully differential single-ended not used clock input divide by 2 disabled enabled duty cycle stabilizer disabled enabled ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 32 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Table 21. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol INTREF_EN R/W 0 1 2 to 0 INTREF[2:0] R/W 000 001 010 011 100 101 110 111 Access Value 0000 Description not used programmable internal reference enable disable active programmable internal reference 0 dB (FS = 2 V) −1 dB (FS = 1.78 V) −2 dB (FS = 1.59 V) −3 dB (FS = 1.42 V) −4 dB (FS = 1.26 V) −5 dB (FS = 1.12 V) −6 dB (FS = 1 V) reserved Table 22. Input buffer control register (address 0010h) bit description Default values are highlighted. Bit 7 to 2 1 to 0 Symbol IB_IBIAS[1:0] R/W 00 01 10 11 Access Value 000000 Description not used input buffer bias current not used medium low high Table 23. Output data standard control register (address 0011h) bit description Default values are highlighted. Bit 7 to 5 4 Symbol LVDS_CMOS R/W 0 1 3 OUTBUF R/W 0 1 2 OUTBUS_SWAP R/W 0 1 Access Value 000 Description not used output data standard: LVDS DDR or CMOS CMOS LVDS DDR output buffers enable output enabled output disabled (high Z) output bus swapping no swapping output bus is swapped (MSB becomes LSB and vice versa) ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 33 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Table 23. Output data standard control register (address 0011h) bit description …continued Default values are highlighted. Bit 1 to 0 Symbol DATA_FORMAT[1:0] Access R/W 00 01 10 11 Value Description output data format offset binary two’s complement gray code offset binary Table 24. Output clock register (address 0012h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol DAVINV R/W 0 1 2 to 0 DAVPHASE[2:0] R/W 000 001 010 011 100 101 110 111 Access Value 0000 Description not used output clock data valid (DAV) polarity normal inverted DAV phase select output clock shifted (ahead) by 3 ns output clock shifted (ahead) by 2.5 ns output clock shifted (ahead) by 2 ns output clock shifted (ahead) by 1.5 ns output clock shifted (ahead) by 1 ns output clock shifted (ahead) by 0.5 ns default value as defined in timing section output clock shifted (delayed) by 0.5 ns Table 25. Offset register (address 0013h) bit description Default values are highlighted. Bit 7 to 6 5 to 0 Symbol DIG_OFFSET[5:0] R/W 011111 ... 000000 ... 100000 Access Value 00 Description not used digital offset adjustment +31 LSB ... 0 ... −32 LSB Table 26. Test pattern register 1 (address 0014h) bit description Default values are highlighted. Bit 7 to 3 Symbol Access Value 00000 Description not used ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 34 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Table 26. Test pattern register 1 (address 0014h) bit description …continued Default values are highlighted. Bit 2 to 0 Symbol TESTPAT_SEL[2:0] Access R/W 000 001 010 011 100 101 110 111 Value Description digital test pattern select off mid scale −FS +FS toggle ‘1111..1111’/’0000..0000’ custom test pattern ‘1010..1010.’ ‘010..1010’ Table 27. Test pattern register 2 (address 0015h) bit description Default values are highlighted. Bit 7 to 0 Symbol TESTPAT_USER[13:6] Access R/W Value 00000000 Description custom digital test pattern (bits 13 to 6) Table 28. Test pattern register 3 (address 0016h) bit description Default values are highlighted. Bit 7 to 2 1 to 0 Symbol TESTPAT_USER[5:0] Access R/W Value 000000 00 Description custom digital test pattern (bits 5 to 0) not used Table 29. Fast OTR register (address 0017h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol FASTOTR R/W 0 1 2 to 0 FASTOTR_DET[2:0] R/W 000 001 010 011 100 101 110 111 Access Value 0000 Description not used fast Out-of-Range (OTR) detection disabled enabled set fast OTR detect level −20.56 dB −16.12 dB −11.02 dB −7.82 dB −5.49 dB −3.66 dB −2.14 dB −0.86 dB ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 35 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Table 30. CMOS output register (address 0020h) bit description Default values are highlighted. Bit 7 to 4 3 to 2 Symbol DAV_DRV[1:0] R/W 00 01 10 11 1 to 0 DATA_DRV[1:0] R/W 00 01 10 11 Access Value 0000 Description not used drive strength for DAV CMOS output buffer low medium high very high drive strength for DATA CMOS output buffer low medium high very high Table 31. LVDS DDR output register 1 (address 0021h) bit description Default values are highlighted. Bit 7 to 6 5 Symbol DAVI_x2_EN R/W 0 1 4 to 3 DAVI[1:0] R/W 00 01 10 11 2 DATAI_x2_EN R/W 0 1 1 to 0 DATAI[1:0] R/W 00 01 10 11 Access Value 00 Description not used double LVDS current for DAV LVDS buffer disabled enabled LVDS current for DAV LVDS buffer 3.5 mA 4.5 mA 1.25 mA 2.5 mA double LVDS current for DATA LVDS buffer disabled enabled LVDS current for DATA LVDS buffer 3.5 mA 4.5 mA 1.25 mA 2.5 mA ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 36 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs Table 32. LVDS DDR output register 2 (address 0022h) bit description Default values are highlighted. Bit 7 to 4 3 Symbol BIT/BYTE_WISE R/W 0 1 2 to 0 LVDS_INTTER[2:0] R/W 000 001 010 011 100 101 110 111 Access Value 0000 Description not used DDR mode for LVDS output bit wise (even data bits output on DAV rising edge / odd data bits output on DAV falling edge) byte wise (MSB data bits output on DAV rising edge / LSB data bits output on DAV falling edge) internal termination for LVDS buffer (DAV and DATA) no internal termination 300 Ω 180 Ω 110 Ω 150 Ω 100 Ω 81 Ω 60 Ω ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 37 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm SOT618-6 D B A terminal 1 index area E A A1 c detail X e1 1/2 e e 11 L 10 21 e b 20 v w CAB C y1 C C y Eh 1/2 e e2 1 terminal 1 index area 40 Dh 31 30 X 0 Dimensions Unit mm A(1) A1 b c 0.2 D(1) 6.1 6.0 5.9 Dh 4.55 4.40 4.25 E(1) 6.1 6.0 5.9 Eh 4.55 4.40 4.25 e 0.5 2.5 scale e1 4.5 e2 4.5 L 0.5 0.4 0.3 5 mm v 0.1 w y y1 0.1 max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT618-6 References IEC JEDEC MO-220 JEITA --European projection sot618-6_po Issue date 09-02-23 09-03-04 Fig 31. Package outline SOT618-6 (HVQFN40) ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 38 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 13. Revision history Table 33. Revision history Release date 20101217 Data sheet status Product data sheet Change Supersedes notice ADC1415S_SER v.3 Document ID ADC1415S_SER v.4 Modifications: • • • Data sheet status changed from Preliminary to Product. Text and drawings updated throughout entire data sheet. Section 10.4 “Typical characteristics” added to the data sheet. Preliminary data sheet Objective data sheet Objective data sheet ADC1415S065_080_105_125_2 ADC1415S065_080_105_125_1 - ADC1415S_SER v.3 20100412 ADC1415S065_080_105_125_2 20090604 ADC1415S065_080_105_125_1 20090528 ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 39 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 14. Legal information 14.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. © NXP B.V. 2010. All rights reserved. 14.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or ADC1415S_SER All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 4 — 17 December 2010 40 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 17 December 2010 41 of 42 NXP Semiconductors ADC1415S series Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 10.4 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 11.6.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal characteristics . . . . . . . . . . . . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Clock and digital output timing . . . . . . . . . . . . 12 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Typical characteristics . . . . . . . . . . . . . . . . . . 16 Application information. . . . . . . . . . . . . . . . . . 17 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI and Pin control modes . . . . . . . . . . . . . . . 17 Operating mode selection. . . . . . . . . . . . . . . . 18 Selecting the output data standard . . . . . . . . . 18 Selecting the output data format. . . . . . . . . . . 18 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 20 System reference and power management . . 21 Internal/external references . . . . . . . . . . . . . . 21 Programmable full-scale . . . . . . . . . . . . . . . . . 22 Common-mode output voltage (VO(cm)) . . . . . 22 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 23 Equivalent input circuit . . . . . . . . . . . . . . . . . . 24 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 24 Clock input divider . . . . . . . . . . . . . . . . . . . . . 24 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 25 Digital output buffers: CMOS mode . . . . . . . . 25 Digital output buffers: LVDS DDR mode . . . . . 26 DAta Valid (DAV) output clock . . . . . . . . . . . . 27 Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 27 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Output codes versus input voltage . . . . . . . . . 28 Serial Peripheral Interface (SPI) . . . . . . . . . . . 28 Register description . . . . . . . . . . . . . . . . . . . . 28 Default modes at start-up . . . . . . . . . . . . . . . . 29 11.6.3 12 13 14 14.1 14.2 14.3 14.4 15 16 Register allocation map . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 38 39 40 40 40 40 41 41 42 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 December 2010 Document identifier: ADC1415S_SER