BF1100WR

DISCRETE SEMICONDUCTORS DATA SH EET BF1100WR Dual-gate MOS-FET Product specification File under Discrete Semiconductors, SC07 1995 Apr 25 Philips Semiconductors Philips Semiconductors Product specification Dual-gate MOS-FET FEATURES • Specially designed for use at 9 to 12 V supply voltage • Short channel transistor with high forward transfer admittance to input capacitance ratio • Low noise gain controlled amplifier up to 1 GHz • Superior cross-modulation performance during AGC. APPLICATIONS • VHF and UHF applications such as television tuners and professional communications equipment. DESCRIPTION Enhancement type field-effect transistor in a plastic microminiature SOT343R package. The transistor consists of an amplifier MOS-FET with source and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. Marking code: MF. handbook, halfpage BF1100WR PINNING PIN 1 2 3 4 SYMBOL s, b d g2 g1 source drain gate 2 gate 1 DESCRIPTION d 4 3 g2 g1 2 1 Top view MAM192 s,b Fig.1 Simplified outline (SOT343R) and symbol. QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj yfs Cig1-s Crs F drain current total power dissipation operating junction temperature forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure f = 1 MHz f = 800 MHz PARAMETER drain-source voltage CONDITIONS − − − − 24 − − − MIN. − − − − 28 2.2 25 2 TYP. MAX. 14 30 280 150 33 2.6 35 − UNIT V mA mW °C mS pF fF dB 1995 Apr 25 2 Philips Semiconductors Product specification Dual-gate MOS-FET LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS ID IG1 IG2 Ptot Tstg Tj Note 1. Device mounted on a printed-circuit board. PARAMETER drain-source voltage drain current gate 1 current gate 2 current total power dissipation storage temperature operating junction temperature see Fig.2; up to Tamb = 50 °C; note 1 CONDITIONS − − − − − −65 − MIN. BF1100WR MAX. 14 30 ±10 ±10 280 +150 +150 V UNIT mA mA mA mW °C °C MLD180 MLD156 handbook, halfpage 300 40 Y fs (mS) 30 Ptot (mW) 200 20 100 10 0 0 50 100 150 200 Tamb ( oC) 0 50 0 50 100 150 T j ( oC) Fig.3 Fig.2 Power derating curve. Forward transfer admittance as a function of junction temperature; typical values. 1995 Apr 25 3 Philips Semiconductors Product specification Dual-gate MOS-FET THERMAL CHARACTERISTICS SYMBOL Rth j-a Rth j-s Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 °C; unless otherwise specified. SYMBOL V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) PARAMETER gate 1-source breakdown voltage gate 2-source breakdown voltage forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage CONDITIONS VG2-S = VDS = 0; IG1-S = 1 mA VG1-S = VDS = 0; IG2-S = 1 mA VG2-S = VDS = 0; IS-G1 = 10 mA VG1-S = VDS = 0; IS-G2 = 10 mA VG2-S = 4 V; VDS = 9 V; ID = 20 µA VG2-S = 4 V; VDS = 12 V; ID = 20 µA VG2-S(th) gate 2-source threshold voltage VG1-S = 4 V; VDS = 9 V; ID = 20 µA VG1-S = 4 V; VDS = 12 V; ID = 20 µA IDSX drain-source current VG2-S = 4 V; VDS = 9 V; RG1 = 180 kΩ; note 1 VG2-S = 4 V; VDS = 12 V; RG1 = 250 kΩ; note 2 IG1-SS IG2-SS Notes 1. RG1 connects gate 1 to VGG = 9 V; see Fig.26. 2. RG1 connects gate 1 to VGG = 12 V; see Fig.26. gate 1 cut-off current gate 2 cut-off current VG2-S = VDS = 0; VG1-S = 12 V VG1-S = VDS = 0; VG2-S = 12 V MIN. 13.2 13.2 0.5 0.5 0.3 0.3 0.3 0.3 8 8 − − PARAMETER thermal resistance from junction to ambient thermal resistance from junction to soldering point CONDITIONS note 1 Ts = 91 °C; note 2 BF1100WR VALUE 350 210 UNIT K/W K/W MAX. 20 20 1.5 1.5 1 1 1.2 1.2 13 13 50 50 V V V V V V V V UNIT mA mA nA nA 1995 Apr 25 4 Philips Semiconductors Product specification Dual-gate MOS-FET DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VG2-S = 4 V; ID = 10 mA; unless otherwise specified. SYMBOL yfs PARAMETER forward transfer admittance CONDITIONS pulsed; Tj = 25 °C VDS = 9 V VDS = 12 V Cig1-s input capacitance at gate 1 f = 1 MHz VDS = 9 V VDS = 12 V Cig2-s input capacitance at gate 2 f = 1 MHz VDS = 9 V VDS = 12 V Cos drain-source capacitance f = 1 MHz VDS = 9 V VDS = 12 V Crs reverse transfer capacitance f = 1 MHz VDS = 9 V VDS = 12 V F noise figure f = 800 MHz; GS = GSopt; BS = BSopt VDS = 9 V VDS = 12 V − − 2 2 − − 25 25 − − 1.4 1.1 − − 1.6 1.4 − − 2.2 2.2 24 24 28 28 MIN. TYP. BF1100WR MAX. 33 33 2.6 2.6 − − 1.8 1.5 35 35 2.8 2.8 UNIT mS mS pF pF pF pF pF pF fF fF dB dB MLD157 handbook, halfpage gain 0 handbook, halfpage 120 MLD158 reduction (dB) 10 Vunw (dBµV) 110 (1) (2) 20 100 30 90 40 50 0 1 2 3 VAGC (V) 4 80 0 10 20 30 40 50 gain reduction (dB) f = 50 MHz. Tj = 25 °C. (1) RG = 250 kΩ to VGG = 12 V. (2) RG = 180 kΩ to VGG = 9 V. fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C. Fig.5 Fig.4 Gain reduction as a function of the AGC voltage; typical values. Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.26. 1995 Apr 25 5 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR MLD159 handbook, halfpage 20 handbook, halfpage 20 MLD160 ID (mA) 16 V G1 S = 1.4 V 1.3 V 1.2 V ID (mA) 16 V G2 S = 4 V 3 V 2.5 V 2V 12 12 1.5 V 8 1.1 V 8 1.0 V 4 0.9 V 4 1V 0 0 4 8 12 V DS (V) 16 0 0 0.4 0.8 1.2 1.6 2.0 V G1 S (V) VG2-S = 4 V. Tj = 25 °C. VDS = 9 to 12 V. Tj = 25 °C. Fig.6 Output characteristics; typical values. Fig.7 Transfer characteristics; typical values. handbook, halfpage 250 MLD161 MLD162 I G1 (µA) handbook, halfpage 40 V G2 S = 4 V 200 3.5 V 150 y fs (mS) 30 V G2 S = 4 V 3.5 V 3V 3V 20 100 2.5 V 50 2V 10 2.5 V 2V 0 0 1 2 V G1 S (V) 3 0 0 10 20 I D (mA) 30 VDS = 9 to 12 V. Tj = 25 °C. VDS = 9 to 12 V. Tj = 25 °C. Fig.8 Gate 1 current as a function of gate 1 voltage; typical values. Fig.9 Forward transfer admittance as a function of drain current; typical values. 1995 Apr 25 6 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR handbook, halfpage 16 MLD163 MLD164 handbook, halfpage 20 ID (mA) 12 ID (mA) 15 R G1 = 100 kΩ 147 kΩ 180 kΩ 205 kΩ 8 10 249 kΩ 301 kΩ 402 kΩ 511 kΩ 4 5 0 0 20 40 60 I G1 (µA) 80 0 0 4 8 12 V GG = V DS (V) 16 VDS = 9 to 12 V. VG2-S = 4 V. Tj = 25 °C. VG2-S = 4 V. RG1 connected to VGG. Tj = 25 °C. Fig.10 Drain current as a function of gate 1 current; typical values. Fig.11 Drain current as a function of gate 1 supply voltage (= VGG) and drain supply voltage; typical values; see Fig.26. handbook, halfpage 12 MLD165 handbook, halfpage 12 MLD166 ID (mA) 8 ID (mA) 8 4 4 0 0 2 4 6 8 10 V GG (V) 0 0 4 8 V GG (V) 12 VDS = 9 V; VG2-S = 4 V. RG1 = 180 kΩ (connected to VGG); Tj = 25 °C. VDS = 12 V; VG2-S = 4 V. RG1 = 250 kΩ (connected to VGG); Tj = 25 °C. Fig.12 Drain current as a function of gate 1 voltage (= VGG); typical values; see Fig.26. 1995 Apr 25 7 Fig.13 Drain current as a function of gate 1 voltage (= VGG); typical values; see Fig.26. Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR handbook, halfpage 50 MLD167 I G1 (µA) 40 handbook, halfpage 50 MLD168 V GG = 9 V 8V 7V I G1 (µA) 40 V GG = 12 V 11 V 10 V 30 6V 20 5V 4V 10 30 9V 8V 7V 20 10 0 0 2 4 V G2 S (V) 6 0 0 2 4 V G2 S (V) 6 VDS = 9 V. RG1 = 180 kΩ (connected to VGG); Tj = 25 °C. VDS = 12 V. RG1 = 250 kΩ (connected to VGG); Tj = 25 °C. Fig.14 Gate 1 current as a function of gate 2 voltage; typical values. Fig.15 Gate 1 current as a function of gate 2 voltage; typical values. MLD169 MLD170 handbook, halfpage 16 handbook, halfpage 16 ID (mA) 12 V GG = 9 V 8V 7V 6V 8 5V 4V ID (mA) 12 V GG = 12 V 11 V 10 V 9V 8V 7V 8 4 4 0 0 2 4 V G2 S (V) 6 0 0 2 4 V G2 S (V) 6 VDS = 9 V. RG1 = 180 kΩ (connected to VGG); Tj = 25 °C. VDS = 12 V. RG1 = 250 kΩ (connected to VGG); Tj = 25 °C. Fig.16 Drain current as a function of the gate 2 voltage; typical values; see Fig.26. Fig.17 Drain current as a function of the gate 2 voltage; typical values; see Fig.26. 1995 Apr 25 8 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR 10 2 handbook, halfpage y is (mS) 10 MLD181 10 3 y rs (µS) 10 2 MLD182 10 3 ϕ rs (deg) ϕ rs 10 2 b is 1 g is y rs 10 10 10 1 10 102 f (MHz) 10 3 1 10 1 102 f (MHz) 10 3 VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.18 Input admittance as a function of frequency; typical values. Fig.19 Reverse transfer admittance and phase as a function of frequency; typical values. 10 2 MLD183 10 2 MLD184 10 handbook, halfpage yos (mS) bos 1 y fs (mS) y fs ϕ fs (deg) 10 ϕ fs 10 10 1 gos 1 10 1 102 f (MHz) 10 3 10 2 10 102 f (MHz) 10 3 VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.20 Forward transfer admittance and phase as a function of frequency; typical values. Fig.21 Output admittance as a function of frequency; typical values. 1995 Apr 25 9 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR 10 2 handbook, halfpage y is (mS) 10 MLD185 10 3 y rs (µS) 10 2 MLD186 10 3 ϕ rs (deg) ϕ rs 10 2 b is y rs 10 10 1 g is 10 1 10 102 f (MHz) 10 3 1 10 1 102 f (MHz) 10 3 VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.22 Input admittance as a function of frequency; typical values. Fig.23 Reverse transfer admittance and phase as a function of frequency; typical values. 10 2 MLD187 10 2 MLD188 handbook, halfpage 10 y fs (mS) y fs ϕ fs (deg) yos (mS) 1 bos 10 ϕ fs 10 10 1 gos 1 10 102 f (MHz) 10 3 10 2 10 1 102 f (MHz) 10 3 VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.24 Forward transfer admittance and phase as a function of frequency; typical values. Fig.25 Output admittance as a function of frequency; typical values. 1995 Apr 25 10 Philips Semiconductors Product specification Dual-gate MOS-FET BF1100WR handbook, full pagewidth VAGC R1 10 k Ω C1 4.7 nF C3 12 pF C2 R GEN 50 Ω VI R2 50 Ω 4.7 nF DUT RG L1 ≈ 450 nH C4 4.7 nF RL 50 Ω VGG V DS MGC420 For VGG = VDS = 9 V, RG = 180 kΩ. For VGG = VDS = 12 V, RG = 250 kΩ. Fig.26 Cross-modulation test circuit. 1995 Apr 25 11 Philips Semiconductors Product specification Dual-gate MOS-FET Table 1 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 2 Scattering parameters: VDS = 9 V; VG2-S = 4 V; ID = 10 mA s11 MAGNITUDE (ratio) 0.985 0.981 0.975 0.965 0.947 0.927 0.913 0.890 0.869 0.845 0.823 ANGLE (deg) −3.9 −7.3 −14.4 −21.6 −28.3 −34.9 −41.7 −47.9 −54.0 −59.7 −65.4 s21 MAGNITUDE (ratio) 2.618 2.602 2.577 2.555 2.513 2.449 2.339 2.361 2.302 2.228 2.167 ANGLE (deg) 175.1 170.5 160.7 151.6 141.8 133.4 124.6 115.4 106.4 97.6 89.6 s12 MAGNITUDE (ratio) 0.001 0.001 0.002 0.002 0.003 0.003 0.003 0.003 0.003 0.003 0.003 ANGLE (deg) 137.9 80.4 74.0 79.3 80.5 82.8 78.9 80.6 93.9 104.8 129.3 BF1100WR s22 MAGNITUDE (ratio) 1.000 0.999 0.995 0.994 0.992 0.988 0.984 0.982 0.979 0.976 0.974 ANGLE (deg) −1.9 −4.0 −7.6 −11.3 −15.0 −18.5 −22.0 −25.3 −28.8 −32.1 −35.5 Noise data: VDS = 9 V; VG2-S = 4 V; ID = 10 mA f (MHz) 800 Fmin (dB) 2.00 Γopt (ratio) 0.67 (deg) 43.9 rn 0.89 Table 3 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 4 Scattering parameters: VDS = 12 V; VG2-S = 4 V; ID = 10 mA s11 MAGNITUDE (ratio) 0.985 0.980 0.973 0.962 0.946 0.929 0.912 0.895 0.868 0.845 0.823 ANGLE (deg) −3.7 −7.4 −14.6 −21.5 −28.5 −35.0 −41.6 −47.8 −53.8 −59.8 −65.7 s21 MAGNITUDE (ratio) 2.576 2.563 2.541 2.519 2.479 2.419 2.373 2.336 2.284 2.213 2.160 ANGLE (deg) 175.3 170.9 161.6 152.9 143.5 135.5 127.2 118.7 110.0 101.6 94.1 s12 MAGNITUDE (ratio) 0.000 0.001 0.002 0.002 0.003 0.003 0.003 0.003 0.003 0.003 0.003 ANGLE (deg) 125.0 111.2 83.0 85.2 79.4 78.2 80.0 83.4 91.3 95.9 112.2 s22 MAGNITUDE (ratio) 1.000 1.000 0.997 0.996 0.995 0.991 0.989 0.987 0.985 0.983 0.981 ANGLE (deg) −1.6 −3.3 −6.4 −9.3 −12.4 −15.3 −18.1 −20.9 −23.7 −26.5 −29.3 Noise data: VDS = 12 V; VG2-S = 4 V; ID = 10 mA f (MHz) 800 Fmin (dB) 2.00 Γopt (ratio) 0.66 12 (deg) 43.3 rn 0.97 1995 Apr 25 Philips Semiconductors Product specification Dual-gate MOS-FET PACKAGE OUTLINE BF1100WR 1.00 max 0.2 M A 0.2 M B 0.4 0.2 0.1 max 0.2 A 3 4 2.2 2.0 1.35 1.15 2 1 0.7 0.5 1.4 1.2 2.2 1.8 B 0.3 0.1 0.25 0.10 MSB367 Dimensions in mm. Fig.27 SOT343R. 1995 Apr 25 13 Philips Semiconductors Product specification Dual-gate MOS-FET DEFINITIONS Data Sheet Status Objective specification Preliminary specification Product specification Limiting values BF1100WR This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Apr 25 14