BF1102

DISCRETE SEMICONDUCTORS DATA SHEET ook, halfpage MBD128 BF1102 Dual N-channel dual gate MOS-FET Preliminary specification 1999 Jul 08 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET FEATURES • Two low noise gain controlled amplifiers in a single package • Specially designed for 5 V applications • Superior cross-modulation performance during AGC • High forward transfer admittance • High forward transfer admittance to input capacitance ratio. APPLICATIONS • Gain controlled low noise amplifier for VHF and UHF applications such as television tuners and professional communications equipment. DESCRIPTION The BF1102 is a combination of two equal dual gate MOS-FETs with shared source and gate 2 leads. The source and substrate are interconnected. An internal bias circuit enables DC stabilization and a very good cross-modulation performance at 5 V supply voltage. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT363 micro-miniature plastic package. handbook, halfpage BF1102 PINNING - SOT363 PIN 1 2 3 4 5 6 gate 1 (1) gate 2 (1,2) drain (1) drain (2) source (1,2) gate 1 (2) DESCRIPTION g2 (1, 2) 6 5 4 g1 (1) AMP1 d (1) g1 (2) 1 2 3 Marking code: W1. AMP2 d (2) s (1, 2) MBL029 Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. − − Ts ≤ 102 °C; note 1 ID = 15 mA ID = 15 mA f = 1 MHz f = 800 MHz − − − − − − TYP. − − − 43 2.8 30 − − − MAX. UNIT Per MOS-FET unless otherwise specified VDS ID Ptot yfs Cig1-s Crss F Xmod Tj Note 1. Ts is the temperature at the soldering point of the source lead. CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. drain-source voltage drain current (DC) total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation operating junction temperature 7 40 200 − − − 2.8 − 150 V mA mW mS pF fF dB dBµV °C input level for k = 1% at 40 dB AGC 100 1999 Jul 08 2 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS − − − − Ts ≤ 102 °C − −65 − MIN. BF1102 MAX. UNIT Per MOS-FET unless otherwise specified VDS ID IG1 IG2 Ptot Tstg Tj drain-source voltage drain current (DC) gate 1 current gate 2 current total power dissipation storage temperature operating junction temperature 7 40 ±10 ±10 200 +150 +150 V mA mA mA mW °C °C THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER thermal resistance from junction to soldering point VALUE 240 UNIT K/W handbook, halfpage 250 Ptot (mW) 200 MGS359 150 100 50 0 0 50 100 150 Ts (°C) 200 Fig.2 Power derating curve. 1999 Jul 08 3 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET STATIC CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS VG1-S = VG2-S = 0; ID = 10 µA VGS = VDS = 0; IG1-S = 10 mA VGS = VDS = 0; IG2-S = 5 mA VG2-S = VDS = 0; IS-G1 = −10 mA VG1-S = VDS = 0; IS-G2 = −10 mA VDS = 5 V; VG2-S = 4 V; ID = 20 µA VDS = 5 V; VG1-S = 4 V; ID = 20 µA VG1-S = 5 V; VG2-S = VDS = 0 VG2-S = 5 V; VG1-S = VDS = 0 MIN. BF1102 MAX. − 15 15 1.5 1.5 1 1.2 20 50 20 UNIT Per MOS-FET unless otherwise specified V(BR)DSS V(BR)G1-SS V(BR)G2-SS V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-S IG2-S Notes 1. RG1 connects gate 1 to VGG = 5 V. DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified. SYMBOL yfs Cig1-ss Cig2-ss Coss Crss F Xmod PARAMETER Tj = 25 °C f = 1 MHz f = 1 MHz f = 1 MHz f = 800 MHz; YS = YS opt input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; (note 2) input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; (note 2) Notes 1. Not used MOS-FET: VG1-S = 0; VDS = 0. 2. Measured in test circuit of Fig.17. CONDITIONS MIN. TYP. MAX. UNIT drain-source breakdown voltage gate-source breakdown voltage gate-source breakdown voltage forward source-gate voltage forward source-gate voltage gate-source threshold voltage gate-source threshold voltage drain-source current gate cut-off current gate cut-off current 7 6 6 0.5 0.5 0.3 0.3 − − V V V V V V V mA nA nA VG2-S = 4 V; VDS = 5 V; RG = 120 kΩ; note 1 12 Per MOS-FET unless otherwise specified (note 1) forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance noise figure cross-modulation 36 2 − − − − 85 100 43 2.8 − 1.6 30 2 − − 50 3.6 7 2.5 50 2.8 − − mS pF pF pF fF dB dBµV dBµV reverse transfer capacitance f = 1 MHz 1999 Jul 08 4 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET ALL GRAPHS FOR ONE MOS-FET BF1102 handbook, halfpage 30 MGS360 VG2-S = 4 V 3.5 V 3V 2.5 V handbook, halfpage 30 MGS361 ID (mA) 20 ID (mA) 2V 20 VG1-S = 1.5 V 1.4 V 1.3 V 1.2 V 10 1.5 V 10 1.1 V 1V 0 0 0.4 0.8 1.2 1.6 1V 2.0 2.4 VG1-S (V) 0 0 2 4 6 8 10 VDS (V) VDS = 5 V. Tj = 25 °C. VG2-S = 4 V. Tj = 25 °C. Fig.3 Transfer characteristics; typical values. Fig.4 Output characteristics; typical values. handbook, halfpage 160 MGS362 IG1 (µA) 120 VG2-S = 4 V 3.5 V handbook, halfpage 50 |yfs | 40 MGS363 VG2-S = 4 V 3.5 V 3V (mS) 3V 30 80 2.5 V 20 40 2V 10 2V 0 0 0.5 1 1.5 2 2.5 VG1-S (V) 2.5 V 0 0 10 20 ID (mA) 30 VDS = 5 V. Tj = 25 °C. VDS = 5 V. T j = 25 °C. Fig.5 Gate 1 current as a function of gate 1 voltage; typical values. Fig.6 Forward transfer admittance as a function of drain current; typical values. 1999 Jul 08 5 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 handbook, halfpage 25 ID (mA) 20 MGS364 handbook, halfpage 15 MGS365 ID (mA) 10 15 10 5 5 0 0 20 40 I G1 (µA) 60 0 0 1 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. R G1 = 120 k Ω (connected to VGG ); see Fig.17. Fig.7 Drain current as a function of gate 1 current; typical values. Fig.8 Drain current as a function of gate 1 supply voltage (= VGG); typical values. handbook, halfpage 30 MGS366 MGS367 RG1 = 47 kΩ 68 kΩ 82 kΩ 100 kΩ 120 kΩ 150 kΩ 180 kΩ 220 kΩ handbook, halfpage 20 ID (mA) ID (mA) VG1-S = 5 V 4.5 V 4V 3.5 V 16 20 12 3V 8 10 4 0 0 2 4 6 8 10 VGG = VDS (V) 0 0 2 4 VG2-S (V) 6 VG2-S = 4 V; Tj = 25 °C. R G1 connected to VGG; see Fig.17. VDS = 5 V; Tj = 25 °C. R G1 = 120 k Ω (connected to VGG ); see Fig.17. Fig.9 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values. Fig.10 Drain current as a function of gate 2 voltage; typical values. 1999 Jul 08 6 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 handbook, halfpage 40 MGS368 handbook, halfpage 120 MGS369 I G1 (µA) 30 VG1-S = 5 V 4.5 V 4V Vunw (dB µV) 110 20 3.5 V 3V 100 10 90 0 0 2 4 VG2-S (V) 6 80 0 20 40 60 gain reduction (dB) VDS = 5 V; VGG = 5 V; fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C; VDS = 5 V; Tj = 25 °C. R G1 = 120 k Ω (connected to VGG); see Fig.17. R G1 = 120 k Ω (connected to VGG ); see Fig.17. Fig.11 Gate 1 current as a function of gate 2 voltage; typical values. Fig.12 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values. 1999 Jul 08 7 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 102 handbook, halfpage yis (mS) MGS370 103 handbook, halfpage |yrs | (µS) 102 ϕ rs |yrs| MGS371 103 −ϕ rs (deg) 102 10 bis 1 g is 10 10 10 − 1 10 102 f (MHz) 103 1 10 102 f (MHz) 1 103 VDS = 5 V; VG2 = 4 V. I D = 15 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 °C. Fig.13 Input admittance as a function of frequency; typical values. Fig.14 Reverse transfer admittance and phase as a function of frequency; typical values. 102 handbook, halfpage |yfs | (mS) |y fs| MGS372 102 − ϕ fs (deg) handbook, halfpage 10 MGS373 yos (mS) ϕ fs 10 10 1 bos g os 1 10 102 f (MHz) 1 103 10 − 1 10 102 f (MHz) 103 VDS = 5 V; VG2 = 4 V. I D = 15 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 °C. Fig.15 Forward transfer admittance and phase as a function of frequency; typical values. Fig.16 Output admittance as a function of frequency; typical values. 1999 Jul 08 8 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET BF1102 handbook, full pagewidth VAGC R1 10 kΩ C1 4.7 nF C3 4.7 nF C2 RGEN 50 Ω VI R2 50 Ω 4.7 nF RG1 DUT ≈ 2.2 µH C4 4.7 nF L1 RL 50 Ω VGG VDS MGS315 Fig.17 Cross-modulation test set-up (for one MOS-FET). 1999 Jul 08 9 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET PACKAGE OUTLINE BF1102 Plastic surface mounted package; 6 leads SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC EIAJ SC-88 EUROPEAN PROJECTION ISSUE DATE 97-02-28 1999 Jul 08 10 Philips Semiconductors Preliminary specification Dual N-channel dual gate MOS-FET DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values BF1102 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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