BF1204

DISCRETE SEMICONDUCTORS DATA SHEET andbook, halfpage MBD128 BF1204 Dual N-channel dual gate MOS-FET Product specification Supersedes data of 2000 Nov 13 2001 Apr 25 Philips Semiconductors Product specification Dual N-channel dual gate MOS-FET FEATURES • Two low noise gain controlled amplifiers in a single package • Superior cross-modulation performance during AGC • High forward transfer admittance • High forward transfer admittance to input capacitance ratio. APPLICATIONS • Gain controlled low noise amplifiers for VHF and UHF applications with 3 to 9 V supply voltage, such as digital and analog television tuners and professional communications equipment. DESCRIPTION The BF1204 is a combination of two equal dual gate MOS-FET amplifiers with shared source and gate 2 leads. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross-modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT363 micro-miniature plastic package. PINNING - SOT363 PIN 1 2 3 4 5 6 gate 1 (a) gate 2 gate 1 (b) drain (b) source drain (a) BF1204 DESCRIPTION handbook, halfpage 6 5 4 d (a) s d (b) AMP a AMP b 1 2 3 g1 (a) g2 g1 (b) MBL252 Top view Marking code: L3- Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. − − Ts ≤ 102 °C; note 1 ID = 12 mA; f = 1 MHz ID = 12 mA; f = 1 MHz f = 1 MHz f = 800 MHz − 25 − − − − TYP. − − − 30 1.7 15 1.1 105 − MAX. UNIT Per MOS-FET; unless otherwise specified VDS ID Ptot yfs Cig1-s Crss NF Xmod Tj Note 1. Ts is the temperature at the soldering point of the source lead. CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. 2001 Apr 25 2 drain-source voltage drain current (DC) total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation operating junction temperature 10 30 200 40 2.2 − 1.8 − 150 V mA mW mS pF fF dB dBµV °C input level for k = 1% at 40 dB AGC 100 Philips Semiconductors Product specification Dual N-channel dual gate MOS-FET LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS − − − − Ts ≤ 102 °C − −65 − MIN. BF1204 MAX. UNIT Per MOS-FET; unless otherwise specified VDS ID IG1 IG2 Ptot Tstg Tj drain-source voltage drain current (DC) gate 1 current gate 2 current total power dissipation storage temperature operating junction temperature 10 30 ±10 ±10 200 +150 150 V mA mA mA mW °C °C THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER thermal resistance from junction to soldering point VALUE 240 UNIT K/W handbook, halfpage 250 MGS359 Ptot (mW) 200 150 100 50 0 0 50 100 150 Ts (°C) 200 Fig.2 Power derating curve. 2001 Apr 25 3 Philips Semiconductors Product specification Dual N-channel dual gate MOS-FET STATIC CHARACTERISTICS Tj = 25 °C; per MOS-FET; unless otherwise specified. SYMBOL V(BR)DSS PARAMETER CONDITIONS MIN. 10 6 6 0.5 0.5 0.3 0.3 8 − − BF1204 MAX. − 10 10 1.5 1.5 1 1.2 16 50 20 UNIT V V V V V V V mA nA nA drain-source breakdown voltage VG1-S = VG2-S = 0; ID = 10 µA V(BR)G1-SS gate-source breakdown voltage VGS = VDS = 0; IG1-S = 10 mA V(BR)G2-SS gate-source breakdown voltage VGS = VDS = 0; IG2-S = 10 mA V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-S IG2-S Note 1. RG1 connects gate 1 to VGG = 5 V. DYNAMIC CHARACTERISTICS forward source-gate voltage forward source-gate voltage gate-source threshold voltage gate-source threshold voltage drain-source current gate cut-off current gate cut-off current VG2-S = VDS = 0; IS-G1 = 10 mA VG1-S = VDS = 0; IS-G2 = 10 mA VDS = 5 V; VG2-S = 4 V; ID = 100 µA VDS = 5 V; VG1-S = 4 V; ID = 100 µA VG2-S = 4 V; VDS = 5 V; RG = 120 kΩ; note 1 VG1-S = 5 V; VG2-S = VDS = 0 VG2-S = 4 V; VG1-S = VDS = 0 Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; per MOS-FET (1); unless otherwise specified. SYMBOL yfs Cig1-ss Cig2-ss Coss Crss Gtr PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance reverse transfer capacitance power gain Tj = 25 °C f = 1 MHz f = 1 MHz f = 1 MHz f = 1 MHz f = 200 MHz; GS = 2 mS; BS = BS(opt); GL = 0.5 mS; BL = BL(opt); note 1 f = 400 MHz; GS = 2 mS; BS = BS(opt); GL = 1 mS; BL = BL(opt); note 1 CONDITIONS MIN. 25 − − − − 30 26 TYP. 30 1.7 3.3 0.85 15 34 30 25 9 0.9 1.1 − 92 105 MAX. 40 2.2 − − − 38 34 29 11 1.5 1.8 − − − UNIT mS pF pF pF fF dB dB dB dB dB dB dBµV dBµV dBµV f = 800 MHz; GS = 3.3 mS; BS = BS(opt); 21 GL = 1 mS; BL = BL(opt); note 1 NF noise figure f = 10.7 MHz; GS = 20 mS; BS = 0 f = 400 MHz; YS = YS(opt) f = 800 MHz; YS = YS(opt) Xmod cross-modulation input level for k = 1% at 0 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 input level for k = 1% at 10 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 input level for k = 1% at 40 dB AGC; fw = 50 MHz; funw = 60 MHz; note 2 Notes 1. For the MOS-FET not in use: VG1-S = 0; VDS = 0. 2. Measured in Fig.19 test circuit. 2001 Apr 25 4 − − − 90 − 100 Philips Semiconductors Product specification Dual N-channel dual gate MOS-FET ALL GRAPHS FOR ONE MOS-FET MCD952 BF1204 handbook, halfpage 20 ID (mA) VG2-S = 4 V 3.5 V 3V 2.5 V handbook, halfpage 24 MCD953 16 2V ID (mA) 16 VG1-S = 1.5 V 1.4 V 1.3 V 12 8 1.5 V 8 1.2 V 1.1 V 1V 4 1V 0 0 0.4 0.8 1.2 1.6 2 VG1-S (V) 0.9 V 0 0 2 4 6 8 10 VDS (V) VDS = 5 V. Tj = 25 °C. VG2-S = 4 V. Tj = 25 °C. Fig.3 Transfer characteristics; typical values. Fig.4 Output characteristics; typical values. handbook, halfpage 100 MCD954 IG1 (µA) VG2-S = 4 V 3.5 V 3V handbook, halfpage 40 MCD955 80 yfs (mS) 30 3.5 V VG2-S = 4 V 3V 60 2.5 V 20 2.5 V 40 2V 10 20 1.5 V 0 0 0.5 1 1.5 1V 2 2.5 VG1-S (V) 0 0 4 8 12 16 20 ID (mA) 2V VDS = 5 V. Tj = 25 °C. VDS = 5 V. Tj = 25 °C. Fig.5 Gate 1 current as a function of gate 1 voltage; typical values. Fig.6 Forward transfer admittance as a function of drain current; typical values. 2001 Apr 25 5 Philips Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1204 handbook, halfpage 20 MCD956 ID (mA) handbook, halfpage 16 MCD957 16 ID (mA) 12 12 8 8 4 4 0 0 10 20 30 40 50 IG1 (µA) 0 0 1 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V. Tj = 25 °C. VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. RG1 = 120 kΩ (connected to VGG); see Fig.19. Fig.7 Drain current as a function of gate 1 current; typical values. Fig.8 Drain current as a function of gate 1 supply voltage (= VGG); typical values. handbook, halfpage 20 MCD958 ID (mA) RG1 = 68 kΩ 82 kΩ 100 kΩ 120 kΩ 150 kΩ 180 kΩ handbook, halfpage 16 MCD959 16 ID (mA) 12 VGG = 5 V 4.5 V 4V 3.5 V 12 8 3V 8 220 kΩ 4 4 0 0 2 4 6 VGG = VDS (V) 0 0 2 4 VG2-S (V) 6 VG2-S = 4 V; Tj = 25 °C. RG1 connected to VGG; see Fig.19. VDS = 5 V; Tj = 25 °C. RG1 = 120 kΩ (connected to VGG); see Fig.19. Fig.9 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values. Fig.10 Drain current as a function of gate 2 voltage; typical values. 2001 Apr 25 6 Philips Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1204 handbook, halfpage 40 MCD960 handbook, halfpage gain 0 MCD961 IG1 (µA) 30 VGG = 5 V 4.5 V 4V reduction (dB) −10 −20 20 3.5 V 3V −30 10 −40 0 0 2 4 VG2-S (V) 6 −50 0 1 2 3 VAGC (V) 4 VDS = 5 V; Tj = 25 °C. RG1 = 120 kΩ (connected to VGG); see Fig.19. VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ; f = 50 MHz; Tamb = 25 °C. Fig.11 Gate 1 current as a function of gate 2 voltage; typical values. Fig.12 Typical gain reduction as a function of AGC voltage; see Fig.19. handbook, halfpage 120 MCD962 handbook, halfpage 16 MCD963 Vunw (dBµV) 110 ID (mA) 12 100 8 90 4 80 0 10 20 30 40 50 gain reduction (dB) 0 0 10 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ; f= 50 MHz; funw = 60 MHz; Tamb = 25 °C. VDS = 5 V; VGG = 5 V; RG1 = 120 kΩ; f = 50 MHz; Tamb = 25 °C. Fig.13 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.19. Fig.14 Drain current as a function of gain reduction; typical values; see Fig.19. 2001 Apr 25 7 Philips Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1204 102 handbook, halfpage Yis (mS) 10 MLD429 103 handbook, halfpage yrs (µS) 102 ϕrs MLD430 −103 ϕrs (deg) −102 bis gis 1 10 yrs −10 10−1 10 102 f (MHz) 103 1 10 102 f (MHz) −1 103 VDS = 5 V; VG2 = 4 V. VDS = 5 V; VG2 = 4 V. Fig.15 Input admittance as a function of frequency; typical values. Fig.16 Reverse transfer admittance and phase as a function of frequency; typical values. 102 handbook, halfpage yfs (mS) MLD431 −102 ϕfs (deg) handbook, halfpage 10 MLD432 yfs Yos (mS) 1 bos 10 ϕfs −10 10−1 gos 1 10 102 f (MHz) −1 103 10−2 10 102 f (MHz) 103 VDS = 5 V; VG2 = 4 V. VDS = 5 V; VG2 = 4 V. Fig.17 Forward transfer admittance and phase as a function of frequency; typical values. Fig.18 Output admittance as a function of frequency; typical values. 2001 Apr 25 8 Philips Semiconductors Product specification Dual N-channel dual gate MOS-FET BF1204 handbook, full pagewidth VAGC R1 10 kΩ C1 4.7 nF C3 4.7 nF C2 RGEN 50 Ω VI R2 50 Ω 4.7 nF RG1 DUT ≈ 2.2 µH C4 4.7 nF L1 RL 50 Ω VGG VDS MGS315 Fig.19 Cross-modulation test set-up (for one MOS-FET). Scattering parameters VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C. f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 s11 MAGNITUDE (ratio) 0.991 0.987 0.981 0.969 0.958 0.939 0.921 0.898 0.874 0.847 0.817 ANGLE (deg) −3.29 −7.12 −14.21 −21.22 −28.14 −35.01 −41.75 −48.51 −54.96 −61.62 −67.84 s21 MAGNITUDE (ratio) 2.95 2.90 2.86 2.83 2.79 2.74 2.68 2.62 2.55 2.49 2.41 ANGLE (deg) 175.78 171.61 163.45 155.11 147.37 139.04 131.35 123.38 115.74 107.84 100.24 s12 MAGNITUDE (ratio) 0.00060 0.00119 0.00234 0.00339 0.00429 0.00508 0.00565 0.00611 0.00646 0.00662 0.00670 ANGLE (deg) 85.25 84.74 80.85 75.77 72.23 68.24 64.97 61.90 57.77 55.04 52.16 s22 MAGNITUDE (ratio) 0.995 0.994 0.992 0.989 0.987 0.983 0.981 0.976 0.973 0.969 0.966 ANGLE (deg) −1.44 −2.90 −5.70 −8.50 −11.25 −13.96 −16.67 −19.36 −22.04 −24.80 −27.45 2001 Apr 25 9 Philips Semiconductors Product specification Dual N-channel dual gate MOS-FET PACKAGE OUTLINE Plastic surface mounted package; 6 leads BF1204 SOT363 D B E A X y HE vMA 6 5 4 Q pin 1 index A A1 1 e1 e 2 bp 3 wM B detail X Lp c 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.30 0.20 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 0.65 HE 2.2 2.0 Lp 0.45 0.15 Q 0.25 0.15 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT363 REFERENCES IEC JEDEC EIAJ SC-88 EUROPEAN PROJECTION ISSUE DATE 97-02-28 2001 Apr 25 10 Philips Semiconductors Product specification Dual N-channel dual gate MOS-FET DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS BF1204 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. 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