BF1212WR

DISCRETE SEMICONDUCTORS DATA SHEET BF1212; BF1212R; BF1212WR N-channel dual-gate MOS-FETs Product specification 2003 Nov 14 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs FEATURES • Short channel transistor with high forward transfer admittance to input capacitance ratio • Low noise gain controlled amplifier • Excellent low frequency noise performance • Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. APPLICATIONS • Gain controlled low noise VHF and UHF amplifiers for 5 V digital and analog television tuner applications. DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1212, BF1212R and BF1212WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. BF1212; BF1212R; BF1212WR PINNING PIN 1 2 3 4 source drain gate 2 gate 1 DESCRIPTION handbook, 2 columns 4 3 1 Top view 2 MSB014 BF1212; marking code: LGp Fig.1 Simplified outline (SOT143B). handbook, 2 columns 3 4 handbook, halfpage 3 4 2 Top view BF1212R; marking code: LKp 1 2 MSB035 1 MSB842 Top view BF1212WR; marking code: ML Fig.2 Simplified outline (SOT143R). Fig.3 Simplified outline (SOT343R). QUICK REFERENCE DATA SYMBOL VDS ID Ptot yfs Cig1-ss Crss F Xmod Tj PARAMETER drain-source voltage drain current total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation junction temperature 2 f = 1 MHz f = 800 MHz input level for k = 1 % at 40 dB AGC CONDITIONS − − − 28 − − − 100 − MIN. − − − 33 1.7 15 1.1 104 − TYP. 6 30 180 43 2.2 30 1.8 − 150 MAX. UNIT V mA mW mS pF fF dB dBµV °C 2003 Nov 14 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME BF1212 BF1212R BF1212WR − − − DESCRIPTION plastic surface mounted package; 4 leads plastic surface mounted package; reverse pinning; 4 leads plastic surface mounted package; reverse pinning; 4 leads VERSION SOT143B SOT143R SOT343R LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDS ID IG1 IG2 Ptot PARAMETER drain-source voltage drain current (DC) gate 1 current gate 2 current total power dissipation BF1212; BF1212R BF1212WR Tstg Tj Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s BF1212; BF1212R BF1212WR PARAMETER thermal resistance from junction to soldering point 185 155 K/W K/W VALUE UNIT storage temperature junction temperature Ts ≤ 116 °C; note 1 Ts ≤ 122 °C; note 1 − − −65 − 180 180 +150 150 mW mW °C °C CONDITIONS − − − − MIN. 6 30 ±10 ±10 MAX. V mA mA mA UNIT 2003 Nov 14 3 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR handbook, halfpage 250 MDB828 Ptot (mW) 200 150 (2) (1) 100 50 0 0 50 100 150 Ts (°C) 200 (1) BF1212WR. (2) BF1212; BF1212R. Fig.4 Power derating curve. STATIC CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL V(BR)DSS PARAMETER drain-source breakdown voltage CONDITIONS VG1-S = VG2-S = 0 V; ID = 10 µA VG2-S = VDS = 0 V; IG1-S = 10 mA VG1-S = VDS = 0 V; IG2-S = 10 mA VG2-S = VDS = 0 V; IS-G1 = 10 mA VG1-S = VDS = 0 V; IS-G2 = 10 mA VG2-S = 4 V; VDS = 5 V; ID = 100 µA VG1-S = 5 V; VDS = 5 V; ID = 100 µA VG2-S = 4 V; VDS = 5 V; RG1 = 150 kΩ; note 1 VG2-S = VDS = 0 V; VG1-S = 5 V VG1-S = VDS = 0 V; VG2-S = 4 V MIN. 6 6 6 0.5 0.5 0.3 0.35 8 − − MAX. − 10 10 1.5 1.5 1.0 1.0 16 50 20 UNIT V V V V V V V mA nA nA V(BR)G1-SS gate 1-source breakdown voltage V(BR)G2-SS gate 2-source breakdown voltage V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-S IG2-S Note 1. RG1 connects G1 to VGG = 5 V. forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage gate 2-source threshold voltage drain-source current gate 1 cut-off current gate 2 cut-off current 2003 Nov 14 4 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified. SYMBOL yfs Cig1-ss Cig2-ss Coss Crss F PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance noise figure f = 1 MHz f = 1 MHz f = 1 MHz f = 11 MHz; GS = 20 mS; BS = 0 f = 400 MHz; YS = YS (opt) f = 800 MHz; YS = YS (opt) Gtr power gain f = 200 MHz; GS = 2 mS; BS = BS (opt); GL = 0.5 mS; BL = BL (opt) f = 400 MHz; GS = 2 mS; BS = BS (opt); GL = 1 mS; BL = BL (opt) f = 800 MHz; GS = 3.3 mS; BS = BS (opt); GL = 1 mS; BL = BL (opt) Xmod cross-modulation input level for k = 1%; fw = 50 MHz; funw = 60 MHz; note 1 at 0 dB AGC at 10 dB AGC at 40 dB AGC Note 1. Measured in test circuit Fig.21. 90 − 100 − 89 104 − − − dBµV dBµV dBµV CONDITIONS pulsed; Tj = 25 °C MIN. 28 − − − − − − − − − − TYP. 33 1.7 1.1 0.9 15 4 0.9 1.1 35 30 25 MAX. 43 2.2 − − 30 − 1.6 1.8 − − − UNIT mS pF pF pF fF dB dB dB dB dB dB reverse transfer capacitance f = 1 MHz 2003 Nov 14 5 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR handbook, halfpage 30 MLE233 (1) (4) (2) (3) (5) handbook, halfpage 32 MLE234 (1) (2) (3) (4) ID (mA) 20 ID (mA) 24 (6) 16 (5) (6) 10 8 (7) (7) (8) (9) 0 0 0.5 1 1.5 2 VG1-S (V) (1) (2) (3) (4) VG2-S = 4 V. VG2-S = 3.5 V. VG2-S = 3 V. VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. VDS = 5 V. Tj = 25 °C. (1) (2) (3) (4) (5) 2.5 0 0 2 4 VDS (V) 6 VG1-S = 1.6 V. VG1-S = 1.5 V. VG1-S = 1.4 V. VG1-S = 1.3 V. VG1-S = 1.2 V. (6) VG1-S = 1.1 V. (7) VG1-S = 1.0 V. (8) VG1-S = 0.9 V. (9) VG1-S = 0.8 V. VG2-S = 4 V. Tj = 25 °C. Fig.5 Transfer characteristics; typical values. Fig.6 Output characteristics; typical values. handbook, halfpage (µA) 100 IG1 MLE235 (1) (2) (3) handbook, halfpage 40 MLE236 (3) (2) (1) yfs (mS) 30 (4) 80 (4) (5) 60 20 40 (5) (6) 10 20 (6) (7) (7) 0 0 0.5 1 1.5 2 VG1-S (V) VDS = 5 V. Tj = 25 °C. 0 0 4 8 12 16 20 ID (mA) VDS = 5 V. Tj = 25 °C. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. Fig.7 Gate 1 current as a function of gate 1 voltage; typical values. Fig.8 Forward transfer admittance as a function of drain current; typical values. 2003 Nov 14 6 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR handbook, halfpage 24 MLE237 handbook, halfpage 16 MLE238 ID (mA) 16 ID (mA) 12 8 8 4 0 0 10 20 30 40 50 IG1 (µA) 0 0 1 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V. Tj = 25 °C. VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. RG1 = 150 kΩ (connected to VGG); see Fig.21. Fig.9 Drain current as a function of gate 1 current; typical values. Fig.10 Drain current as a function of gate 1 supply voltage; typical values. handbook, halfpage 20 MLE239 ID (mA) 16 (1) (2) (3) (4) (5) handbook, halfpage 16 MLE240 ID (mA) 12 (1) (2) (3) (4) (5) 12 (6) (7) (8) 8 8 4 4 0 0 2 4 6 VGG = VDS (V) VG2-S = 4 V; Tj = 25 °C. RG1 connected to VGG; see Fig.21. 0 0 2 4 VG2-S (V) 6 (1) RG1 = 47 kΩ. (2) RG1 = 56 kΩ. (3) RG1 = 82 kΩ. (4) RG1 = 100 kΩ. (5) (6) (7) (8) RG1 = 120 kΩ. RG1 = 150 kΩ. RG1 = 180 kΩ. RG1 = 220 kΩ. (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. (4) VGG = 3.5 V. (5) VGG = 3 V. VDS = 5 V; Tj = 25 °C. RG1 = 150 kΩ (connected to VGG); see Fig.21. Fig.11 Drain current as a function of gate 1 and drain supply voltage; typical values. Fig.12 Drain current as a function of gate 2 voltage; typical values. 2003 Nov 14 7 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR handbook, halfpage 30 MLE241 handbook, halfpage 0 MLE242 IG1 (µA) 20 (1) (2) (3) (4) (5) gain reduction (dB) −20 10 −40 0 0 2 4 VG2-S (V) 6 −60 0 1 2 3 VAGC (V) 4 (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. (4) VGG = 3.5 V. (5) VGG = 3 V. VDS = 5 V; Tj = 25 °C. RG1 = 150 kΩ (connected to VGG); see Fig.21. VDS = 5 V; VGG = 5 V; RG1 = 150 kΩ (connected to VGG); see Fig.21; f = 50 MHz; Tamb = 25 °C. Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. Fig.14 Typical gain reduction as a function of AGC voltage. handbook, halfpage 120 MLE243 handbook, halfpage 16 MLE244 Vunw (dBµV) 110 ID (mA) 12 100 8 90 4 80 0 10 20 30 40 50 gain reduction (dB) 0 0 10 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; RG1 = 150 kΩ (connected to VGG); see Fig.21; f= 50 MHz; funw = 60 MHz; Tamb = 25 °C. VDS = 5 V; VGG = 5 V; RG1 = 150 kΩ (connected to VGG); see Fig.21; f= 50 MHz; Tamb = 25 °C. Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values. Fig.16 Drain current as a function of gain reduction; typical values. 2003 Nov 14 8 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR 102 handbook, halfpage yis (mS) 10 MLE245 103 handbook, halfpage yrs (µS) 102 ϕrs MLE246 −103 ϕrs (deg) −102 bis gis 1 10 yrs −10 10−1 10 102 f (MHz) 103 1 10 102 f (MHz) −1 103 VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 °C. Fig.17 Input admittance as a function of frequency; typical values. Fig.18 Reverse transfer admittance and phase as functions of frequency; typical values. 102 handbook, halfpage MLE247 −102 handbook, halfpage 10 MLE248 yfs (mS) yfs ϕfs (deg) yos (mS) 10 −10 1 bos ϕfs gos 1 10 102 f (MHz) 103 −1 10−1 10 102 f (MHz) 103 VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V. ID = 12 mA; Tamb = 25 °C. Fig.19 Forward transfer admittance and phase as functions of frequency; typical values. Fig.20 Output admittance as a function of frequency; typical values. 2003 Nov 14 9 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR handbook, full pagewidth VAGC R1 10 kΩ C1 4.7 nF C3 4.7 nF C2 RGEN 50 Ω VI R2 50 Ω 4.7 nF RG1 DUT ≈ 2.2 µH C4 4.7 nF L1 RL 50 Ω VGG VDS MGS315 Fig.21 Cross-modulation test set-up. Table 1 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 2 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C s11 MAGNITUDE (ratio) 0.990 0.988 0.983 0.974 0.969 0.958 0.947 0.936 0.924 0.910 0.896 ANGLE (deg) −3.39 −6.76 −13.40 −19.86 −26.46 −32.73 −38.83 −44.75 −50.51 −56.18 −61.64 s21 MAGNITUDE (ratio) 3.288 3.280 3.261 3.218 3.205 3.141 3.086 3.017 2.949 2.870 2.785 ANGLE (deg) 176.5 173.0 166.1 159.0 152.6 145.9 139.5 133.1 126.9 120.5 114.7 s12 MAGNITUDE (ratio) 0.0005 0.0011 0.0021 0.0030 0.0039 0.0045 0.0049 0.0051 0.0051 0.0049 0.0045 ANGLE (deg) 86.9 85.6 81.2 77.5 74.6 72.4 70.9 69.5 69.9 69.8 72.7 s22 MAGNITUDE (ratio) 0.990 0.990 0.991 0.991 0.994 0.994 0.993 0.991 0.981 0.984 0.980 ANGLE (deg) −1.66 −3.30 −6.62 −9.92 −13.30 −16.56 −19.77 −22.78 −25.77 −28.72 −31.77 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C f (MHz) 400 800 Fmin (dB) 0.9 1.1 Γopt (ratio) 0.695 0.634 (deg) 13.87 30.30 Rn (Ω) 28.5 32.85 2003 Nov 14 10 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs PACKAGE OUTLINES Plastic surface mounted package; 4 leads BF1212; BF1212R; BF1212WR SOT143B D B E A X y vMA HE e bp wM B 4 3 Q A A1 c 1 b1 e1 2 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT143B REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-02-28 2003 Nov 14 11 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR Plastic surface mounted package; reverse pinning; 4 leads SOT143R D B E A X y vMA HE e bp wM B 3 4 Q A A1 c 2 b1 e1 1 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.55 0.25 Q 0.45 0.25 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT143R REFERENCES IEC JEDEC EIAJ SC-61B EUROPEAN PROJECTION ISSUE DATE 97-03-10 99-09-13 2003 Nov 14 12 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs BF1212; BF1212R; BF1212WR Plastic surface mounted package; reverse pinning; 4 leads SOT343R D B E A X y HE e vMA 3 4 Q A A1 c 2 wM B bp e1 b1 1 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.4 0.3 b1 0.7 0.5 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 1.15 HE 2.2 2.0 Lp 0.45 0.15 Q 0.23 0.13 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT343R REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-21 2003 Nov 14 13 Philips Semiconductors Product specification N-channel dual-gate MOS-FETs DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development BF1212; BF1212R; BF1212WR DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Nov 14 14 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R77/02/pp15 Date of release: 2003 Nov 14 Document order number: 9397 750 12308