BLF0810-180

DISCRETE SEMICONDUCTORS DATA SHEET M3D379 M3D461 BLF0810-180; BLF0810S-180 Base station LDMOS transistors Product specification Supersedes data of 2003 May 09 2003 Jun 12 Philips Semiconductors Product specification Base station LDMOS transistors FEATURES • Typical CDMA IS95 performance at standard settings with a supply voltage of 27 V and IDQ of 1130 mA. Adjacent channel bandwidth is 30 kHz, adjacent channel at ± 750 kHz: – Output power = 30 W – Gain = 16 dB – Efficiency = 27% – ACPR = −46 dBc at 750 kHz and BW = 30 kHz • Easy power control • Excellent ruggedness • High power gain • Excellent thermal stability • Designed for broadband operation (800 to 1000 MHz) • Internally matched for ease of use. PINNING - SOT502A PIN 1 2 3 drain gate source; connected to flange DESCRIPTION BLF0810-180; BLF0810S-180 APPLICATIONS • Common source class-AB operation applications in the 860 to 960 MHz frequency range • CDMA and multicarrier applications. DESCRIPTION 180 W LDMOS power transistor for base station applications at frequencies from 800 to 1000 MHz. PINNING - SOT502B PIN 1 2 3 drain gate source; connected to flange DESCRIPTION handbook, halfpage 1 1 3 2 Top view 3 MBK394 2 Top view MBL105 Fig.1 Simplified outline SOT502A (BLF0810-180). Fig.2 Simplified outline SOT502B (BLF0810S-180). QUICK REFERENCE DATA Typical RF performance at Th = 25 °C in a common source test circuit. MODE OF OPERATION Class-AB (2-tone) CDMA (IS95) f (MHz) f1 = 890.0; f2 = 890.1 890 VDS (V) 27 27 PL (W) 140 (PEP) 30 (AV) Gp (dB) 16 16 ηD (%) 39 27 d3 (dBc) −28 − ACPR 750 (dBc) − −46 2003 Jun 12 2 Philips Semiconductors Product specification Base station LDMOS transistors BLF0810-180; BLF0810S-180 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDS VGS Tstg Tj drain-source voltage gate-source voltage storage temperature junction temperature PARAMETER − − −65 − MIN. MAX. 75 ±15 +150 200 V V C °C UNIT THERMAL CHARACTERISTICS SYMBOL Rth j-c Rth j-hs Notes 1. Thermal resistance is determined under RF operating conditions. 2. Depending on mounting condition in application. CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL V(BR)DSS VGSth IDSS IDSX IGSS gfs RDSon PARAMETER drain-source breakdown voltage gate-source threshold voltage drain-source leakage current on-state drain current gate leakage current forward transconductance drain-source on-state resistance CONDITIONS VGS = 0; ID = 3 mA VDS = 10 V; ID = 300 mA VGS = 0; VDS = 36 V VGS = VGSth + 9 V; VDS = 10 V VGS = ±20 V; VDS = 0 VDS = 10 V; ID = 10 A VGS = 9 V; ID = 10 A MIN. 75 4 − 45 − − − TYP. − − − − − 9 60 MAX. − 5 3 − 1 − − UNIT V V µA A µA S mΩ PARAMETER thermal resistance from junction to case thermal resistance from heatsink to junction CONDITIONS Th = 25 °C, PL = 35 W (AV), note 1 Th = 25 °C, PL = 35 W (AV), note 2 VALUE 0.42 0.62 UNIT K/W K/W 2003 Jun 12 3 Philips Semiconductors Product specification Base station LDMOS transistors APPLICATION INFORMATION RF performance in a common source class-AB circuit. BLF0810-180; BLF0810S-180 VDS = 27 V; IDQ = 1130 mA; f = 890 MHz; Th = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. − − −6 − − − −27 UNIT Mode of operation: 2-tone CW, 100 kHz spacing Gp ηD IRL d3 Gp ηD d3 gain power drain efficiency input return loss third order intermodulation distortion gain power drain efficiency third order intermodulation distortion ruggedness VSWR = 15 : 1 through all phases; PL = 125 W (PEP) PL = 30 W (AV) PL = 30 W (AV) at BW = 30 kHz PL = 125 W (PEP) PL = 90 W (PEP) 15 24 − − − 33 − 16 30 −13 −40 16 37 −32 dB % dB dBc dB % dBc no degradation in output power Mode of operation: CDMA, IS95 (pilot, paging, sync and traffic codes 8 to 13) Gp ηD ACPR 750 gain power drain efficiency adjacent channel power ratio − − − 16 27 −46 − − − dB % dBc 2003 Jun 12 4 Philips Semiconductors Product specification Base station LDMOS transistors BLF0810-180; BLF0810S-180 handbook, halfpage η 50 MDB158 17 gain (dB) 16.5 handbook, halfpage −20 MDB159 (4) (%) 40 d3 (dBc) −30 η(1,2,3) 16 30 (5) 15.5 20 15 (6) −40 (1) −50 14.5 (2) (3) 10 0 0 50 14 100 150 PL (PEP) (W) −60 0 50 100 150 PL (PEP) (W) VDS = 27 V; IDQ = 1.1 A; f1 = 890.0 MHz; f2 = 890.1 MHz. (1) η at Th = −40 °C. (2) η at Th = 20 °C. (3) η at Th = 80 °C. (4) gain at Th = −40 °C. (5) gain at Th = 20 °C. (6) gain at Th = 80 °C. VDS = 27 V; IDQ = 1.1 A; f1 = 890.0 MHz; f2 = 890.1 MHz. (1) Th = −40 °C. (2) Th = 20 °C. (3) Th = 80 °C. Fig.3 2-tone power gain and efficiency as functions of load power at different temperatures. Fig.4 Third order intermodulation distortion as a function of load power at different temperatures. handbook, halfpage −30 MDB160 handbook, halfpage −40 MDB161 d5 (dBc) (3) d7 (dBc) −50 (3) (2) −40 (1) (1) (2) −50 −60 −60 −70 −70 0 50 100 150 PL (PEP) (W) 0 50 100 150 PL (PEP) (W) VDS = 27 V; IDQ = 1.1 A; f1 = 890.0 MHz; f2 = 890.1 MHz. (1) Th = −40 °C. (2) Th = 20 °C. (3) Th = 80 °C. VDS = 27 V; IDQ = 1.1 A; f1 = 890.0 MHz; f2 = 890.1 MHz. (1) Th = −40 °C. (2) Th = 20 °C. (3) Th = 80 °C. Fig.5 Fifth order intermodulation distortion as a function of load power at different temperatures. Fig.6 Seventh order intermodulation distortion as a function of load power at different temperatures. 2003 Jun 12 5 Philips Semiconductors Product specification Base station LDMOS transistors BLF0810-180; BLF0810S-180 handbook, halfpage 20 MDB162 40 handbook, halfpage 0 MDB163 gain (dB) 15 (2) (1) ηD (%) 30 dim (dBc) −20 (3) (1) (2) (5) 10 (4) 20 −40 (4) 5 10 −60 (6) (3) 0 0 50 0 100 150 PL (PEP) (W) −80 0 50 100 150 PL (PEP) (W) VDS = 27 V; f1 = 890.0 MHz; f2 = 890.1 MHz. VDS = 27 V; f1 = 890.0 MHz; f2 = 890.1 MHz. (1) IDQ = 1 A. (2) IDQ = 1.45 A. (3) IDQ = 1 A. (4) IDQ = 1.45 A. (1) d3; IDQ = 1 A. (2) d5; IDQ = 1 A. (3) d7; IDQ = 1 A. (4) d3; IDQ = 1.3 A. (5) d5; IDQ = 1.3 A. (6) d7; IDQ = 1.3 A. Fig.7 Power gain and drain efficiency as functions of peak envelope load power; typical values. Fig.8 Intermodulation distortion as a function of peak envelope load power; typical values. handbook, halfpage −45 ACPR (dBc) −50 −55 −60 −65 MDB164 handbook, halfpage −40 MDB165 ACPR at 750 kHz (2) ACPR (dBc) −50 ACPR at 750 kHz (1) (1) −60 (2) ACPR at 1.98 MHz (4) −70 ACPR at 1.98 MHz (3) (4) −70 −75 40 (3) 41 42 43 44 45 PL (AV) (dBm) −80 0 10 20 30 40 PL (PEP) (W) VDS = 27 V; f = 894 MHz; IDQ = 1.1 A. VDS = 27 V; f = 894 MHz. (1) IDQ = 1 .1A. (2) IDQ = 1.4 A. (3) IDQ = 1.1 A. (4) IDQ = 1.4 A. (1) Th = 20 °C. (2) Th = 80 °C. (3) Th = 20 °C. (4) Th = 80 °C. Fig.9 CDMA IS95 ACPR distortion as a function of average load power and IDQ. Fig.10 CDMA IS95 ACPR distortion as a function of peak envelope load power at different temperatures. 2003 Jun 12 6 Philips Semiconductors Product specification Base station LDMOS transistors BLF0810-180; BLF0810S-180 handbook, halfpage Z 2 MDB166 i (Ω) handbook, halfpage Z 2 MDB167 L (Ω) 1.5 ri 1.5 1 1 RL 0.5 0.5 0 xi −0.5 −1 0.85 0 −0.5 XL 0.9 0.95 f (GHz) 1 −1 0.85 0.9 0.95 f (GHz) 1 Class-AB operation; VDS = 27 V; IDQ = 1125 mA; PL = 35 W. Values comprised for different parameters. Class-AB operation; VDS = 27 V; IDQ = 1125 mA; PL = 35 W. Values comprised for different parameters. Fig.11 Input impedance as a function of frequency (series components); typical values. Fig.12 Load impedance as a function of frequency (series components); typical values. handbook, halfpage drain ZL gate Z IN MGS998 Fig.13 Definition of transistor impedance. 2003 Jun 12 7 Philips Semiconductors Product specification Base station LDMOS transistors BLF0810-180; BLF0810S-180 handbook, full pagewidth C2 Vbias Q1 C3 C4 C6 L9 R1 C7 L5 L10 C15 L12 C17 C9 Vsupply C10 L3 RF in L1 C1 L2 L4 C5 L6 L7 Q2 L11 L14 C13 C18 C11 C12 L13 C16 L15 L16 RF out L8 C8 C14 MDB168 Fig.14 Test circuit for 860 to 900 MHz. 2003 Jun 12 8 Philips Semiconductors Product specification Base station LDMOS transistors BLF0810-180; BLF0810S-180 handbook, full pagewidth BLF0810-180 output Rev C C2 C4 C15 C17 C9 C3 R1 C1 L5 C7 C5 C13 C8 C11 C12 C18 C10 C6 BLF0810-180 input Rev C C16 C14 BLF0810-180 output Rev C 60 60 BLF0810-180 input Rev C 40 40 MDB169 Dimensions in mm. The components are situated on one side of the copper-clad Rogers 6006 printed-circuit board (εr = 6.15); thickness = 25 mm. The other side is unetched and serves as a ground plane. Fig.15 Component layout for 860 to 900 MHz test circuit. 2003 Jun 12 9 Philips Semiconductors Product specification Base station LDMOS transistors List of components (see Figs 14 and 15) COMPONENT C1, C6, C13, C14, C15, C16, C17 C2 C3 C4, C9, C10, C11, C12 C5, C18 C7, C8 R1 Q1 Q2 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12, L13 L14 L15, L16 Notes DESCRIPTION multilayer ceramic chip capacitor; note 1 multilayer ceramic chip capacitor; note 1 multilayer ceramic chip capacitor; note 1 tantalum capacitor air trimmer capacitor multilayer ceramic chip capacitor potentiometer 7808 voltage regulator BLF0810-180; BLF0810S-180 VALUE 68 pF 330 nF 100 nF 10 µF 5 pF 8.2 pF 1 kΩ DIMENSIONS BLF0810-180/BLF0810S-180 LDMOS transistor stripline; note 2 stripline; note 2 stripline; note 2 stripline; note 2 ferroxcube stripline; note 2 stripline; note 2 stripline; note 2 stripline; note 2 stripline; note 2 stripline; note 2 stripline; note 2 stripline; note 2 stripline; note 2 9.73 × 0.92 mm 1.82 × 9.3 mm 8.15 × 17.9 mm 44 × 0.92 mm 18.45 × 28.3 mm 9.95 × 5.38 mm 37.6 × 3.35 mm 2.36 × 0.92 mm 4.22 × 0.92 mm 5.22 × 0.92 mm 6.47 × 0.92 mm 5.38 × 4.8 mm 2.4 × 0.92 mm 1. American Technical Ceramics type 100A or capacitor of same quality. 2. The striplines are on a double copper-clad Rogers 6006 printed-circuit board (εr = 6.15); thickness = 0.64 mm 2003 Jun 12 10 Philips Semiconductors Product specification Base station LDMOS transistors PACKAGE OUTLINES Flanged LDMOST ceramic package; 2 mounting holes; 2 leads BLF0810-180; BLF0810S-180 SOT502A D A 3 D1 F U1 q C B c 1 L H U2 p w1 M A M B M E1 E A 2 b w2 M C M Q 0 5 scale 10 mm DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT mm inches A 4.72 3.43 0.186 0.135 b 12.83 12.57 c 0.15 0.08 D D1 E 9.50 9.30 E1 9.53 9.25 F 1.14 0.89 H 19.94 18.92 L 5.33 4.32 p 3.38 3.12 Q 1.70 1.45 q 27.94 U1 34.16 33.91 1.345 1.335 U2 9.91 9.65 0.390 0.380 w1 0.25 0.01 w2 0.51 0.02 20.02 19.96 19.61 19.66 0.788 0.786 0.772 0.774 0.505 0.006 0.495 0.003 0.374 0.375 0.366 0.364 0.045 0.785 0.035 0.745 0.210 0.133 0.170 0.123 0.067 1.100 0.057 OUTLINE VERSION SOT502A REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-28 03-01-10 2003 Jun 12 11 Philips Semiconductors Product specification Base station LDMOS transistors BLF0810-180; BLF0810S-180 Earless flanged LDMOST ceramic package; 2 leads SOT502B D A F 3 D1 D U1 c L 1 H U2 E1 E 2 b w2 M D M Q 0 5 scale 10 mm DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT mm inches A 4.72 3.43 0.186 0.135 b 12.83 12.57 c 0.15 0.08 D D1 E 9.50 9.30 E1 9.53 9.25 F 1.14 0.89 H 19.94 18.92 L 5.33 4.32 0.210 0.170 Q 1.70 1.45 U1 20.70 20.45 U2 9.91 9.65 w2 0.25 20.02 19.96 19.61 19.66 0.788 0.786 0.772 0.774 0.505 0.006 0.495 0.003 0.374 0.375 0.366 0.364 0.045 0.785 0.035 0.745 0.067 0.815 0.057 0.805 0.390 0.010 0.380 OUTLINE VERSION SOT502B REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-28 03-01-10 2003 Jun 12 12 Philips Semiconductors Product specification Base station LDMOS transistors DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development BLF0810-180; BLF0810S-180 DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Jun 12 13 Philips Semiconductors Product specification Base station LDMOS transistors NOTES BLF0810-180; BLF0810S-180 2003 Jun 12 14 Philips Semiconductors Product specification Base station LDMOS transistors NOTES BLF0810-180; BLF0810S-180 2003 Jun 12 15 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613524/06/pp16 Date of release: 2003 Jun 12 Document order number: 9397 750 11545