BSP204A

DISCRETE SEMICONDUCTORS DATA SHEET BSP204; BSP204A P-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor FEATURES • Direct interface to C-MOS, TTL, etc. • High-speed switching • No secondary breakdown. DESCRIPTION P-channel enhancement mode vertical D-MOS transistor in a TO-92 variant envelope, intended for use in relay, high-speed and line transformer drivers. PINNING - TO-92 variant (BSP204) PIN 1 2 3 gate drain source DESCRIPTION handbook, halfpage BSP204; BSP204A QUICK REFERENCE DATA SYMBOL −VDS −ID RDS(on) VGS(th) PARAMETER drain-source voltage drain current drain-source on-resistance gate-source threshold voltage DC value −ID = 200 mA −VGS = 10 V −ID = 1 mA VGS = VDS CONDITIONS MAX. 200 250 15 2.8 UNIT V mA Ω V PIN CONFIGURATION 1 d 2 3 g s MAM147 PINNING - TO-92 variant (BSP204A) PIN 1 2 3 gate drain DESCRIPTION source Fig.1 Simplified outline and symbol. April 1995 2 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL −VDS ±VGSO −ID −IDM Ptot Tstg Tj Note PARAMETER drain-source voltage gate-source voltage drain current drain current total power dissipation storage temperature range junction temperature DC value peak value up to Tamb = 25 °C (note 1) CONDITIONS BSP204; BSP204A MIN. − − − − − −65 − MAX. 200 20 250 600 1 150 150 UNIT V V mA mA W °C °C 1. Device mounted on an epoxy printed-circuit board, maximum lead length 4 mm; mounting pad for the drain lead minimum 10 mm x 10 mm. THERMAL RESISTANCE SYMBOL Rth j-a Note 1. Device mounted on an epoxy printed-circuit board, maximum lead length 4 mm; mounting pad for the drain lead minimum 10 mm x 10 mm. PARAMETER from junction to ambient (note 1) VALUE 125 UNIT K/W April 1995 3 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL −V(BR)DSS −IDSS ±IGSS −VGS(th) RDS(on) | Yfs| Ciss PARAMETER drain-source breakdown voltage drain-source leakage current gate-source leakage current gate-source threshold voltage drain-source on-resistance transfer admittance input capacitance CONDITIONS −ID = 10 µA VGS = 0 −VDS = 160 V VGS = 0 ±VGS = 20 V VDS = 0 −ID = 1 mA VGS = VDS −ID = 200 mA −VGS = 10 V −ID = 200 mA −VDS = 25 V −VDS = 25 V −VGS = 0 f = 1 MHz −VDS = 25 V −VGS = 0 f = 1 MHz −VDS = 25 V −VGS = 0 f = 1 MHz −ID = 250 mA −VDD = 50 V −VGS = 0 to 10 V −ID = 250 mA −VDD = 50 V −VGS = 0 to 10 V BSP204; BSP204A MIN. 200 − − 0.8 − 100 − TYP. − − − − 10 200 65 MAX. UNIT − 1 100 2.8 15 − 90 V µA nA V Ω mS pF Coss output capacitance − 20 30 pF Crss feedback capacitance − 6 15 pF Switching times (see Figs 2 and 3) ton turn-on time − 5 10 ns toff turn-off time − 20 30 ns April 1995 4 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP204; BSP204A handbook, halfpage VDD = −50 V handbook, halfpage 10 % INPUT 90 % 0V −10 V ID 50 Ω MBB689 10 % OUTPUT 90 % ton toff MBB690 Fig.2 Switching time test circuit. Fig.3 Input and output waveforms. handbook, halfpage 1.2 MRC238 handbook, halfpage −1 MDA706 Ptot (W) 0.8 ID (A) −0.8 VGS = −10 V −6 V −0.6 −5 V −0.4 0.4 −0.2 −3 V 0 0 50 100 150 200 Tamb (°C) 0 0 −5 −10 −15 −20 −25 VDS (V) −4 V Fig.4 Power derating curve. Fig.5 Typical output characteristics; Tj = 25 °C. April 1995 5 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP204; BSP204A handbook, halfpage −1 MDA707 ID (A) −0.8 −103 handbook, halfpage MDA708 VGS = −10 V −5 V ID (mA) −4 V −0.6 −102 −0.4 −0.2 0 0 −2 −4 −6 −8 −10 VGS (V) −10 8 12 16 20 24 28 RDSon (Ω) Fig.6 Typical transfer characteristic; −VDS = 10 V; Tj = 25 °C. Fig.7 Typical on-resistance as a function of drain current; Tj = 25 °C. handbook, halfpage 160 MDA734 handbook, halfpage 2.5 k 2 MDA710 C (pF) 120 1.5 80 Ciss 1 40 Coss Crss 0 0 −5 −10 −15 −20 −25 VDS (V) 0 −50 0 50 100 Tj (°C) 150 0.5 Fig.9 Fig.8 Typical capacitances as a function of drain-source voltage; VGS = 0; f = 1 MHz; Tj = 25 °C. Temperature coefficient of drain-source on-resistance; R DS ( on ) at T j k = ---------------------------------------------- ; R DS ( on ) at 25 ° C typical RDS(on) at −200 mA/−10 V. April 1995 6 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP204; BSP204A handbook, halfpage 1.1 k 1 MDA711 0.9 0.8 0.7 −50 0 50 100 Tj (°C) 150 Fig.10 Temperature coefficient of gate-source threshold voltage; – V GS ( th ) at T j k = ----------------------------------------------- ; – V GS ( th ) at 25 ° C typical −VGS(th) at −1 mA. April 1995 7 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor PACKAGE OUTLINE Plastic single-ended leaded (through hole) package; 3 leads (on-circle) BSP204; BSP204A SOT54 variant c L2 E d A L b 1 2 D e1 e 3 b1 L1 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 variant REFERENCES IEC JEDEC TO-92 EIAJ SC-43 EUROPEAN PROJECTION ISSUE DATE 97-04-14 A 5.2 5.0 b 0.48 0.40 b1 0.66 0.56 c 0.45 0.40 D 4.8 4.4 d 1.7 1.4 E 4.2 3.6 e 2.54 e1 1.27 L 14.5 12.7 L1(1) max 2.5 L2 max 2.5 April 1995 8 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Application information BSP204; BSP204A This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. April 1995 9 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor NOTES BSP204; BSP204A April 1995 10 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor NOTES BSP204; BSP204A April 1995 11 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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